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TLM Modeling Environment Goes Commercial

TLM Modeling Environment Goes Commercial
by Daniel Payne on 03-20-2014 at 6:00 pm
Categories: EDA, Magillem, STMicroelectronics

The most successful EDA companies typically choose a domain where they have deep knowledge, then serve a few leading-edge customers that are willing to work with a start-up in exchange for early access to that new technology. The theory is that if you can satisfy the leading-edge customer then you can also satisfy the rest of the market segment. Magillemis one such EDA company that has worked closely with STMicroelectronics over the years on ESL tools that use IP-XACTand help manage complexity, interoperability and design re-use for SoC designers. This week Magillem announced something a little bit different, because they have signed an OEM agreement with STMicroelectronics to offer ST’s TLM (Transaction Level Modeling) modeling environment and methodology.

The EDA industry has provided tools to model at a variety of levels, and each for a different purpose:

  • Transistor-level, for SPICE circuit simulation and layout versus schematic checking
  • Gate-level, for functional simulation and fault modeling
  • Cell-level, for collections of transistors and gates
  • Register Transfer Level (RTL), a language based approach using VHDL, Verilog or SystemVerilog. RTL can be automatically synthesized into gate or cell levels.
  • Transaction Level Modeling (TLM), a higher-lever approach to modeling a digital system, where details of communication between modules are separated from the details of the implementation of functional units or of the communication architecture. (Source: Wikipedia)

Magillem already offered five tools for SoC design:

  • Magillem IP-XACT Packager
  • Magillem Platform Assembly
  • Magillem Register View
  • Magillem Generator Studio
  • Magillem Flow Control

This new TLM modeling fills a product gap for Magillem, and will allow SoC designers to build and analyze virtual platforms using SystemC, one of the faster growing segments in EDA today. SystemC is a set of C++ classes and macros which provide an event-driven simulation interface in C++ (Source: Wikipedia). SystemC is a standard defined by Accellera, and Magillem is a board member of Accellera.

Expect more product details and availability to be announced as we get closer to DAC in June. There is a press release at the Magillem site with quotes from Philippe Magarshack, Executive Vice-President and General Manager, Design Enablement and Services STMicroelectronics and Cyril Spasevski, Chair and CTO of Magillem. You can also visit with Magillem at CHIPEX in Tel Aviv, Israel at the end of April.

lang: en_US

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Handel Jones on FD-SOI vs FinFET

Handel Jones on FD-SOI vs FinFET
by Paul McLellan on 03-20-2014 at 1:27 am
Categories: FD-SOI, Foundries, STMicroelectronics

Handel Jones has a new white-paper out titled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel has done an in-depth analysis of the wafer and die costs of the various approaches, bulk planar (what we have been doing up to now), FD-SOI and FinFET. The analysis takes into account depreciation, equipment maintenance, direct/indirect labor, facilities, wafer cost, consumables, monitor wafers and line yield.


It turns out that at 28nm, FD-SOI is already marginally cheaper than bulk planar CMOS. It has a smaller number of masks and fewer processing steps. The difference is a bit bigger at 20nm. At 16nm the comparison with FinFET shows that FD-SOI is a lot cheaper. See the diagram above.


He then goes on to analyze die costs, taking into account gross die per wafer and yield. That results in the graph above. The money quote is that:At 14nm/16nm, the FD-SOI die cost for a 100mm[SUP]2[/SUP] die is 28.2% lower than the bulk FinFET die cost and has higher yield. The leakage of FD-SOI devices is projected to be comparable to that of FinFET devices.

For the very highest performance SoCs, then FinFET is presumably worth the cost. But for anything not on the bleeding edge then FD-SOI might be a more cost-effective solution. FD-SOI, like FinFET, has much lower leakage than bulk, but FinFET can have issues with dynamic power due to the high gate capacitance.

STMicroelectronics has been the trailblazer for FD-SOI and has working products in 28nm. It is not a theoretical alternative to FinFET, it is real. The whole supply chain is starting to fall into place.

At EDPS in Monterey on 17th/18th April I will be talking about FD-SOI in more depth. My working title is Praise FD-SOI, slag FinFETs but maybe I’ll find something a little more politically acceptable. There are also presentations that afternoon on FinFETs (praise FinFETs, slag FD-SOI perhaps) and on 3D-IC (praise TSVs, slag Moore’s Law completely). Come along and watch the wrestling match. Moore’s Law as we used to know it is over: 28nm won. It is not just cheaper than every process that came before it, it is cheaper than every process that is going to come after it. Details on EDPS are here.

The final conclusions of the white-paper:

  • at 28nm and 20nm, the lower power consumption and higher performance of FD-SOI compared to planar bulk CMOS gives major competitive advantages to FD-SOI in high volume portable applications.
  • the lower cost of FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI for high volume applications at this technology node.

Handel’s white-paper is here.


More articles by Paul McLellan…

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Sewn open: Arduino and soft electronics

Sewn open: Arduino and soft electronics
by Don Dingee on 03-19-2014 at 3:00 pm
Categories: Foundries

As several other recent threads on SemiWiki have pointed out, the term “wearables” is a bit amorphous right now. The most recognizable wearable endeavors so far are the smartwatch and fitness band, but these are far from the only categories of interest.

There is another area of wearable wonder beginning to get attention: clothing, which has drawn the interest of researchers, makers, and moms alike. The endgame as many see it is smart clothing: the weaving of electronics, sensors, and conventional fabrics into something called e-textiles. However, while athletes, soldiers, and other niches may get sensor-impregnated jerseys sooner, affordable clothing based on exotic advanced fabrics for most consumers may still be 20 or 30 years away by some estimates.

Right now, we have these anything-but-soft computing structures – chips, circuit boards, displays, switches – adaptable for some clothing applications. Still missing are some key elements, most notably power in the form of energy harvesting or smaller and denser batteries. The influence of water-based washing machines and their adverse effect on most electronics also looms large.

How do we cross this gap? It’s not all about advanced R&D; these types of challenges are well suited for experimentation and the imagination of makers. Several Arduino-compatible maker modules – all based on Atmel microcontrollers – have jumped in to the fray, showing how “soft electronics” can help create solutions.

photo courtesy Becky Stern

Maybe I’ve built one or two too many harness assemblies using expensive, mil-spec circular connectors, but the fascinating thing to me is what makes all these boards wearable. Small size is nice, but anybody knows a project needs wiring, right? You’ll notice the large plated holes on the first several offerings: these are eyelets for conductive thread, literally intended to sew these boards to other components like fabric pushbuttons. Many projects also use snaps, similar to 9V battery connections, to disconnect boards for conventional washing of the garment.

The other side of this is the software. One of the attractive features of Arduino is the IDE, real live C-style programming simplified for the masses, with functions designed to perform I/O on the Atmel MCU. Code is edited on a PC or Mac, and compiled into a sketch and uploaded to the board. There are so many examples of code for Arduino maker modules out there available in open source, it makes it easy to find and integrate functions quickly.

If that all sounds crazy, consider the pioneer for this is Leah Buechley of the MIT Media Lab, one of the thought leaders of the maker movement and an expert on e-textiles. She is the brain behind the LilyPad, the original 2” diameter Arduino wearable circa 2007 commercialized through SparkFun, with the most recent version featuring the ATmega32u4 and native USB.

Adafruit took the next steps with two wearable boards. FLORA is slightly smaller than the LilyPad and retains the same familiar circular profile and ATmega32u4 MCU. GEMMA goes even smaller, 1.1” in diameter, packing an ATtiny85 on board with a USB connection for easy development.


Not to be outdone by circles, squares and rectangles have recently come back into form. SquareWear 2.0 comes in two versions, the 1.7” square variant with a coin cell socket onboard, both including the ATmega328 MCU with simulated USB, high current MOSFET ports, a light sensor, and a temperature sensor. Seeed grabbed the ATmega32u4 and designed it into the Xadow, a tiny 1” x 0.8” expandable unit with integrated flat cable connectors for daisy chaining.


These aren’t just toys for creating flashing LEDs; there is no shortage of sensors and connectivity, including displays, GPS, Bluetooth, and more compatible with these wearable maker modules. Their popularity is growing: Becky Stern of Adafruit claims there are over 10,000 units of FLORA shipped so far, and they are the darlings of maker faire fashion shows and hackathons.

Besides the upside for makers, maybe this sewing angle will finally allow us to explain electronics to our moms, after all. Until we get to the fulfilled flexible future of e-textiles and more advanced technology, the conductive thread of soft electronics will stitch together creative ideas using somewhat familiar tiny modules with today’s microcontrollers.

lang: en_US

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Triple Patterning

Triple Patterning
by Paul McLellan on 03-19-2014 at 1:00 pm
Categories: EDA, Foundries

As you can’t have failed to notice by now, 28nm is the last process node that does not require double patterning. At 20nm and below, at least some layers require double patterning. The tightest spacing is typically not the transistors but the local interconnect and, sometimes, metal 1.


In the litho world they call double patterning LELE. This stands for litho-etch-litho-etch which describes the steps taken. Using the first mask, half the polygons are patterned and then etched. Then using the second mask, the other half of the polygons are patterned and then etched. This imposes some restrictions on what can be put on the mask, since it has to be so-called two-colorable, meaning the polygons can be split into two masks such that there each mask has polygons that are sufficiently far apart (there are lots of articles on SemiWiki about the details of this). One problem with LELE is that the second mask is registered onto the first pattern using the fiducial marks (like any other mask) and so there is a level of misalignment that the design must be able to cope with, approximately 10nm, so you can’t actually double the density using double patterning.

So what is beyond double patterning?

Three things:

  • triple patterning called LELELE in the lithography world
  • self-aligned double patterning (SADP) also sometimes called sidewall image transfer (SIT)
  • EUV, 14nm wavelength instead of 193nm, so we can go back to single exposure

EUV isn’t happening for 10nm unless either there is a miracle in improvement of the power of the light source (and some other problems are solved). Or 10nm slips out several years. Both are possible. The economics of 10nm are somewhere between unknown and dubious.


Triple patterning is pretty much the same as double patterning except that the polygons are partitioned onto three masks. The constraints on the design are different, to ensure this can be done. The big advantage of triple patterning over double is that it is a lot denser. Not three times as dense since the 3 masks will still have some misalignment. In fact because with 3 masks the alignment problems are worse (the distances are tighter) it looks like 3-4nm misalignment is the maximum, which is very hard to achieve.


SADP/SIT removes the potential misalignment between the multiple masks. First a mask is used to put down a temporary sacrificial structure called a mandrel. Then sidewalls are constructed on the sides of the mandrel. The mandrel is removed. This is now double patterning but due to the method of construction there was never a time when a mask was critically aligned on the previous one so the misalignment is removed. Sometimes this is also called pitch doubling since the sidewalls are half the pitch of the mandrels.

This SADP/SIT process can be repeated, using the sidewalls as new mandrels and constructing new sidewalls. This gives self aligned quadruple patterning. With enough process steps (and money) you can get down to 7nm like this without EUV.

One of the biggest decisions in process architecture is to decide what the pitch for various layers should be. The most critical pitch is that for local interconnect and metal 1 since these have major impact on the density of memories and standard cells. Too big a pitch and the process is not competitive since the area is to large. Too tight a pitch and the areas are small but the process is very expensive due to all the extra process steps and masks required. This is why there is so much attention on 14/16nm on what the metal 1 pitch is. An additional complication is that with these two layers it is not possible to live with 1D structures (lay down a grating and then use a cut mask to divide it up) since it is essential to be able to run in both the X and Y directions.

For 10nm it looks like SADP/SIT is needed for a few layers and then double patterning above that. Triple patterning seems like it maybe too expensive to be worth it.


More articles by Paul McLellan…

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Aldec the leader in DO254

Aldec the leader in DO254
by Luke Miller on 03-19-2014 at 12:00 pm
Categories: Aldec, EDA, FPGA, Xilinx

I am convinced after studying out the matter, that Aldec is one of the leaders in DO254 certification. As you listen and read the news as I do about flight MA-370, you keep theorizing and wondering. This is a good time to introduce the reader to the seriousness of flight worthy electronics and the arduous process to achieve certification. First and foremost I recommend if your company is serious about designing airborne electronics that you attend the Aldec D0254 Training conference. Three chucked full days, of the seriousness of DO254. Under $2k, this is a bargain. The three day high level objectives are shown below.


I want to briefly go over some Aldec tools, process and hardware that will assist even the fledgling company entertaining the idea of setting out to design products that require DO254/FAA type certification. Buckle your seat belt, you can do this with Aldec without having to acquire a company! First let’s identify the challenge. Below is a very simple drawing with an FPGA, the FPGA could be any FPGA, I chose Xilinx since I am more familiar with them.

The processing and algorithms in the FPGA are not the challenge. Let’s pretend that each status input is over 8 IO lines, and each output control is over 8 IO lines. From a safety critical point of view, what happens if any inputs bits are opened? Shorted? Missing state cases? Could that cause the rudder to be stuck down? Yikes… You get the idea. So at some point you must verify in hardware every single IO does what it is supposed to do and not supposed to do. It also requires that ‘errors’ on inputs result to a ‘safe’ output condition. You still need to verify the guts in the FPGA do exactly what they are supposed to do. Now picture all the systems in a Boeing 777! (Though the standard did not exist then) That is not trivial, and I would estimate 25% of the budget is given to electronics design and 75% to test and verification.

Aldec has an awesome video on DO-254 and there solution for FPGA target in level testing. Watch it right now if you can, as it would take me another few pages to explain all of it. Aldec also has white papers on the topic as well, all worth reading and studying.

To plagiarize from Aldec, “DO-254/CTS™ is a certifiable at-speed FPGA level in-target testing system for Levels A and B DO-254 designs.” When designing firmware for an FPGA you have a testbench or testbed. The testbench will have input stimuli and you capture the results and compare. Usually when hardware comes you redesign most of the testbed work so it can work on hardware. This is no place to live when working DO254, and Aldec’s DO254/CTS allows you an evaluation platform ASAP so you can reuse your test vectors and pay attention to the important things which are the safety critical tests. Since the Aldec solution uses real hardware, it runs in real time as RTL simulation is slow an painful, and eats up precious time and $$. Below is a nice diagram that captures the system. I encourage to get over to the Aldec website and attend the training in May. Until then…

lang: en_US

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Xilinx’s UltraScale vs Arria 10 – Non dolet, Paete

Xilinx’s UltraScale vs Arria 10 – Non dolet, Paete
by Luke Miller on 03-18-2014 at 9:30 pm
Categories: FPGA, Xilinx

The DSP48E2 (I do not come up with these names… Could have named it a multiplier thingy) in the Xilinx 20nm UltraScale family (I do not come up with these names… Could of named it Virtex-8, or Luke-8) is simply amazing. Today was good, as I began playing with UltraScale tools and seeing how the DSP checks out. I also encourage you to check out the Altera 20nm node and you will once again see quite a difference between the families. In fact Altera says they are ‘redefining the midrange’ at the 20nm node… and for the Stratix-10, ‘Delivering unimaginable performance’. I am holding back on that one, in fact dear reader you could add in the punch line here. I was humming ‘it’s a small world after all’, picturing tattoo from Fantasy Island, yelling De FPGA, De FPGA Boss!

Xilinx claims that the complex multiplier in the 20nm UltraScale will need ½ the DSP resources it needed in the 28nm node. That is a big deal, as in my field, RADAR/EW complex multiplication is important. For example, the wife asks me to cut her hair. That is input A, input B is I keep saying no but decide to do it. The output C is a very complex situation that involves sobbing, and that is me sobbing. That is a true story by the way (No I didn’t cry, I embellished a bit), and it turned out exactly like I said it would. My dear, dear Manly reader, may I suggest you never cut your wife’s hair, ever. My dear, dear feminine reader, do not ask your man to style your hair, you will really regret it and will take 3 months to forgive your guy. I know, pray for my family.

In the UltraScale 20nm Kintex 115, we have 5500 DSP. There are 3600 DSP in the largest 28nm Virtex-7 FPGA, so you say ‘well that is only a 1900 DSP increase.’ I say you spoiled designer you! Remember the Virtex-2 Pro Days, with a whopping 232 18×18 multipliers, see how you are spoiled? Ok, the 1900 DSP increase in actually much more than that when you factor in clock frequency, bit widths, and efficiency. For most configurations, the complex multiplier that used 8 DSP slices in 28nm will only need 4 DSP in UltraScale 20nm. That is 1900 + 2X GMACs gained when performing complex multiplies.

For example, if you wanted a system that needed 1375 18×27 complex multiplies you could do this in one UltraScale Kintex-115. Altera’s Arria-10, would need 1.63 Arria’s. And I know it is very hard to purchase a 0.63 FPGA so I think you need 2 Altera FPGAs. Altera’s Data sheet says you need 2 Variable DSP’s for one complex multiply and there are 1678 Variable DSPs, that means you can only have 839 complex multiplies. 1375/839 = 1.63.

Wait… Now wait! Hold, hold…hold.. On here… in a George Bailey voice. This is for an 18×27 Complex Multiply, and the 1.63 Arria’s was for 18×19…Well I was conservative, and I did not even discuss gigabit transceivers. But the Xilinx KU115 can move 2 Terabits over 64 x 16 gb/s Transceivers. Arria-10, not so much with 48 x 17.4 gb/s transceivers = 1.67 Terabits.

Xilinx KU115 = 5520 DSP x 741 MHz x 2 = 8180 GMACs
Arria10 GX660 = 3356 DSP x 500 MHz x 2 = 3356 GMACs

Arria base multipliers are 18×19 and Xilinx is 18×27, this means as in most systems you will need to use more multipliers to achieve most applications. How many systems do you know that use 18×19 for filter applications? Most systems have digital processing gain that effectively use the Xilinx DSP slice. Xilinx’s DSP is close to 3X better than Altera.

By the way a history lesson from Wikipedia, reader beware, the Name Arria:

“Arria (also Arria Major) was a woman in ancient Rome. Her husband Caecina Paetus was ordered by the emperor Claudius to commit suicide for his part in a rebellion but was not capable of forcing himself to do so. Arria wrenched the dagger from him and stabbed herself, then returned it to her husband, telling him that it didn’t hurt (“Non dolet, Paete!”). Her story was recorded in the letters of Pliny the Younger, who obtained his information from Arria’s granddaughter, Fannia.

Ok..Right… Let’s name an FPGA after a lady who stabbed herself to prove it didn’t hurt to her husband. Sounds like me cutting my wife’s hair! – Non dolet, Paete.

Anyways, Xilinx of course has all your FPGA ranges covered, they call it the ‘low end series’ (I assure you I do not come up with these names, Low End? Arria? How about Super Duper Value FPGA?). Looking at Xilinx’s 28nm, 20nm, there is no other device that comes close to it. So you are using Altera why? Can someone explain to me where the measurable advantage is? How about TI’s DSP chips, why? You can program Xilinx’s FPGAs using C/C++ very easily which excellent QoR, and Floating Point for Xilinx FPGAs are trivial. Considering GPU’s? Think again about using FPGAs SEU, Power and Reliability are many times better than GPUs. Xilinx clearly is the leader in the FPGA realm and it did not happen by accident. Check them out today, you will not be disappointed.

lang: en_US

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Atmel on Tour at AT&T Park

Atmel on Tour at AT&T Park
by Paul McLellan on 03-18-2014 at 5:02 pm
Categories: Foundries

OK, it’s not exactly AT&T park…it’s the parking lot. But they have a huge semi loaded up with lots of cool Atmel stuff to show off some of the things that their customers are doing with their microcontrollers and display technology, primarily focused on the internet of things (IoT). I went down to check it out, which would have been a lot easier before I moved house since they are a few hundred yards from my old place. They will be in Napa on 23-242th March and then Las Vegas on 26th. There are lots more cities too.


First up is one of the smart watches (coincidentally Google just announced their entrance into this market today too). It contains two Atmel microcontrollers, one ARM Cortex to do the work and another 8-bit AVR microcontroller to handle I/O and to wake up the application processor when there is work to be done. It also has a wireless charger (on the left) which is a good idea given that the watch is waterproof and so the case can be completely sealed.

Next up was some Philips technology for controlling dozens of lights for color and brightness from an iPad. Each bulb (actually an LED or a strip of LEDs) has a Zigbee mesh network microcontroller and can vary its color across the spectrum.


Then a Black and Decker cordless drill. One problem companies in the power tool business have is that they would like their tools to only work with their batteries. They obviously have a financial interest in doing this but it is a huge liability problem too. Their products tend to be build overseas and sometimes the designs get stolen and batteries with crummy cells or electronics are sold as genuine. And it is Black and Decker that gets sued when one of these catches fire, which is a real issue with battery control. The bigger the battery, the bigger the problem. In fact it is one of the things that Tesla had to focus on to build power packs the size they need using the same lithium-ion technology used in cellphones, laptops and cameras. Using a chip that costs well under $1 with Atmel’s security software it is possible to make batteries that authenticate. They communicate over the power lines when the battery is changed and if the authentication fails with either the drill or the charger then it simply will not work. Some of the inkjet printer manufacturers have started to do this too, to ensure that only genuine cartridges are used, since their business model depends on cheap printers and making money on ink. Putting up the cost of the printer cuts their market share a lot but not selling ink means they can’t make money.


Finally a technology I’ve seen before, which is Atmel’s flexible display technology called Xsense. The touchscreens look exactly like the transparencies we used to use on overhead projectors, although actually a bit thinner. They can be flexed in use although the initial applications seem to tend more towards being able to build screens that are not flat: watches that wrap around your wrist, curved tablets and so on.


They also had a 3-D printer. I’ve written before how Atmel has over 90% market share of the microcontrollers for this market. As the prices come down, these are clearly going to get much more widely available. The one they had printed in plastic (you can also get them that print metal and how about this one printing a house out of concrete, in 24 hours).

Later there was a panel session on Internet of things with people from Atmel, ARM, Humavox (wierless charging) and August (IoT door locks). I won’t try and describe the whole panel, this blog is already too long. The most interesting aspect was that everyone was very concerned about security and privacy. After all, if you control the door lock through your smartphone you want to make sure nobody else does, and you probably don’t want just anyone to know all the times at which you come and go. Especially if they can correlate that with where your self-driving car took you, who you called and so on. As more and more data ends up in the cloud, this will be a bigger and bigger problem. There was also a worry about small companies being taken over by the likes of large ones: you may not care that Google knows the temperature in your living room, but you probably do care if they know everything above and can sell that information to monetize it.

Full details of Atmel’s Tech on Tour are here.


More articles by Paul McLellan…

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Social Media at Carbon Design Systems

Social Media at Carbon Design Systems
by Daniel Payne on 03-18-2014 at 11:12 am
Categories: EDA

Started in 2002 Carbon Design Systems has ESL (Electronic System Level) modeling and validation tools for complex SoC design. With their software you can:

  • Perform system level model generation of existing and 3rd party IP directly from RTL for use in any virtual platform
  • Do performance analysis & optimization of SoC architectures
  • Enable pre-silicon firmware debug

Continue reading “Social Media at Carbon Design Systems”

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Mentor U2U Is On April 10th

Mentor U2U Is On April 10th
by Paul McLellan on 03-17-2014 at 7:19 pm
Categories: EDA, Siemens EDA

If you are a Mentor user, U2U, the Mentor User group is coming up on April 10th. This is an all day event at the DoubleTree. The event is free. Registration starts at 8am and the agenda itself starts at 9am. There is a reception from 5-6pm in the evening.

There are three keynotes. At 9am: Wally Rhines, CEO of Mentor. The Big Squeeze. For decades, we’ve known it was coming and now it’s here. Moore’s Law—which is really just a special case of the “learning curve”—can no longer drive the 30% per year reduction in cost per transistor, beginning with the 20/16/14 nm generation. Either we find innovations beyond just shrinking feature sizes and increasing wafer diameter or we slow our progress down the learning curve, introducing innovative new electronic capabilities at a slower rate than in the past. There are lots of alternatives, including a reduction in profitability of the members of the supply chain, to keep the progress continuing at the same rate as the last fifty years.

At 10am: Ashok Krishnamoorthy, the chief technologist at Oracle (the part that used to be Sun Microsystems). Optical Interconnects at a Turning Point – The Opportunity and Prospects for Silicon as a Photonics Enabler. Interconnect will play a major role in overall system performance and energy consumption for future computing systems. Current optical links can provide the required bandwidth, but are relatively expensive and power-hungry. VCSEL-based optical modules can improve the situation greatly, and will help optical interconnects penetrate deeper into computing systems. Recent advances in high-density, ultra-low energy silicon photonic links are likely to make them the preferred solution in the long term as density, bandwidth, and energy efficiency are jointly optimized.

At 1pm: Shawn Han, VP Foundry Marketing at Samsung. Solutions to Smart Mobile Devices. Samsung have done a great job in becoming a real force in foundry, most famously making most of Apple’s Ax chips. Expect them to be come even more of a force at 16nm. This is billed as a “special session” rather than a keynote so I have no idea what to expect.

Outside the keynotes, the day is organized into 8 parallel tracks: Calibre I and II, CustomIC/AMS, Place & Route, Silicon Test and Yield Analysis, Functional Verifications, PADS, PCB.

Some talks that look especially interesting looking are:

  • How to achieve fast power and ground analysis at the full chip level (Broadcom)
  • How to design and verify silicon photonics components (University of British Columbia)
  • How to take advantage of the TSMC9000 IP reliability program (TSMC Technology)
  • Achieving required power, performance, area (PPA) on ARM cores (ARM)
  • How Sherlock Holmes and Dr. Watson Track Down a Yield Limiter (Aptina Imaging)

The full detailed agenda is here(pdf). Free registration is here.


More articles by Paul McLellan…