SemiWiki – Page 836 – The Open Forum for Semiconductor Professionals

October 2, 2013June 14, 2019

Architecture-level Power Modeling Methodology at Samsung

Architecture-level Power Modeling Methodology at Samsung
by Daniel Payne on 10-02-2013 at 10:58 am
Categories: EDA

At DAC this year there was a presentation from Samsung titled, “Profile-based Architecture Power Modeling Methodology for AP/SoC Product”. I’ve been using Samsung Smart Phones for the past four generations, so was very curious about how they have managed to improve the average battery life from less than one business day to about 1.5 days now while dramatically increasing both screen size and CPU/GPU metrics.
Continue reading “Architecture-level Power Modeling Methodology at Samsung”

October 1, 2013June 14, 2019

Sequential Equivalence Checking with Jasper

Sequential Equivalence Checking with Jasper
by Paul McLellan on 10-01-2013 at 6:15 pm
Categories: EDA

When new restaurants open they sometimes have what is called a ‘soft opening’ where they open a few days earlier than the official opening night. They are less busy since nobody knows they are open yet, maybe the whole menu isn’t available and expectations may be lower. Of course, Broadway productions also often open off-Broadway (although that usually means a long way from Broadway these days, like Chicago). And anyone who has ever raised money for a startup knows that you don’t do the first run-through of your pitch with a big name like Sequoia. You polish it with a couple of people who are not likely to invest but at least are prepared to spend the time with you.

Of course EDA products often have soft openings too, sometimes known as beta-testing. If this is done properly then a handful of lead customers use the product, help debug it, and hopefully show up to praise it in the official launch. I’ve said before that one of the hardest problems in EDA these days is getting test data to test your new tool. Leading edge companies are not going to send you their latest microprocessor or modem. Or any 20nm design for that matter. It is not just a data problem, you have to solve a problem that a customer really feels pain about, or never mind the data they won’t give you the time. However, somehow you need both data and engineers to test a state-of-the-art tool that solves a critical problem. In EDA anything else won’t sell anyway, so why bother to develop it.

One big problem is verifying RTL to RTL, known as sequential equivalence checking or SEC. Combinational equivalence checking (“normal” equivalence checking) assumes that all the registers in both sets of RTL always hold the same values. In some cases they may even assume the registers are named the same. Perhaps they can cope with some simple cases such as register retiming. Here logic is moved from after a register to before (or v.v.) to balance timing during synthesis; if you move an inverter then the register value is inverted, but then it is always inverted so not too hard to cope with. This also copes fine with the type of clock gating added automatically in synthesis: if the register value is not going to change (usually because the old value is being recirculated) then don’t clock the register instead (and take out the unused muxes).

SEC handles more complex cases, where the register values might not always match. Why would you want to do something like that? The biggest reason these days is power. Isn’t power always the biggest reason in any SoC today? It can also be architectural optimization. But the main reason for doing architectural optimization is power, so I repeat myself.

I mentioned one case where you might not clock a register, which is when you can detect the value is not going to change. In effect, it already holds the “right” value. But another more subtle case is when you can detect that the value is not going to get used downstream. In that case you can avoid clocking the register, but now it holds a “wrong” value. But that doesn’t matter since the wrong value goes straight into a multiplexor (say) that selects some other value and you can know that the wrong value will never be seen. If you can see that the value of the register is only used occasionally then a lot of power can be saved by only clocking in the value when it is about to be used.

You can further reduce power. If a register is not gated on this clock cycle and feeds another register, then it does not need to be gated on the next clock cycle since the old value is already correct. This requires adding flops to the clock nets (also a change in sequential behavior) to capture whether the previous stage was clocked the cycle before. There are other cases like this too, but you get the idea. A lot of this optimization is done by hand, but there are also at least 2 or 3 automated solutions that cover some of the cases (not from Jasper, they are focused on formal verification of designs and are not too concerned about how you got there).

If this sounds like it might generate a lot of weird corner cases then you are right. One technology is especially good with corner cases though: formal verification. Jaspers SEC App can handle these cases and prove you didn’t get them wrong and let an occasion slip through where the value is used but the register is not clocked. But it’s an App that doesn’t exist yet except off-Broadway.

Joe Hupcey, director of product development at Jasper has a blog entry showing in a more detail just how the SEC App can be used to verify that power optimizations only reduce power and don’t screw up the design. The blog is here.

Vigyan Signal of Oski (who are specialists in performing formal verification as a service and generally helping customers with formal verification methodology) has a video about using the SEC App with a lot of practical details about flow and methodology. It is less than 8 minutes long.

Jasper’s User Group is October 22-23rd in Cupertino. I’m sure there will be more on SEC there. Indeed, it is second on the list of topics that will be covered. More details and to register are here or click on the banner below.

October 1, 2013June 14, 2019

ST Endorses PowerArtist with ARM Cores & FDSOI libs

ST Endorses PowerArtist with ARM Cores & FDSOI libs
by Pawan Fangaria on 10-01-2013 at 12:00 pm
Categories: Ansys, Inc., EDA

It was an interesting webinar I attended, presented by STMicroelectronicson how they are benefited in power saving and thermal dissipation by using FDSOI technology and also by using PowerArtist in their design. So, it’s an advantage from both sides – semiconductor technology and semiconductor design tool. It’s worth attending the short webinar of about 30-40 minutes, presented by Anne Merlande of ST in a very simplistic way. One of the attractions of the webinar is an exciting video which speaks about the advantages of FDSOI technology over bulk architecture along with some simple experiments; FDSOI is simpler and provides significantly improved device performance, power efficiency and lower temperature, ideal for smart phones that have longer battery life and cooler to handle.

Now let’s see ST’s experience with Apache’sPowerArtist and ARMCores. I am just outlining some of these; details can be looked at in the webinar. I don’t have to mention much about ST’s long relationship (of about 17 years) with ARM and ST being lead partner with ARM on A15 and A57. Recent focus has been on low power and high performance.

ST uses PowerArtist at RTL level to determine the best architecture and implementation strategy to gain in dynamic power saving, thermal and power integrity analysis, SMPS sizing and power optimization of ST IPs embedded into ST ARM sub-systems. By doing this, they are able to significantly save time in attaining power sign-off stage. How about accuracy? Let’s see.

[The flow used at ST for PowerArtist calibration]

[PowerArtist calibration on Dual Cortex-A9 sub-system (A9ss)]

Block level accuracy between PowerArtist on A9ss and ST sign-off was compared at all 3 stages – i) post-layout netlist using SPEF, ii) post-layout netlist using PACE and iii) RTL using PACE.

[Correlation data at post-layout netlist+SPEF, post-layout netlist+PACE and RTL+PACE stages]

Similarly, ST verified block level accuracy between PowerArtist on Dual Cortex-A15 sub-system at RTL using A9ss-PACE and post-placed netlist. It is observed that PowerArtist accuracy at RTL level is within acceptable limits. Clocktree inaccuracy is relatively higher as this is good for timing but bad for dynamic power. Correct PACE (Power Artist Calibrator and Estimator) models provide correct accuracy levels.

Power integrity patterns are developed by running simulation at RTL level and adjusting power window to identify the best window to get the maximum current slope. This eliminates the need of gate level simulation.

By using PowerArtist’s power exploration capabilities, ST is able to detect power bugs early in the cycle and save more than 30% power.

[A15ss low-power use case dynamic power]

PowerArtist enables power convergence and tracking of power along with RTL development.

Overall, PowerArtist has been seen to significantly shorten the design cycle with its power prediction and verification capabilities at RTL level, accurately and efficiently. Power bugs can be identified and corrected at RTL level, thus improving design (chip) reliability. It’s worth attending the webinar and knowing more.

September 30, 2013July 18, 2025

Stick to the script for repeatable FPGA-based prototyping

Stick to the script for repeatable FPGA-based prototyping
by Don Dingee on 09-30-2013 at 7:00 pm
Categories: EDA, Synopsys

70% of today’s ASIC and SoC designs are being prototyped on FPGAs. Everybody knows that. But, did you know that automating the process of converting what could be thousands of ASIC “golden” files into FPGA-friendly versions can mean big savings in a large design?

Continue reading “Stick to the script for repeatable FPGA-based prototyping”

September 30, 2013June 14, 2019

How to Quickly Optimize BEOL Process at Your Desk?

How to Quickly Optimize BEOL Process at Your Desk?
by Pawan Fangaria on 09-30-2013 at 11:00 am
Categories: Coventor, EDA

Engineers are always looking to improve the efficiency of how they work, but don’t want to sacrifice accuracy in the process. This is true in the world of semiconductor process development, where traditional build-and-test cycles are both time and resource intensive. But what if there was a way to do certain steps in a ‘virtual’ way, at your desktop, through predictive modeling technologies? This can only be done if you are able to accurately predict the structural behavioral sensitivity to process variation observed in the fab.

In this article I will focus on the copper interconnect formation in the BEOL (Back-End-Of-Line). At 16nm and below, Etch and PVD (Physical Vapor Deposition) metallization are left with extremely narrow process windows, and at the same time there is pressure on analytical resources and time-to-market requirements. There is a need for a robust automated process modeling platform which can precisely do variation analysis and accurately predict the design model.

Being fascinated with SEMulator3D tool for process modeling, I looked further into a BEOL Metallization whitepaperbased on this platform, written by Ryan J Patz at Coventor. This is an informative paper about how SEMulator3D enables process interaction characterization (as opposed to individual unit process optimization) and how Virtual Metrology and cross-section capability can give more information per run as compared to trial-and-error silicon testing. Using virtual fabrication to optimize complex process flows for large design areas (e.g. complete SRAM block) before committing silicon can help reduce time-to-market and lower technology development costs significantly.

Patz demonstrated the new capabilities in SEMulator3D 2013 through an experiment of M1-V1-M2 via chain integration. The design features a Trench First Metal Hard-Mask flow with a Self-Aligned Via scheme (TFMHM-SAV) for V1-M2 with double patterning for the M2 level. The paper highlights how SEMulator3D 2013 uses its Virtual Metrology capability to perform standard in-fab measurements and out-of-fab destructive physical characterization. We will see how SEMulator3D Expeditor, a tool for automating a large number of runs, helps in investigating BEOL process sensitivity to lithography and process variation.

[M1 baseline after a) Lithography, b) Mask open, c) BLok open, d) Copper barrier seed (CuBS), e) CMP]

[V1-M2 baseline after a) M2-L1 lithography, b) M2-L2 lithography, c) V1 partial etch, d) BLok open, e) CuBS]

The above figures show the nominal integrated process. The M1-V1-M2 dual damascene baseline flow used Litho-Etch-Litho-Etch (LELE) double patterning for the M2 level and the model was run through V1-M2 metallization and CMP.

The Ta/TaN Liner deposition needs to be conformal and continuous for device yield and reliability. The SEMulator3D platform allows the user to control liner thickness, conformality (thickness/overhang ratio) and overhang angle to study the deposition process. Virtual Metrology was used to measure M2 CD (critical dimension) and Cu cross-section area to quantify the impact of Liner Conformality on the device. An 81-way experiment was completed in about 3 hours on a single 4 core CPU machine. Such a comprehensive in-fab study will likely be prohibited by wafer and SEM (Scanning Electron Microscope) resource requirements.

[Ta/TaN liner thickness (nm) and TiN etch ratio profile impact on M2 space CD – a) 5/5, 0.025, b) 3/3, 0.05, c) 5/5, 0.05, d) 5/5, 0.1, e) M2 space CD dependence on liner thickness and TiN etch ratio]

In the above figure, images a, c and d show the impact of the TiN etch ratio (selectivity) on liner profile. Images b and c show bread-loaf formation as the liner thickness increases. This learning could be used in-fab to optimize the post etch TiN profile and thickness for maximum liner deposition process margin.

[% of Cu in M2 trench at liner thickness/overhang ratio of a) 1, b) 3 and c) 5; d) % of Cu in M2 trench dependence on liner thickness/overhang ratio and thickness]

The above figure shows that the M2 Cu cross-section area as a percentage of total metal is sensitive to both liner conformality (thickness/overhang ratio) and total thickness. The percentage of Cu in the 32nm trench can be substantially increased with a more conformal liner. In the same figure, the blue marker at the bottom of the M2 trench in image a highlights discontinuous liner coverage and direct contact of Cu and low-k. This interface was detected automatically during the model build.

[Dielectric materials are not shown. Cu diffusion during subsequent processing in a1) 0nm with material view, a2) 0nm with electrical new view, b) 5nm, c) 10nm, d) 15nm]

The above figure shows the risk of a Cu diffusion at a Cu/low-k interface during subsequent processing which can result in shorting. In the above figure, each electrical net is represented by a unique color (which can be counted by Virtual Metrology). The image d with largest Cu diffusion shows that the electrical nets are shorted and represented in a single color.

[Cu void formation at CuBS thickness/overhang ratio of a) 1, b) 3 and c) 5; Ta/TaN thickness=5/5nm, thickness/overhang=3, CuBS top layer thickness=3.5nm. d) Cu voiding area over a single V1-M1 contact for 81 runs]

An experiment was run using the Coventor Expeditor tool to characterize the process window for continuous liner and Cu seed layers. Image a in the above figure illustrates void formation due to a discontinuous Cu seed layer. The Cu/Void interface area is not possible to measure in-fab but it is possible to measure with Virtual Metrology and the results are in the above chart. The results suggest overhang during Cu seed can help ensure a continuous seed layer.

[Liner thickness/Overhang ratio and Via lithography misalignment of a) 1 and -5nm, b) 3 and -5nm and c) 3 and +5nm. V1-M1 interface area as a function of liner thickness/overhang ratio]

Another important study was the sensitivity of Line-end self-aligned Viascontact area to process variation. The above figure shows that liner conformality and via lithography misalignment have a strong impact on the V1-M1 interface area, specifically at a thickness/overhang ratio of 1. Characterization of constructs like this example can help determine design rules and weak points in the device to drive development priorities.

It’s interesting to note how the unit processes interactions impact the final device. This realization is an important step towards understanding how to enable APC (Automated Process Control). For example, if M1 post etch CD is small, it may require a different M2 overlay tolerance or M2 TiN thickness to ensure electrical performance is in spec.

This whitepaperis a must read for process engineers, chip designers and others associated with the semiconductor industry. This paper discusses important metallization process trends with focus on the impact to the final device. The SEMulator3D platform offers a virtual fabrication tool with automation and metrology capability to quickly and thoroughly map a complete process space. Happy read!!

September 29, 2013June 14, 2019

Another Negative Year for Semiconductor CapEx

Another Negative Year for Semiconductor CapEx
by Bill Jewell on 09-29-2013 at 11:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

Global semiconductor capital spending is headed for another decline in 2013, following a 12% decline in 2012. Gartner’s September forecast called for a 7% decline in 2013. Most of the major spenders expect flat to declining expenditures in 2013. Intel in July estimated 2013 spending of $11 billion, flat with 2012 and down from its April forecast of $12 billion. Samsung expects a 4% decline in 2013 spending compared to its April estimate of flat. The two largest foundry companies expect strong growth in 2013 capital spending. TSMC stated in January it planned 2013 spending of $9.5 billion to $10.0 billion, up 14% to 20% from a year ago. GlobalFoundries estimated an 18% increase in spending.

The total 2013 capital spending of the six companies listed is $41.3 billion, up 2% from $40.5 billion in 2012. This represents 78% of Gartner’s forecast of $54.8 billion in total semiconductor industry capital spending in 2013, compared to 69% in 2012. The numbers imply a drop of 26% in 2013 spending by the rest of the industry outside of the six companies listed. However it is likely several of the six companies will announce lower 2013 spending plans when they release their third quarter results in October.

The expected decline in 2013 semiconductor capital spending is confirmed by the trend in semiconductor manufacturing equipment. SEMI (Semiconductor Equipment and Materials International) and SEAJ (Semiconductor Equipment Association of Japan) each release monthly bookings and billings data based on inputs from their member companies. Combining the SEMI and SEAJ data shows a downward trend in bookings and billings beginning in June 2013. Billings for the year 2013 should be down about 8% to 12% from 2012.

SEMI and SEAJ cooperate on quarterly estimates of global semiconductor manufacturing equipment shipments by region. The chart below shows data from 2007 and 2011. In 2007, the peak year prior to the great recession, shipments reached $42.8 billion. After steep declines in 2008 and 2009, shipments recovered to exceed the 2007 peak, reaching $45.3 billion in 2011. Shipments declined 15% in 2012 to $36.9 billion.

Although total semiconductor manufacturing shipments in 2011 were roughly equal to 2007, the trends by region differed significantly. The two largest markets in 2007 saw significant declines by 2011. Japan dropped $3.5 billion and Taiwan dropped $2.1 billion. North America became the largest market in 2011 with an increase of $1.7 billion from 2007. All other regions showed growth. Interestingly Europe showed more gain in shipments from 2007 to 2011 (up $1.3 billion) than China (up $0.7 billion). Assuming the U.S. accounts for the vast majority of North America shipments, the U.S., Taiwan, South Korea and Japan accounted for 74% of shipments in 2011 versus 79% in 2007. Although the overall semiconductor industry has become globalized, semiconductor manufacturing remains heavily concentrated in just four countries.

lang: en_US

September 28, 2013June 14, 2019

With SCE-MI, timing really is everything

With SCE-MI, timing really is everything
by Don Dingee on 09-28-2013 at 11:00 pm
Categories: Aldec, EDA

In one of my favorite movies, Brad Pitt utters the only question that matters in baseball or technology management in the face of uncertainty: “Okay, good. What’s the problem?” Not surprisingly in that scene, as the question circles the table of experts used to doing things the old way, not a single one can answer it correctly in the new context.

For all the talk about massive SoC designs and teams being eaten alive by verification taking 50% to 70% of the design cycle time, there is a lot of industry disagreement on what exactly is the problem. There is no shortage of solutions, but most focus on trying to run stuff faster. The thing about faster is, it can be really expensive, and one piece running faster by itself often doesn’t solve the problem.

With that in mind, we bring in a new white paper from Bill Jason Tomas at Aldec. He starts at the same place a lot of others do: hardware-assisted verification, where FPGA prototypes are used in co-emulation to speed up critical pieces of the effort. This works very well at reasonable scale, but all too often at the massive scale of today’s SoC, something else happens: the testbench itself takes up more and more of the emulation time.

Why? Most test generators are written in some high-level representation, and are event-driven as opposed to timing-driven. At some point where the ball meets the bat, timing really is everything when cycle-exact RTL comes up, and a bottleneck forms when the hardware-assisted emulator has to field all those mismatched and unformatted events.

The game-changing solution is a set of transactors to connect the untimed testbench to the timed modules living on the emulator. Moving from events to transactions, each with proper timing and structure, allows the emulator to run with its fast timing intact.

But if everyone goes off and writes their own transactors designed for their testbench and emulation system, we are back at the start – still waiting for our design to verify, because different transactors don’t work together. Enter the Standard Co-Emulation Modeling Interface (SCE-MI). When Accellera set out to establish the SCE-MI standard, portability of transactor models was a key consideration.

SCE-MI sets up message channels, analogous to sockets in network programming models, which abstract the interface. As Bill points out, a single event in the testbench can trigger hundreds of clock cycles in the emulator. Transactors convert the message to a sequence of clocked bit-level data forming the timing-accurate inputs to the DUT, and similarly process output patterns back into event formats the testbench expects.

The HES-DVM environment provides the SCE-MI infrastructure for users to connect a SystemC testbench to an Aldec HES-7 FPGA-based prototyping system. The Aldec implementation of SCE-MI uses TCP/IP to provide reliable message delivery between the sides. This increases the portability of the Aldec SMS library, so it may be used with Aldec and 3[SUP]rd[/SUP] party simulators.

For more on SCE-MI and the thinking behind transactions, here’s the full white paper:

SCE-MI Macro-Based Interface for System-on-Chip Verification

When people ask me what the problem in technology today is, whether the context is SoC design, software development, or the Internet of Things, I’m giving one answer lately: creative inclusion, bringing disparate IP together in some kind of framework. You can’t win if you don’t get on base, no matter how good your individual tools are. SCE-MI is a good example of innovation, allowing great tools to integrate more smoothly.

lang: en_US

September 28, 2013June 14, 2019

TSMC Open Innovation Platform Forum, October 1st

TSMC Open Innovation Platform Forum, October 1st
by Paul McLellan on 09-28-2013 at 5:00 am
Categories: EDA, Foundries, IP, TSMC

One of TSMC’s two big Silicon Valley events each year is the Open Innovation Platform (OIP) Forum. This year it is on Tuesday October 1st. It is in the San Jose Convention Center and starts at 9am (registration opens at 8am). Pre-registration to attend is now open here or click on the image to the right.

From 9.10 to 9.40 is the TSMC keynote and then from 9.40 to 10.10 is a presentation on TSMC and its Ecosystem for Innovation.

After a coffee break, the rest of the day is in three parallel tracks: EDA, IP and a services track that also contains little leavening of EDA and IP too. The big guns are all there: Cadence, Synopsys, Mentor and ARM are all presenting. Smaller companies such as iRocTech and Sidense are also there. The complete program is below.

[TABLE] cellpadding=”4″ style=”width: 97%”
|-
| align=”center” style=”width: 15%” | [TABLE] cellpadding=”10″ style=”width: 100%”
|-
| align=”center” |
|-

|-
| 11:00 – 11:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | Design Reliability with Calibre Smart-Fill and PERC
|-
| valign=”top” align=”center” | Broadcom & Mentor Graphics
|-

|-
| 11:30 – 12:00
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | TSMC 16nm FinFET SRAM Design Verification
|-
| valign=”top” align=”center” | Synopsys
|-

| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | Soft-Error Testing at Advanced Technology Nodes
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| valign=”top” align=”center” | GUC
|-

|-
| 12:00 – 13:00
| colspan=”3″ valign=”top” align=”center” | Lunch
|-
| 13:00 – 13:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | Addressing Custom Design Challenges for IP Design at 16nm FinFET technology
|-
| valign=”top” align=”center” | Cadence
|-

| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | Optimizing Cortex-A57 for TSMC 16nm FinFET
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| valign=”top” align=”center” | ARM
|-

|-
| 13:30 – 14:00
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | A Synergetic, Multi-Partner, Soft Error Rate Analysis Framework For Latest Process Nodes
|-
| valign=”top” align=”center” | iROC
|-

|-
| 14:00 – 14:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | EDA-Based DFT for 3D-IC Applications
|-
| valign=”top” align=”center” | Mentor Graphics
|-

|-
| 14:30 – 15:00
| colspan=”3″ align=”center” | Coffee Break
|-
| 15:00 – 15:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | Advanced Power, Signal and Reliability Verification for 20nm, 16nm FinFET, and 3D-IC Designs
|-
| valign=”top” align=”center” | ANSYS Apache
|-

| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | ARM POP IP Accelerating Time-to-PPA in Mainstream Mobile
|-
| valign=”top” align=”center” | ARM
|-

|-
| 15:30 – 16:00
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | Low Power and Faster Timing ECO for sub-20nm Designs
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| valign=”top” align=”center” | Dorado Design Automation
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|-
| 16:00 – 16:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | FinFET modeling and extraction solution for TSMC’s advanced 16-nm process
|-
| valign=”top” align=”center” | Synopsys
|-

|-
| 16:30 – 17:00
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC
|-
| valign=”top” align=”center” | Mentor Graphics & nVIDIA
|-

|-
| 17:00 – 18:00
| colspan=”3″ align=”center” | Networking and Social Hour
|-

TSMC created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served more than 600 customers, manufacturing more than 11,000 products for various applications covering a variety of computer, communications and consumer electronics market segments. Total capacity of the manufacturing facilities managed by TSMC, including subsidiaries and joint ventures, reached 15.1 million eight-inch equivalent wafers in 2012. TSMC operates three advanced 12-inch wafer GIGAFAB™ facilities (fab 12, 14 and 15), four eight-inch wafer fabs (fab 3, 5, 6, and 8), and one six-inch wafer fab (fab 2). TSMC also manages two eight-inch fabs at wholly owned subsidiaries: WaferTech in the United States and TSMC China Company Limited, In addition, TSMC obtains 8-inch wafer capacity from other companies in which the Company has an equity interest.

TSMC’s 2012 total sales revenue reached a new high at US$17.1 billion. TSMC is headquartered in the Hsinchu Science Park, Taiwan, and has account management and engineering service offices in China, Europe, India, Japan, North America, and, South Korea.

September 26, 2013June 14, 2019

What Mentor Said at ITC

What Mentor Said at ITC
by Beth Martin on 09-26-2013 at 4:47 pm
Categories: EDA

At the ITC test conference in early September, Mentor made three announcements. ITC is a big event for Mentor’s test group, and where they usually roll out their new tools and capabilities. The indefatigable Steve Pateras was captured on film describing them.

I’ve summarize Mentor’s three announcements and added links to resources.

Hybrid compression ATPG/LBIST, which is useful for testing high-reliability and safety-critical ICs, for instance in automotive and medical areas. This is a newer technology that re-uses the same scan, clocking, and other test logic to apply both deterministic and random test patterns. See the new whitepaper“Improve Logic Test with a Hybrid ATPG/BIST Solution” (requires registration). They announcedthat Renesas adopted Mentor’s hybrid TK/LBIST solution to satisfy the in-system test requirements mandated by the ISO 26262 automotive quality standard.

An IJTAG (P1687) ecosystem. IJTAG is the spiffy new standard for control and test of IP, which is billed as a real plug-n-play IP integration standard. Last year, Mentor announced their Tessent IJTAG tool that automates the support of the standard. See the Tessent IJTAG datasheetand a whitepaper, “Automated Test Creation for Mixed Signal IP using IJTAG.” The announcementwas that that they worked with Asset Intertech to ensure interoperability between Tessent IJTAG and Asset’s ScanWorks IJTAG solution, allowing engineers to access the operational and diagnostic features of all IP blocks in the design from a top-level interface. This greatly simplifies the job of integrating the hundreds of IP blocks in a typical system, and represents a large step towards creating an IJTAG ecosystem between EDA, IP providers and hardward/software debug tools.

The transistor-level ATPG that they call Cell-Aware test has lots of published industry data showing improved test quality for very-low DPM applications, including automotive, medical, aerospace…really anyone who wants fewer failing devices making it to the field. They have a great web seminar on Cell-Aware test (registration required), and a Cell-Aware Test datasheet. Their announcement is that Open-Silicon is using Cell-Aware test meet demand for very low DPM by detecting defects within cells.

More articles by Beth Martin…

September 26, 2013June 14, 2019

The US Executive Forum 2013

The US Executive Forum 2013
by Daniel Nenni on 09-26-2013 at 10:00 am
Categories: Global Semiconductor Alliance, Semiconductor Services

The US Executive Forum hosted by the Global Semiconductor Alliance was held last night at the beautiful Rosewood Sand Hill Hotel in Menlo Park. We all have memorable events in our professional lives and this is one of mine, absolutely. The audience was filled with semiconductor executives from around the world who chatted freely at lunch and during the breaks. At the end of the night my pocket was filled with business cards and my mind was filled with friendly faces to remember. I may forget names but never a face.

When I first started writing I jokingly said I blogged for food. After that the lunch offers and forum invitations poured in. At last count I have attended 23 events this year and I still have many more on my calendar. Engaging with the fabless semiconductor ecosystem face to face is everything. It’s what you know AND who you know, absolutely. My business model is different on this event however. If you want to know the details you have to buy me lunch.

Dr. Rice shared her views on technology, the global economy, and conflicts around the world. Dr. Rice also reminded us of something that we should never forget: America is the only country that you can immigrate to and become an American. You can’t immigrate to Japan and become Japanese or Germany and become German, right? This is definitely something to be proud of and something to protect.

The most memorable session was the panel moderated by Aart de Geus with the CEO’s of Altera, Micron, and Marvell plus the President and CSO of Samsung.

This Panel Discussion will spotlight CEOs from leading semiconductor companies as they discuss amongst other things, the toughest challenges facing our industry today and what reforms can be made to address those challenges.

And indeed it did. I wrote a blog a while back suggesting that Aart run for Governor and I stand by that. This panel was one of the best I have seen. Again, buy me lunch and I will discuss it in detail but let me just say this…. WOW! Aart asked some very compelling questions and did not accept non-answers. I was front row center and the audience Q&A was also a WOW!

To give credit where credit is due, the GSA really hit this one out of the park. If you are not already engaged with the GSA here is how you can get started. In addition to the corporate website, you can follow the GSA on LinkedInHERE. Better yet, you can join one of the LinkedIn groups and engage GSA members directly:

These groups are moderated and populated by industry professionals. Ask questions and you will get answers. Also check their calendar of events HERE, a YouTube channel with clips from past events HERE, and the GSA landing page on SemiWiki HERE with expert coverage by Dr. Paul McLellan and myself.

The Global Semiconductor Alliance (GSA) mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe. www.gsaglobal.org

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