SemiWiki – Page 80 – The Open Forum for Semiconductor Professionals

March 4, 2024October 15, 2024

A Game-Changer for IP Designers: Design Stage Verification

A Game-Changer for IP Designers: Design Stage Verification
by Kalar Rajendiran on 03-04-2024 at 10:00 am
Categories: EDA, IP, Siemens EDA

Calibre Shift Left Solutions Enable Reducing TTM

In today’s rapidly evolving semiconductor industry, the design and integration of intellectual property (IP) play a pivotal role in achieving competitive advantage and market success. Whether sourced from commercial IP providers or developed in-house, ensuring that IP designs are compliant with signoff requirements and seamlessly integrable into larger designs is paramount. From managing design complexity to ensuring power efficiency and security, IP designers must navigate a multitude of factors while striving to meet tight deadlines and maintain quality standards. Additionally, the rise of third-party IP usage and design reuse further complicates the landscape, necessitating interoperability and compatibility across different IP blocks and design modules. The complexity and competitiveness of the IP design landscape necessitate efficient verification processes that minimize time-to-market and resource requirements. Siemens EDA addresses this topic in-depth in a recently published technical whitepaper.

The Importance of Early Verification

Commercial IP design is a fiercely competitive arena, while in-house IP development offers the opportunity for design companies to differentiate themselves by incorporating innovative functionality into their integrated circuit (IC) designs. Regardless of the source, ensuring that IP designs are signoff-compliant and ready for integration into larger designs is essential for maintaining a competitive edge. In addition, Block/chip designers and designers working on three-dimensional integrated circuits (3DICs) also encounter unique verification challenges that require specialized solutions. Reducing the time and resources required for design, implementation, and verification directly impacts marketability and profitability.

One of the key strategies for streamlining the IP design process is the early detection and correction of physical verification issues. By identifying and addressing these issues in the initial stages of the design process, designers can minimize the risk of costly errors and delays during later stages.

Siemens EDA’s Calibre Shift Left Solutions

Calibre Shift Left solutions provide a comprehensive approach to streamlining the IP design process. These solutions combine proven Calibre technology with innovative strategies to support consistent and thorough verification of IP designs while maximizing productivity and efficiency. By shifting select physical verification and design optimization tasks earlier in the design and implementation workflows, Calibre Shift Left solutions empower design teams to accelerate time-to-market and achieve volume production faster.

Calibre Shift Left Solutions Enable Enhanced Productivity and Reduced Time to Market

From early detection of design issues to comprehensive verification of IP designs, Calibre Shift Left solutions provide the flexibility and scalability needed to meet the diverse needs of semiconductor design teams. Calibre Shift Left solutions offer advanced tools and methodologies to facilitate early detection of physical verification issues, enabling designers to proactively address these challenges and ensure compliance with signoff requirements.

Shift Left Physical Verification in IP Design Flows

Prioritizing and Categorizing Design Issues

Efficient resolution of design issues is essential for maintaining productivity and meeting project deadlines. Prioritizing and categorizing design issues allows designers to focus their efforts on resolving critical issues first, minimizing time and resource wastage. Calibre Shift Left solutions provide functionalities to prioritize and categorize design issues, enabling designers to allocate resources effectively and accelerate the resolution process.

Tailored Benefits for Different IP Design Types

Calibre Shift Left solutions offer specific advantages tailored to different IP design types. For hard IP designers, early verification enables rapid identification and resolution of modified IP components, minimizing retesting requirements and ensuring smooth integration into larger designs. Soft IP designers benefit from early SRAM IP integrity validation, mitigating compilation issues before finalizing the design. Custom IP designers can leverage tools like Calibre RealTime Custom and Calibre Pattern Matching to streamline verification processes and reduce runtime and debug cycles.

Aligning IP Cell Verification with Larger Chip Designs

Ensuring consistency and alignment between IP cell verification and larger chip designs is crucial for seamless integration and optimal performance. Calibre Shift Left solutions enable designers to align IP cell verification with the same intent as larger chip designs, ensuring compatibility and interoperability across different design components. By leveraging Calibre’s proven technology, designers can streamline the verification process and minimize discrepancies between IP cells and larger chip designs.

Extending Beyond IP Design

Beyond IP design, block/chip designers and 3DIC designers can also benefit from Calibre Shift Left solutions to address their unique verification challenges. These solutions enable designers to apply early verification stages efficiently within familiar environments, ensuring high-quality results while accelerating the design process. Calibre Shift Left solutions not only optimize resource utilization but also enhance design agility and competitiveness in today’s dynamic semiconductor landscape.

Optimizing Performance and Automation

Performance optimization and automation play a crucial role in enhancing the efficiency of early design-stage verification. Calibre Shift Left solutions offer advanced optimization techniques and automation capabilities to minimize runtimes and maximize resource efficiency. By integrating Calibre tools into design and implementation environments, designers can streamline verification processes and accelerate design closure while ensuring signoff-quality results.

Summary

In a competitive semiconductor landscape, the Calibre Shift Left solution emerges as a game changer for streamlining the IP design process and enhancing overall efficiency. By addressing key challenges such as early detection of physical verification issues, efficient resolution of design issues, and alignment of IP cell verification with larger chip designs, Calibre Shift Left solutions empower designers to deliver high-quality IP designs in a timely manner. By streamlining verification processes, minimizing time-to-market, and optimizing resource utilization, Calibre Shift Left solutions allow companies to stay ahead of the curve.

Siemens EDA’s whitepaper titled “A game-changer for IP designers: design-stage verification” is essential reading for designers, engineers, and engineering managers aiming to streamline and enhance the efficiency and accuracy of their design processes.

Also Read:

AI and SPICE Circuit Simulation Applications

Mastering Mixed-Signal Verification with Siemens Symphony Platform

Cryogenic Semiconductor Designs for Quantum Computing

March 4, 2024March 4, 2024

How MZ Technologies is Making Multi-Die Design a Reality

How MZ Technologies is Making Multi-Die Design a Reality
by Mike Gianfagna on 03-04-2024 at 6:00 am
Categories: EDA, MZ Technologies
2 Comments

The next design revolution is clearly upon us. Traditional Moore’s Law is slowing, but the exponential demand for innovation and form factor density is not. When you can no longer get it done with a single monolithic chip, moving to a multi-die approach is the answer. This emerging design methodology has many challenges – supply chain-oriented, materials-oriented, and standards-oriented to name a few. There is promising innovation from EDA, IP and standards organizations. Sitting above all this work is a substantial challenge. With so many options to implement new system-level silicon, which set of options are best? 2.5D, 3D, technology choices, IP/chiplet choices and so on. It’s a vexing problem since starting with the wrong options can lead to huge cost and schedule impact. The problem has been referred to as pathfinding, and that is the topic of this post. Read on to see how MZ Technologies is making multi-die design a reality.

About MZ Technologies

I mentioned pathfinding. In the context here, the term refers to identifying the optimal technology choices to implement a 2.5D or 3D multi-die design. The problem has been around for quite a while. Here is a discussion of it from the 2009 IEEE International Symposium on System-on-Chip. I have some experience with these problems as well. Around this same time frame while I was at Atrenta, we developed an early tool to address the pathfinding problem. And later, while at eSilicon, I got an up-close look at how challenging 2.5D design can be.

MZ Technologies was founded in 2014 by a team of leading EDA, IC, and package co-design experts. The goal was to build new technology from scratch to deal with the I/O planning and optimization phase of the physical implementation of complex 2.5D and 3D integrated circuits. That is, solve the pathfinding problem. A bit about the name of the company, which is shorthand for monozukuri. In Japanese, “monozukuri” is a compound word comprising “mono”, which literally means “things” (“products”), and “zukuri”, which means “process of making” or “creation”.

The company is a European EDA provider delivering GENIO™ a unified cockpit for 2.5D & 3D chiplet-based system design. GENIO is a tool that fills the pathfinding gap for multi-die design. It doesn’t compete with existing technologies, but rather interfaces with them to create a broader, more holistic capability. The tool has been around through several releases and has seen application across a wide range of multi-die designs. More on that in a bit.

What MZ Technologies Does

GENIO addresses the system architecture and IC/package co-development flow. This is the part of the design process that typically sits above existing tools and IP. It answers critical questions about the best implementation approach from a form factor, energy, performance, and cost point of view. Getting these things right early in the process can be the margin of victory for a complex design. Starting with a sub-optimal approach will create re-work, overruns, and a good chance the project will fail.

The figure below shows how GENIO fits into the overall design flow with existing tools.

GENIO Design Flow

The tool fits in the flow from concept to design to deliver a first time right optimal result. The goal is to create better manufacturability with optimal resources usage and better yield. GENIO works across the complete design ecosystem from silicon to package to PCB, with integrated design flows.

Digging a bit deeper, system architecture exploration is supported for planning, implementation, and analysis across different engineering domains. What-if analysis is provided for 2D, 2.5D and 3D interconnect management, I/O planning, and optimization. For example, planar vs. SI-based vs. 3D-stack. The optimization algorithms tame multi-die design computational complexity. Early estimations of electrical, mechanical, and thermal behavior are also provided.

With GENIO, it is possible to optimize in one shot through the full system hierarchy, from the top level to subsystems and components. A sophisticated GUI allows cross-highlight and scripting, among other functions, with the ability to go back in the design history to tag the most promising configurations. The figure below shows an example of the GUI.

GENIO GUI

GENIO has delivered a remarkable 60x reduction of architectural design time. The table below illustrates the types of designs GENIO has been applied to.

GENIO Applications

Here is a summary of the current version and next generation of the tool:

GENIO V1.x (commercially available today with a back-end orientation)

Comprehensive system view spans the entire design ecosystem
- Cross-fabric platform, integrated with traditional IC, package & PCB design tools
System-level architecture exploration
- Identifies the more efficient and cost-effective option into 3D system offering
Single, consistent Interconnect Manager
- Represent and maintain the 3D model of the entire system
Cross-hierarchical 3D-aware pathfinding
- Constraint-driven, proprietary optimization algorithms
3D chiplet-based design flow with multiple IP libraries
- Die stacking and silicon-to-silicon vertical communications – mix-and-match “LEGO-like” assembly

GENIO EVO (Next Evolution release; introduces simulation-aware optimization)

Complete 3D system view across physical implementation and analysis
Super-fast parasitic estimation for early analysis
- What-if analysis before physical implementation starts
State-of-the-art TSV modeling
- Including electrical performance (R/C) and mechanical/thermal behavior
Thermal modeling
- Based on power dissipation map and TSVs contribution
Mechanical stress
Voltage and temperature monitor placement according to identified thermal hotspots
- Critical net group spotting and prioritization

3DBlox language support
3D-system partitioning flow
- Support to system partitioning in the early stages of RTL & synthesis
3D-stack floor planning
- Best positioning of system components/chiplets across the stack planes

To Learn More

MZ Technologies licenses its software with a time-based model. Additional services for custom integration, custom module development, and customer training are also available. If you are planning to tackle a multi-die design, you should contact them. I can tell you from first-hand experience the problem MZ solves is very real and can become a fatal flaw if not addressed early. You can reach out at info@monozukuri.eu. And that’s how MZ Technologies is making multi-die design a reality.

Also Read:

Outlook 2024 with Anna Fontanelli Founder & CEO MZ Technologies

CEO Interview: Anna Fontanelli of MZ Technologies

March 3, 2024March 3, 2024

SPIE Let there be Light! High NA Kickoff! Samsung Slows? “Rapid” Decline?

SPIE Let there be Light! High NA Kickoff! Samsung Slows? “Rapid” Decline?
by Robert Maire on 03-03-2024 at 6:00 am
Categories: Events, Semiconductor Advisors, Semiconductor Services
3 Comments

– High NA EUV’s coming out party – “Dawn” of the Angstrom Era
– Well attended, positive vibes, not much new but good progress
– Concerns about Samsung slowing spend while Intel accelerates
– KLA reticle inspection quandary – Risky business in China

SPIE was a High-NA “coming out” party

We would view this years SPIE 2024 conference as the official launch of High-NA EUV technology, both figuratively as well as in reality.

It was announced by Ann Kelleher of Intel that “first light” was achieved by an ASML High-NA tool in Veldhoven (soon to be followed by Intel’s first High-NA tool).

In her presentation we attended we saw a strange set of banana shaped light images on a wafer that were evidence of the first EUV light through a recently assembled tool.

Although its sounds simple, its a big step on the way

Ann also gave a great overview of where the industry and specifically Intel was at and reiterated the five nodes in four years mantra which seems to be underscored by solid progress. It was one of the better overviews talks we have seen.

Tribute to Gordon Moore

There was also an “all star” cast of industry titans who gave a very heartfelt tribute to the late Gordon Moore, father of the semiconductor industry’s heartbeat of “Moore’s Law”. Perhaps the most touching was from Craig Barrett, former CEO of Intel.

It was very appropriate timing as High-NA represents the gateway to the Angstrom era which is proof positive of the continued life and legacy of Moore’s Law and its continued progress

No “New” news

The conference was very well attended and bounced back even more than its pre covid highs. The number of “poster” presentations appeared to more than double. However, there were no major announcements that moved the industry as in some past SPIE conferences.

Many of the presentations were on one aspect of EUV or High-NA or another. DUV was left in the dust along with “I-Line” lithography and other ancient technologies. Photoresist, reticles, metrology and other accoutrements to EUV were the majority of the topics of presentations.

A tale of “two semis”

We heard from a number of people in the equipment industry and supply chain that Samsung has slowed, canceled or delayed many orders. It also seems to be not just the memory side of Samsung that is slowing but the logic/foundry side as well.

It seems fairly clear to us that memory still has a lot of excess fab capacity and that situation has not gotten much better or at least better enough to start capacity purchases.

What is more interesting is that the foundry/logic side is also weak. We could speculate about the continued foundry weakness and would bet that TSMC is likely taking share from Samsung during this weaker period.

We have mentioned this before as second tier foundries get overflow business when things are hot and TSMC can’t service everyone. But when things slow, customers come back to TSMC. We saw other evidence of this with GlobalFoundries projected decline which could be a foreshadowing of Samsung foundry weakness.

On the other side of the coin, Intel seems to be cranking on all cylinders, and going in the opposite direction from Samsung’s slowing spend.

Perhaps Intel being more positive while Samsung cools nets out to the flattish projections we heard from semiconductor equipment makers reporting their December quarter

Applied continues to call SCULPTA etch tool a patterning tool -NOT-

Applied had a repeat performance of its etch tool called SCULPTA which it continues to palm off as a patterning tool by talking about it at SPIE.

Last year, dumb analysts, trashed ASML’s stock by predicting the end of double patterning and the reduction of ASML sales due to SCULPTA which obviously didn’t happen so there was no stupid knee jerk reaction this year….just a ho hum.

A “RAPID” decline? Photons are better than electrons

We continue to express concern and warn about the long term direction of the “RAPID” division of KLA (reticle inspection) which was one of the two founding pillars of the company.

It sounds like the 8xx, E beam reticle inspection tool, which was most likely to be an interim placeholder while waiting for the delayed Actinic inspection 7xx is now dead at two key customers.

It also sounds like the optical market that the 6xx plays in has become more of a commodity horse race which has negatively impacted pricing.

On the bright side it sounds like the long anticipated 7xx Actinic tool may be close to experiencing its version of EUV “first light”….light at the end of a very long tunnel.

Also on the bright side for KLA, the rumored Zeiss Actinic inspection tool that we first reported on sounds like it could be a bit over hyped with too high expectations and may struggle much as their first “AIMS” review tool.

It may still be a race to see who gets the second Actinic tool on the market, KLAC or Zeiss, years after the Lasertec tool. Stay tuned.

Risky business in China

We have long warned about the risk and exposure of 45% of the industry’s semiconductor equipment business being in China. The risk is compounded by potential for prohibited behavior consequences.

Back in the fall it was reported that AMAT was under investigation for violating export regulations on China by cross shipping to China through Korea. We had noted at the time, and no one else seemed to pick up on, the additional risk to CHIPS act awards due to potentially prohibited behavior.

Yesterday, it was widely reported in the news that not only has Applied received more subpoenas regarding the original concerns but the investigation has broadened to now include the SEC.

As we had predicted, the company also just reported that it also received subpoenas related to “certain federal award applications”, which sounds like the feds may be wondering about Applied getting CHIPS act money if they are violating China restrictions ….this could be a “triple play”…..

Link to Reuters article on AMAT subpoenas

The Stocks

There was not a whole lot of impactful news at SPIE this week but the other China news clearly underscores the continued risks.

We also remain concerned that weakness from Samsung may slow any recovery which is hoped for in the second half of the year.

The stocks in general remain fully to well over valued in our view and continue to be swept up in the Nvidia/AI tsunami

We wonder if or when investors will start to separate out those stocks with more or less exposure especially if the recovery takes longer than the expected end of year timeframe.

The China risk continues as a cloud over the industry as evidenced by Applied.

While we still adore Nvidia, and personally own it, other semiconductor stocks may not deserve the same adoration simply through association of being in the same semiconductor industry.

We do still like both ASML, now the biggest equipment maker, and TSMC, by far the biggest and best foundry….but we get a bit more picky as we go down the list especially at nose bleed valuations

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

AMAT – Flattish QTR Flattish Guide – Improving 2024 – Memory and Logic up, ICAPs Down

KLAC- OK Quarter & flat guide- Hopefully 2025 recovery- Big China % & Backlog

LRCX- In line Q4 & flat guide- No recovery yet- China still 40%- Lags Litho

ASML – Strong order start on long road to 2025 recovery – 24 flat vs 23 – EUV shines

Podcast EP210: How VSORA is Opening New Horizons for Generative AI and ADAS Applications

Podcast EP210: How VSORA is Opening New Horizons for Generative AI and ADAS Applications
by Daniel Nenni on 03-01-2024 at 10:00 am

Dan is joined by Jan Pantzar vice president of sales and marketing at VSORA, a provider of high-performance generative AI and ADAS chip solutions based in France. Mr. Pantzar gained extensive experience in the semiconductor, IP and software industries through building and managing organizations around the globe. Previous experience includes executive positions at Ericsson, Cypress and STMicroelectronics.

Jan provides details about the unique processor chips VSORA is developing. The primary markets for these devices is initially generative AI and automotive/autonomous driving, but VSORA technology can be applied in other areas as well. The focus is on very high performance and low power, opening the door to new levels of local processing capability.

Jan discusses the challenges faced today for generative AI and ADAS applications and explains how VSORA’s technology is removing processing and power barriers. He previews what the company will be delivering over the next year and where the impact will be.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

March 1, 2024February 26, 2024

CEO Interview: Larry Zu of Sarcina Technology

CEO Interview: Larry Zu of Sarcina Technology
by Daniel Nenni on 03-01-2024 at 6:00 am
Categories: CEO Interviews, Sarcina Technology, Semiconductor Services

Larry has grown Sarcina from designing semiconductor packages for a few small companies, to doing package designs for top semiconductor companies around the world. From 2014 to 2018, Larry led the expansion of Sarcina beyond package design into final test and wafer sort hardware and software development.

Larry is a semiconductor veteran who started his career at Bell Labs, before moving on to DEC, Intel, and TSMC. Along the way he developed a proven track record of delivering successful products including the Alpha, Itanium 2, Pentium 4, and XBOX 360 microprocessors. Over his career, he has tapped out nearly 1,000 packages with a greater than 99% first tape-out success rate.

Larry received his B.S. in Physics from Peking University and his Ph.D. in Electrical & Computer Engineering from Rutgers University. He has many refereed IEEE publications and holds multiple U.S. patents which have been used in leading US companies’ key products.

Tell us about your company?
Sarcina was founded in Palo Alto, CA in October of 2011. The name “Sarcina” refers to the backpack carried by Roman soldiers. Although it didn’t include their arms and armor, Sarcinas provided the essentials for daily living necessary to accomplish their military missions.

We are an Application Specific Advanced Package (ASAP) company that provides integrated WIPO (Wafer-In, Product-Out) services to customers around the globe. Our vision is to be the leading post-silicon service, setting standards for excellence by providing high-quality, dependable, creative, and assured package, test, and production services to our customers.

What problems are you solving?
As the complexity of designing an advanced semiconductor package becomes more challenging, and the cost of sustaining an internal packaging team for small to mid-sized chip companies and system companies becomes less economical, outsourcing chip packaging makes more sense for many ASIC and system companies. Companies often have to work with multiple independent vendors in Asia to accomplish most of their post-silicon tasks. So, outsourcing these tasks makes sense. That’s why we formed Sarcina: to meet these specific demands.

What application areas are your strongest?
We are the experts in high-power, high pin-count, and high data rate semiconductor packages for high-performance computing applications. Our 100% right-the-first-time success substantiates this claim.

What keeps your customers up at night?
Unresolved technical problems and missed deadlines.

We understand these two pain points. Either one causes companies to work double-shifts: one for their regular day job and the other at night to fix past mistakes. Sarcina’s job is to make sure that never happens and to make working with Sarcina a seamless, time-saving process.

What Does the Competitive Landscape Look Like, and How Do You Differentiate?
That’s an interesting question, and you may find the answer surprising. If you look at this from a service perspective, you’d think we have a large number of competitors across a broad swath of the semiconductor value chain: wafer foundries, ASIC companies, OSAT (Outsourced Semiconductor Assembly and Test) houses. However, if you view this from a business problem-solving perspective, the ASAP space is unique.

We solve both technical and business problems for small to mid-sized ASIC companies and system houses with understaffed post-silicon teams. Our value proposition is advanced packaging, test, assembly, and production at cost points lower than what can be achieved in-house. In the packaging area, our biggest competitors are the low-cost, low-tech, and mature technology entities.

Fortunately, with the boom of AI, mobile devices, autonomous driving, IoT, and the desire to win tomorrow’s tech wars, the market has expanded significantly. We believe the market is large enough to accommodate all of these players. Over time, the inefficient small players may drop out of the race.

Sarcina’s strength and fundamental differentiation is our ability to complete high-performance engineering projects. Over the past 12 years, Sarcina has taped out more than 100 packages, all first-time successes. We’ve never re-taped out a single package. At the same time, we’re able to complete advanced projects with a fraction of the headcount required by other companies. Our engineering efficiency is several times that of the industry norm.

In the networking business, there is a famous rule of thumb: if your product can offer a 10X performance increase … such as speed, efficiency, or capability …. but costs only 2X as much as the existing solution, your business will take off. In our business, we believe that if our engineering efficiency is several times that of our competitor, we’ll effectively compete, regardless of the size of the competitor.

What New Features/Technology Are You Working On?
Every four years, SerDes and PCIe data rates double, and DDR technology advances by a generation. Today, people are working on 112 Gb/s and 224 Gb/s PAM4 SerDes; 32 Gb/s NRZ PCIe-5 and 64 Gb/s PAM4 PCIe-6, as well as 6400 Mb/s to ~10 Gb/s LPDDR5/DDR5/GDDR6. Sarcina’s package design technology is ready for these high data rate chips in an HVM (High Volume Manufacture) environment. IP companies usually provide a live demo of their highest data rate IP with a few lanes of data communication. In a real chip, there will be many lanes with limited routing space. Our job is to provide the package design that meets our customers’ data rate requirements for their real chips. As of today, Sarcina has designed packages for 112 Gb/s SerDes, 64 Gb/s PCIe-6, and 6.4 Gb/s LPDDR5. Our next task is 224 Gb/s PAM4 SerDes with approximately 100 lanes of data communication inside a single package. We are also supporting these data rates on our final test loadboard loopback test.

How Do Customers Normally Engage With Your Company?
Surprisingly, word-of-mouth remains our most efficient way to land business. However, we are stepping up our overall industry presence and visibility as the demand for advanced technology packaging expands. We’re investing more in building collaborations with technology partners and implementing multiple one-on-one outreach channels. While businesses still value face-to-face meetings, we’ve significantly expanded our marketing campaign and assets. We’re appearing at more trade shows, ramping up our earned and paid media, and rebuilding our website, while refreshing our brand assets. All these efforts have dramatically increased our company’s visibility, opening doors to more advanced technology decision-makers.

Also Read:

CEO Interview: Vincent Bligny of Aniah

CEO Interview: Jay Dawani of Lemurian Labs

Luc Burgun: EDA CEO, Now French Startup Investor

February 29, 2024March 21, 2024

WEBINAR: Chipmakers can leverage generative AI to speed up RTL design and verification

WEBINAR: Chipmakers can leverage generative AI to speed up RTL design and verification
by Daniel Nenni on 02-29-2024 at 2:00 pm
Categories: AI, Events, Planorama Design, Semiconductor Services

The subjects of Generative AI and Large Language Models (LLMs) permeate businesses and the public conversation. It’s not without good reason! While this emergent field of AI develops, it is now seen at a minimum as a valuable assistant, or, often, a dramatic accelerant to productivity, even to technical workflows.

As we’re now seeing with AI-assisted coding in software development, generative AI will play a similar role in IC logic design and verification with the same dramatic effect. Increasing in criticality, centralized requirements will be the foundational source of truth for both human engineers and automated “AI assistants” responsible for writing RTL and verification requirements, executing tests, ultimately shrinking time to market.

WATCH THE REPLAY

AI-assisted Software Dev: Requirements to Code

Applications of generative AI are disrupting traditional tech-centric fields, like pure software application development where we see movement from all-human to AI-assisted coding. Tools like GitHub Copilot can act as your micro-level pair programmer. Even with minimal access to small portions of your codebase, it assists developers by proposing sections of code on demand. Copilot is limited, in part, by its inability to understand the high-level requirements that drive the code. AI needs the human-developer to interpret the human-readable requirements and thus, clocks out when the developer clocks out.

Software developers recognize this limitation and the community at large is working towards the audacious vision of full automation from centralized, human-readable requirements. As large-scale commercial LLMs advance, alongside the open and more specialized language models, the fruits of these efforts are becoming increasingly tangible. Nascent projects like GPT-Engineer, Aider, and GPT-Pilot are blazing the trail and moving us closer to this vision of automated 24×7 requirements to code software development.

AI-accelerated RTL Design and Verification

Clearly documented requirements as a single source of truth are key in automating development with generative AI. We see logic design and verification activities ideally suited to AI-accelerated development, unlike pure software development discussed prior. Pure software applications have human-centric GUI’s which AI has yet to automate. To compound, software often suffers from poorly documented requirements which lead to bugs.

By contrast, the logic designed into semiconductor chips originates from rigorous, well-documented specifications – ripe to be accurately interpreted through LLMs. The requirements (or specs) are the bedrock of the entire IC logic design and verification endeavor. Whether the work is carried out by skilled engineers or sophisticated AI assistants, these detailed specifications serve as the single source of truth upon which every aspect of the design is built.

To fully harness the potential of AI assistants, organizations will be tasked to build out AI systems that have access to a unified hub for all product documentation and specifications. This is key now in human-centric workflows but will become mission critical as design and verification is accelerated by AI assisted processes. It’s imperative that these AI systems have access to a unified hub for all product information to ensure that AI tools are aligned with the overarching requirements, operating within the same framework of understanding as their human engineering counterparts.

Meet Sinfonia in our upcoming webinar

Planorama Design is laser focused on the problems of traditional software and IC design and development. We strongly believe that solid, rigorously documented requirements and user experience design are the catalysts to accelerate software and software-hardware (IoT) systems time to market. To accelerate our internal processes and enhance our tools, Planorama Design built Sinfonia from the ground up with a focus on centralization of requirements.

On March 21, 2024 join us for our webinar, “From Specs to Verilog: AI-assisted logic design on a RISC-V implementation” where we will demonstrate Sinfonia. In this webinar, we will show how Sinfonia, with knowledge of RISC-V specification documents can support user-directed enhancements to an existing RISC-V implementation. This approach exemplifies the potential of AI to accelerate logic design and verification, offering a glimpse into future engineering capabilities available to semiconductor and hardware companies.

WATCH THE REPLAY

Learn more about Sinfonia

Connect with Matt Genovese of Planorama

Also Read:

A Bold View of Future Product Development with Matt Genovese

LIVE WEBINAR – The ROI of User Experience Design: Increase Sales and Minimize Costs

CEO Interview: Matt Genovese of Planorama Design

February 29, 2024November 29, 2024

2024 Outlook with Adam Olson of Perforce

2024 Outlook with Adam Olson of Perforce
by Daniel Nenni on 02-29-2024 at 10:00 am
Categories: EDA, Perforce

Perforce is a company that provides software solutions primarily focused on version control, especially for large-scale development projects. Version control systems manage changes to documents, computer programs, large web sites, or other collections of information. Perforce’s main product is Helix Core, formerly known as Perforce Helix, which is a version control system that helps software development teams manage and track changes to their source code, documents, and other digital assets. It is widely used in industries such as game development, automotive, aerospace, and finance where managing complex software projects with many contributors is essential.

Tell us a little bit about yourself and your company.
Adam Olson, Chief Revenue Officer and General Manager for the Digital Creation business unit at Perforce, which includes our integrated semiconductor solutions, Helix Core and Helix IPLM (formerly Methodics).

What was the most exciting high point of 2023 for your company?
We had several major account wins within our Digital Creation business unit and expanded our DevOps portfolio. Perforce also appointed a new CEO at the very end of 2023, which we’re very excited about. Technology veteran Jim Cassens brings to Perforce over 30 years of experience scaling software organizations with a customer-centric management approach. We’re thrilled to have him leading the organization.

What was the biggest challenge your company faced in 2023?
Some of our larger semiconductor customers were facing economic headwinds heading into 2023, which slowed their projects. While these headwinds eased up a bit by the end of the year, the challenges and complexities of the semiconductor industry remain. We find that what may have looked like a relatively mundane decision in the past is now met with larger committees and a need for strong defense of ROI models.

How is your company’s work addressing this biggest challenge?
Perforce is helping our semiconductor clients tame complexity and increase efficiencies across their design flow. We help them accomplish more with less and accelerate time to market, while keeping a lid on costs. Perforce Helix IPLM and Helix Core serve as a scalable, secure foundation for design data management. By tracking all IP and design data in Helix IPLM’s unified, hierarchical data model, our customers benefit from tighter coordination between cross-functional teams, end-to-end traceability, and more efficient requirements verification. And with Helix Core, they get robust, federated, multisite data management for enterprise scale, security, and performance.

What do you think the biggest growth area for 2024 will be, and why?
Semiconductor IP security will be a big factor in 2024 as global instability and political uncertainty rises and bad actors spend more time trying to compromise networks and other important infrastructure. Organizations – and global, multi-site teams in particular – will need to carefully track and secure design assets to avoid violating rapidly shifting technology restrictions and export control laws. Such violations, often caused by accidental IP leakage, can result in millions of dollars in fines and legal issues, on top of the lost revenue and market setbacks.

How is your company’s work addressing this growth?
Perforce is addressing this growing need for IP security through advanced new features like Geofencing as well as providing fine-grained security and enabling end-to-end traceability across the lifecycle. Helix IPLM’s Geofencing feature delivers dynamic security for global, multi-site teams by restricting IP availability in certain geos, regardless of user access permissions. These restrictions can be applied universally – regardless of the underlying data management systems (Perforce Helix Core, Git, DesignSync, etc). Within Helix Core, organizations can control access down to the file level and even qualify access by IP address.

What conferences did you attend in 2023 and how was the traffic?
Our Digital Creation team attended and exhibited at Embedded World and DAC. We had heavy traffic at our booth at both events – substantially more than the previous year, when conference attendance was still affected by the pandemic. We also attended the GSA Executive Forums in Europe and the US, along with Design & Reuse IP-SoC Silicon Valley.

Will you attend conferences in 2024? Same or more?
We’ll be attending the same conferences in 2024, along with a few others such as GOMACTech and DVCon.

Additional questions or final comments?
Perforce welcomes semiconductor leaders to join our Helix IPLM Monthly User Group (MUG) sessions. It’s a great opportunity to hear from product experts, industry peers, and Helix IPLM users about topics like IP governance, release automation, and IP security, along with best practices and the latest product features. To register, visit https://www.perforce.com/products/helix-iplm/user-group.

Also Read:

The Transformation Model for IP-Centric Design

Chiplets and IP and the Trust Problem

Insights into DevOps Trends in Hardware Design

February 29, 2024March 19, 2024

WEBINAR: Enabling Long Lasting Security for Semiconductors

WEBINAR: Enabling Long Lasting Security for Semiconductors
by Daniel Nenni on 02-29-2024 at 6:00 am
Categories: eFPGA, Events, Flex Logix

Today we live in a world where technology is a part of our everyday lives, not only our personal data, but all devices we rely on on a daily basis including our automobiles, cell phones, and home devices. Hackers have found creative and novel ways to corrupt these products, disable systems, steal secrets and threaten our identities. As we look forward to the future and as technology becomes more entrenched in our lives and impacts our security and safety, we need to move security solutions to the forefront.

WATCH REPLAY NOW

Security is a constantly evolving problem and requires an adaptable solution. In this session, we will address common security problems that we face in today’s challenging world and solutions that can mitigate these threats. Fixed solutions that are implemented today will inevitably be challenged in the future. Hackers today have more time, resources, training and motivation to disrupt technology. With technology increasing in every facet of our lives, defending against this presents a real challenge. We also have to consider upcoming threats, namely quantum computing. Many predict that quantum computing will be able to crack current cryptography solutions in the next few years!

Fortunately, semiconductor manufacturers have solutions that can enable cryptography agility, also known as Crypto Agility, which can dynamically adapt to evolving threats. This includes not only being able to update hardware accelerated cryptography algorithms, but also provide obfuscation to increase root of trust and protect valuable IP secrets in products. Advanced solutions like these also involve the ability for devices to randomly create their own encryption keys, making it harder for algorithms to crack encryption codes. This webinar will demonstrate a variety of solutions and reconfigurable IP from Flex Logix that can be implemented into any semiconductor device to thwart off all current threats as well as future threats. We will highlight solutions from partners who specialize in security and have ready-to-go IP that can be deployed on Flex Logix IP and add crypto agility to any semiconductor.

Watch this webinar now to learn more about enabling crypto agility in your semiconductor can provide long lasting security solutions.

Abstract:

Semiconductors are on the forefront of security to protect our identity, data and daily lives. And we live in a time where hackers have more time, resources, available training and motivation to disrupt our security than ever before. With quantum computing looming and threatening our current security implementations, it is more important than ever to start implementing crypto agile solutions that can adapt to evolving threats. And this needs occur at every level, including the transport, MAC and IP layers. Adding embedded programmable logic from Flex Logix combined with security IP solutions from Xiphera, a hybrid solution can provide long-lasting security for semiconductors.

Speaker Bios:

Jayson Bethurem is responsible for marketing and business development at Flex Logix. Jayson spent six years at Xilinx as Senior Product Line Manager responsible for about a third of revenues. Before that he spent eight years at Avnet as FAE showing customers how to use FPGAs to improve their products. Earlier, he worked at startups using FPGAs to design products.

Dr. Kimmo Järvinen is the co-founder and CTO of Xiphera. Kimmo has a 20-year long career in the academia where he has done cryptography related research in various European universities. Kimmo has a strong academic background in cryptography and cryptographic hardware engineering after having various post-doctoral, research fellow, and senior researcher positions in Aalto University (Espoo, Finland), KU Leuven (Leuven, Belgium), and University of Helsinki (Helsinki, Finland). Kimmo has published more than sixty scientific articles about cryptography and security engineering, and nearly half of them are somehow related to elliptic curve cryptography. Kimmo has substantial theoretical and practical experience in secure and efficient implementation of elliptic curve cryptosystems.

Join us in this webinar to learn more about enabling crypto agility in your semiconductor can provide long lasting security solutions.

Also Read:

Reconfigurable DSP and AI IP arrives in next-gen InferX

eFPGA goes back to basics for low-power programmable logic

eFPGAs handling crypto-agility for SoCs with PQC

February 28, 2024March 7, 2024

Soft checks are needed during Electrical Rule Checking of IC layouts

Soft checks are needed during Electrical Rule Checking of IC layouts
by Daniel Payne on 02-28-2024 at 10:00 am
Categories: EDA, Siemens EDA

IC designs have physical verification applications like Layout Versus Schematic (LVS) at the transistor-level to ensure that layout and schematics are equivalent, in addition there’s an Electrical Rules Check (ERC) for connections to well regions called a soft check. The connections to all the devices needs to have the most consistent voltage signals. Therefore, the path should be through the Metal layers to reduce resistance and factors like IR Drop. Detecting connections thought other materials–like Wells–in mandatory. Soft-Checks are the method most commonly employed to detect this situation. The Calibre product line from Siemens is the most popular tool for DRC and LVS checking, so I read a technical paper from Terry Meeks to learn more about soft checks.

Connecting two metal layers in an IC layout requires precise alignment of both metal layers and the via layer. Here’s a comparison using both a side view and top-down view where the first example is not connected, because Metal1 and Metal 2 are not overlapping, while the second example is connected properly.

Connecting two metal layers with a Via layer.

We want our ERC tool to identify well connectivity errors during soft checks, so that they can be fixed. The following IC layout has a well connectivity error and is shown from the side view, where the Metal1 signal texted as Gnd is connected a diffusion region called a tap diffusion. On the right-hand side is another Metal1 layer with a tap diffusion, but this connectivity creates a high-resistance path in the Rwell to Gnd, and is flagged as an error by the soft check.

Well connectivity error – side view

Another example of soft connectivity error happens in the IC layout below where we can apply only one name per polygon. The digital power net VDD cannot coexist with the analog power net AVDD, and we need to separate these into two shapes. Soft checks help to flag these issues.

AVDD net to VDD net soft check error

An IC layout with both digital and analog power supplies can become rather complex to layout properly, so it’s even more important to have soft checks.

Undetermined areas have question marks

Soft checks are included during your LVS runs, and with Calibre nmLVS there’s a report of soft check results, which can then be viewed using the Calibre RVE viewer.

Using Calibre RVE to review Soft Check errors

Clicking on RVE results tells you which cell has the soft check error, the net names, upper and lower names, and other properties. This info helps to pinpoint what to fix in the IC layout. Clicking on a lower layer like a PWell for a soft check error displays the geometry in yellow.

Soft check result, lower layer

For the same soft check error, clicking on the upper layer shows:

Soft check result, upper layer

During debug you can also show all the upper layer shapes, the green shapes are the selected net upper layer shapes, while yellow is the rejected net upper layer shape.

All upper layer shapes

Debugging soft check errors with RVE involves clicking on the connectivity of selected and rejected nets. A Net Info windows reveals details like which layers are involved, and if shapes are missing connectivity. Looking at which ports are connected to a net reveal if there’s missing VDD or GND errors. This example shows that net 18 is rejected, because it’s missing connectivity to Metal1.

Missing connectivity to Metal1

Summary

LVS checks are mandatory to ensure that an IC has an error-free layout, and soft checks are part of your LVS checks. There’s a proven debugging flow from Siemens in their Calibre nmLVS tool that uses RVE to help layout designers quickly identify soft check failures, so that designers can make fixes and re-verify until all checks are passing. Siemens has written a technical paper for reading online, Detecting and debugging soft check connectivity errors.

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February 28, 2024February 26, 2024

CEO Interview: Michael Sanie of Endura Technologies

CEO Interview: Michael Sanie of Endura Technologies
by Daniel Nenni on 02-28-2024 at 8:00 am
Categories: CEO Interviews

Michael Sanie

Michael Sanie is a veteran of the semiconductor and EDA industries. His career spans several executive roles in diverse businesses with multifunctional responsibilities. He is a passionate evangelist for disruptive technologies.

Most recently, he was the chief marketing executive and senior VP of Enterprise Marketing and Communications at Synopsys, where he also held leadership roles as VP of marketing and strategy for the Design Group and VP of product management for the Verification Group.

Michael previously held executive and senior marketing positions at Cadence, Calypto, Numerical, and Actel, as well as IC design and software engineering positions at VLSI Technology (now NXP Semiconductors).

He holds BSECE and MSEE degrees from Purdue University and an MBA from Santa Clara University.

Tell us about your company

Endura Technologies is developing an end-to-end SoC power delivery solution. In addition to our revolutionary, patented power delivery architecture, we have a diverse skillset to implement test silicon, design IP, design services, design passives (required inductors and capacitors as part of the power delivery solutions), partnerships, and silicon manufacturing relationships. This allows us to create end-to-end SoC power delivery solutions.

Our unique architecture, combined with our fully integrated approach to power delivery at the system level is changing the game for challenging applications such as data centers, automotive, and many others.

What problems are you solving?

Energy consumption for advanced products has become a major care-about across many markets and applications. Battery life and heat dissipation for aggressive form factors drive part of this. The substantial operating costs for massive compute infrastructure is another driver.

A bit more specifically, servers/AI chips are driving much higher compute demands, requiring more power to be delivered. At the same time, these chips are built on smaller nodes, which run on lower Vdd’s. The only way this equation can work is to provide much higher currents with several power rails, and increasingly this is only achievable by 2.5D or 3D IC integration These facts are fundamentally changing power delivery approaches.

On top of that, systems in automotive, audio, and switches typically rely on many sensory inputs ranging from MEMs devices to image sensors to radar. These devices require efficient power delivery across many load configurations and at increasing switching frequencies while maintaining ultra-low noise.

These fundamental disruptions are making people take power delivery a lot more seriously — in two ways: Power delivery is no longer an afterthought; it needs to be designed/architected at the same time as the SoC AND it needs a much more holistic approach. Off-the-shelf PMICs are quickly running out of steam in how they meet these complex requirements. To get the best power delivery each SoC needs its own ‘application-specific’ (or context-aware) power delivery solution.

Powering these systems at scale requires a new approach. One that takes a comprehensive view of power requirements for the chips and chiplets that implement the complete system. And one that optimizes performance, scalability, and efficiency over the broad spectrum of switching frequencies, current loads, voltage ranges, and silicon manufacturing processes.

This is the problem Endura is solving.

What application areas are your strongest?

Endura has applied its technology across a wide range of power-intensive or power-sensitive application areas – mostly data center and automotive. You can find more specific examples on our website that cover data centers, requirements for memories in data centers, a notebook design with a PCIe Gen5 solid state drive, optical modules and automotive.

What keeps your customers up at night?

Advanced system design presents a power delivery balancing act. The drivers for the requirement may differ, but all systems must operate efficiently with the lowest energy consumption possible.

These systems contain many parts, all operating at different frequencies, with varying power demands and obstacles. Solving the complete problem requires a holistic approach to power management and delivery.

But such an approach has been out of reach for most companies, requiring system designers to attempt integration of multiple tools and multiple sets of IP and software to solve the problem. This has been a very difficult problem to solve. Until now.

What does the competitive landscape look like and how do you differentiate?

The traditional approach to power delivery focuses on a component-level strategy. That is, acquire best-in-class power management solutions, typically from tier-1 suppliers and integrate these devices at the PCB level.

The substantial complexity and power demands of applications such as data centers require a new, fine-grained approach – one that integrates power delivery down to the chip level and one that co-optimizes the architecture for optimal system-level performance.

There are some design teams (typically in larger companies with a broad range of skills) that are making the investment to achieve these results across the supply chain. For everyone else, the complexity of integrating such approaches remains out of reach. Endura is democratizing this new, system-level approach to power delivery, so it is available to every system design team.

What new features/technology are you working on?

Power management approaches include the use of traditional, discrete devices (sVR) to embedded chiplets for 2.5/3D integration (eVR) down to on-chip, integrated blocks for optimum point-of-load energy delivery (iVR).

While sVR approaches are well-understood, deployment of fully integrated eVR and iVR strategies is extremely complex and challenging. Endura has the technology and know-how to solve these problems, and this is our development focus.

How do customers normally engage with your company?

Endura Technologies has development facilities in California and Dublin, Ireland. If you would like to explore how we can help you develop a forward-looking power strategy you can reach out at info@enduratechnologies.com.

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CEO Interview: Jay Dawani of Lemurian Labs

Luc Burgun: EDA CEO, Now French Startup Investor