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September 25, 2014

Atmel Expands Wireless Portfolio

Atmel Expands Wireless Portfolio
by Paul McLellan on 09-25-2014 at 7:00 am
Categories: Foundries

Recently someone described the Internet of Things (IoT) as being the semiconductor classification that we used to call ‘other’. It’s a nice line but actually I think IoT really is something different from what we were already doing before. Although it is a market that cuts across medical, automotive, home-electronics, wearables and more, there really is a lot of commonality, the biggest one being connectivity. It really isn’t IoT if it isn’t, directly or indirectly, connected to the internet.

One company that is well positioned to ride the IoT wave is Atmel. They have a very broad range of microcontrollers at different power/price/performance points along with a number of connectivity solutions. Earlier this week they announced a new set of Wi-Fi SoCs and modules as part of its SmartConnect wireless portfolio. There are two new turnkey SoCs (WILC1000 and WINC1500) and four new modules featuring the SoCs.

The WINC1000 is an IEEE 802.11b/g/n network controller. The WILC100 is an IEEE 802.11b/g/n IoT link controller. These SoCs came to Atmel in the acquisition in July of New Port Media (NMI) and they have been seamlessly integrated in just two months.

Expanding on Atmel’s Wi-Fi offering, the WILC1000 and WINC1500 are SoC solutions optimized for battery-powered IoT applications. These wireless SoCs feature fully integrated power amplifiers for the industry’s best communication range, without compromising cost or performance. Both the WILC1000 and WINC1500 are add-on solutions which can connect to any Atmel MCU or eMPU targeting a wide range of Internet of Things (IoT), consumer and industrial applications. Both products are available either as fully-certified modules ready for production to accelerate a designer’s time-to-market or as discrete SoCs for customers requiring the highest design flexibility.

The WILC1000 and WINC1500 provide multiple peripheral interfaces including UART, SPI, SDIO and I2C. The only external clock source needed is a high-speed crystal or oscillator with a wide variety of reference clock frequencies supported (between 12 – 50 MHz) and are IEEE 802.11 b/g/n, RF, baseband, MAC certified. The WILC1000 is available now as a chip and three different modules. The WINC1500 is available now as a chip and a module, with an evaluation kit, featuring Atmel’s SAMD21 MCU.

Strategic Materials Conference

Strategic Materials Conference
by Paul McLellan on 09-24-2014 at 8:00 pm
Categories: ESD Alliance, Semiconductor Services

SEMI’s Strategic Materials Conference is coming up fast, on September 30th and October 1st next week at the Biltmore in Santa Clara. This year’s theme, Materials Matter—Enabling the Future of IC Fabrication and Packaging, will take a broad look at what is driving the demand for new materials, and how material suppliers are being impacted by the value chain they serve.

The semiconductor industry has reached a major inflection point: no longer is device scaling and performance driven solely by reductions in feature size. Higher device performance using less power requires the incorporation of many new materials to maintain the industry’s cadence. These material needs to span across the spectrum from fabricating 3D transistor structures, to accelerating interconnect speeds, to packaging the devices in the appropriate form factors for use in phones, tablets and devices encompassing the internet of things. SMC will discuss market opportunities and examine how to win in this “Age of Materials”.

The two keynote speakers are from the biggest IDM and the biggest fabless semiconductor company: Intel and Qualcomm. Matt Nowak of Qualcomm gives the opening keynote on Materials Innovation for the Digital 6th Sense Era. On Wednesday morning, the keynote is delivered by Tim Hendry of Intel on Strategies and New Models for Creating an Affordable Material Supply Chain.

New this year are:

Device Makers Session: Materials Challenges for Emerging Technology and Devices
Market Trends Session: Economic/Material Trends/Emerging Technology Trends

There are also sessions (with multiple presentations) on Supply Change Challenges, Advanced Memories, Advanced Packaging/TSVs and “beyond 10nm”, the Material Manufacturers Perspective.

The complete agenda for the conference is here. The conference is almost sold out so online registration has been closed. Call Lin Tso at 408 943-7920 for availability if you want to go.

The Must Read FPGA Book – Secrets Inside

The Must Read FPGA Book – Secrets Inside
by Luke Miller on 09-24-2014 at 1:00 pm
Categories: FPGA, Xilinx

Crockett, Elliot, Enderwitz & Stewart is not a law firm, thank goodness… what you’ll find is that these folks are the authors of the world famous book entitled, now hold on here for a title, this is a creative one “The Zynq Book”, It is free, get your download here. Every designer should have this book no matter what FPGA parts they use. There is also a FREE companion “The Zynq Book Tutorials” when you get to the download page.

Zynq hands down is the most influential FPGA SoC of ALL time. The Zynq Book is already on Amazon’s Top 10 Best Seller list. That really is impressive. Why, because Xilinx SoC is for real and is opening new realms for FPGA design all over the world. A quick Chapter list is below:

CHAPTER 1 Introduction
CHAPTER 2 The Zynq Device (“What is it?”)
CHAPTER 3 Designing with Zynq (“How do I work with it?”)
CHAPTER 4 Device Comparisons (“Why do I need Zynq?”)
CHAPTER 5 Applications and Opportunities (“What can I do with it?”)
CHAPTER 6 The ZedBoard
CHAPTER 7 Education, Research and Training
CHAPTER 8 First Designs on Zynq
CHAPTER 9 Embedded Systems and FPGAs
CHAPTER 10 Zynq System-on-Chip Design Overview
CHAPTER 11 Zynq System-on-Chip Development
CHAPTER 12 Next Steps in Zynq SoC Design
CHAPTER 13 IP Block Design
CHAPTER 14 Spotlight on High-Level Synthesis
CHAPTER 15 Vivado HLS: A Closer Look
CHAPTER 16 Designing With Vivado High Level Synthesis
CHAPTER 17 IP Creation
CHAPTER 18 IP Reuse and Integration
CHAPTER 19 AXI Interfacing
CHAPTER 20 Adventures with IP Integrator
CHAPTER 21 Introduction to Operating Systems on Zynq
CHAPTER 22 Linux: An Overview
CHAPTER 23 The Linux Kernel
CHAPTER 24 Linux Booting

And for all of you Dummies Altera also has an ebook out which you can download HERE.

Ok, like any great product the idea and or the concept gets copied. Do not fall into the FPGA marketing hype. Xilinx has skipped the 20nm Zynq and will have a part that will blow your mind at 16nm, blogs coming soon. Why the node skip? Zynq at 28nm will cover your needs and as I said in an earlier blog, the competition at 20nm is not good. Simply adding in an ARM and calling it a SoC is not going to cut it. The point is, Xilinx executes near flawlessly which is proven today by shipping the 20nm UltraScale ahead of all competitors using the same fab (level playing field).

Also, do not fall into the marketing trap that you need hard floating point, why if soft gets you what you need without the sacrifice of fixed point? If you use the Arria 10, you will lose 5 TMACs of performance when compared with the Xilinx KU115. Yes, you may get 1.5 TFLOPs from Arria10, and 1.3 TFLOPS from Xilinx at 20nm, but are you willing to give up 5 TMACS for that 0.2 TFLOP advantage? The Xilinx KU115 will give you roughly 8.5 TMACS, while the Arria10 comes along with about 3.5 TMACS. Any engineer knows that is not a good deal, especially at least in my realm there is about an 80% fixed point arithmetic to 20% float.

The other marketing angle for the hard float is to appeal to the engineer to say that quantization analysis is just so complicated and hard, so just float your whole design. I frankly find that almost offensive and talking down to the world’s best designers of systems. Do marketing people really think that world class engineers do not know how to design systems? Try floating a CIC filter… Yikes. Bottom line, Floating point is not free and it will cost you in performance, hard or soft.

Not only does Xilinx have the silicon advantage, but the best tools to program using a higher level language. Altera can hype all they want about their OpenCL solution, the proof will be in the pudding, and one will see that Xilinx’s OpenCL solution will in fact be many times better. Chapter 15, Vivado HLS is my favorite chapter. I will keep saying this but Vivado HLS is simply the tool of the decade and will only keep getting better. Xilinx acquiring AutoESL to buy Autopilot was simply genius. All the blogs, PowerPoint, videos may not convince you but try the tool, and you will not be disappointed, especially if you are a VHDL/Verilog code monkey like me. Enjoy the free book and show the world what your Zynq can do!

September 24, 2014July 18, 2025

Explaining HAPS-DX in an elevator

Explaining HAPS-DX in an elevator
by Don Dingee on 09-24-2014 at 7:00 am
Categories: EDA, Synopsys

Every development team has been through this challenge: finding a tool that looks fantastic, then heading off to the manager one or two levels up who has enough signature authority for the purchase order. Signatures for amounts reading more than a couple of trailing zeros on POs are rarely free, or painless. Continue reading “Explaining HAPS-DX in an elevator”

September 23, 2014July 18, 2025

AMD Design IP Deal with Virage Logic… Oops… Synopsys

AMD Design IP Deal with Virage Logic… Oops… Synopsys
by Eric Esteve on 09-23-2014 at 9:59 am
Categories: EDA, Synopsys

Whoever has said that history never repeats itself should read this recent PR from AMD! The news can be summarized in three points:

Multi-year agreement gives AMD access to a range of Synopsys design IP including interface, memory compiler, logic library and analog IP for advanced FinFET process nodes
Synopsys acquires rights to AMD’s interface and foundation IP, and hires a team of engineers from AMD with IP R&D expertise
These agreements enable AMD to realize ongoing engineering efficiencies and focus engineering efforts on product differentiation

The deal content is in these first two points: AMD can get access to the most expensive IP from Synopsys, because designed for advanced FinFET process nodes, in exchange, Synopsys will hire a team of IP expert engineers from AMD, and get rights for existing AMD’s interface and foundation IP. By the way, FinFET is such a wonderful process that the extra cost for IP compared with bulk is not negligible as I have heard about 1/3[SUP]rd[/SUP] more…

This deal is very similar with a previous deal between AMD and Virage Logic in 2008, when the IP vendor was paid by AMD with rights to PCI Express, USB or SATA IP instead of cash to compensate the memory compiler and logic libraries. Thanks to this deal, Virage Logic had entered into Interface IP market, 18 months before to be acquired by Synopsys for $315 million in cash. No design team was involved in the 2008 deal, but this came less than one year later, when “NXP transfer over 160 employees and the assets associated with selected advanced CMOS libraries, IP blocks and SoC architecture along with other classes of semiconductor IP”. In both cases, these deals have helped Virage Logic to quickly develop their IP port-folio, in particular by including Interface IP.

The above picture, extracted from the “Interface IP Survey” last version (Release 6), has been specifically designed for Semiwiki and Linkedin readers. This is a graphic view of the ASIC and ASSP design start for HDMI, SATA, PCIe, USB 2, USB 3.0, Ethernet, MIPI and DDRn memory Controller IP. If you look at a form (between a circle to an ellipse), the “diameter” (the larger lenght) is proportional to the total number of design starts including such IP function, internally developed or acquired from an IP vendor. In the real life, some SoC may integrate several IP, so the forms may recover each other. For example, we know that an Application Processor SoC may integrate MIPI, HDMI, USB 3.0 and LPDDRn. On the other hand, some of these interfaces are not supposed to be integrated in the same ASIC/ASSP, like Ethernet and MIPI, so the forms are not recovering. SATA is an exception: there are too few design starts, so the form is small and can’t recover with every protocol it should, and MIPI & PCIe should recover a little bit, but the forms are too far. That’s the model limitations, but the picture gives a good view of the respective adoption rate of the various protocols.

The largest by far is (LP)DDRn. If you agree with the System-on-Chip definition, an “IC integrating a Processor (CPU or GPU) core”, you realize that about 100% of the SoC will integrate a memory controller. The more intuitive definition linked to the word “system” suggests that a SoC will be at the hearth of an electronic system, so the chip is expected to “interface” with other IC and with the outside world. That’s the reason why the DDRn form is not only the largest but this recovering with most of the other forms, representing the interface protocols.

From a business point of view, we have shown in a previous post that these interface protocols have exhibited a very strong growth during the past 5 years, and are expected to grow again during the next 5 years. That’s why the rights for interface IP from AMD had a great value 5 years ago for Virage Logic and today for Synopsys. I should have a more precise figure in the next few days, but I suspect the IP business generated with the above mentioned protocols to reach between $900 million to $1 billion by 2020…

When traditional EDA business is almost flat since many years, you better understand why the interface IP “cake” can attract Synopsys and Cadence, and also why these two companies are heavy investors. I don’t think only about the acquisitions that both companies have done during the last three or four years. As a matter of fact, each of them is building a large engineering team, if I mention 1,300 engineers, only dedicated to Design IP for Synopsys, I am probably below the real number as of today (certainly in fact, as this number does not take into account the above mentioned team from AMD). I guess that we can expect to soon get IP related news from Cadence…

You may find additional information here and the Table of Content for “Interface IP Survey 2010-2013 – Forecast 2014-2020” will be available soon (you may contact me through Linkedin if you want to receive it as soon as it will be completed).

Eric Esteve from IPNEST

September 23, 2014

The TSMC iPhone 6!

The TSMC iPhone 6!
by Daniel Nenni on 09-23-2014 at 7:00 am
Categories: Foundries, Intel Foundry, TSMC

Fortunately Paul McLellan and I missed IDF. Paul was atop Mt. Kilimanjaro and I was in Taiwan signing books. After reviewing the materials and watching the videos we really didn’t miss much in regards to mobile so no regrets. The Apple event would have been fun even though I won’t be buying an iPhone6 or an iWatch and I will tell you why.

In case you missed it, the first iPhone 6 tear down is up on iFixit and surprise-surprise it is filled with silicon from TSMC’s customers (Apple A8, Qualcomm: modem, PM IC – RF transiever – LTE receive and envelope tracking, Murata wifi module, Broadcom touchscreen controller, NXP NFC, and chips from Skyworks, InvenSense, Avago and TriQuint). The absence of Samsung silicon was not a surprise however and it supports my theory that, given the choice, fabless companies will partner with pure-play over IDM foundries, absolutely. The fact that Samsung and Apple have intellectual property issues and Samsung has constant anti Apple advertisements probably does not help either but that comes with competing with your customers I suppose.

Really Apple? Tanazania Leads US in Mobile Payments

Really Apple? Tanazania Leads US in Mobile Payments
by Paul McLellan on 09-23-2014 at 1:00 am
Categories: Mobile

I was in Tanzania a few weeks ago. One of the conceits that we have in the US is that we lead the world in technology. That is true in many areas but in mobile the US is a laggard. Just look at the fuss made about NFC payments in the new iPhone given that Japan had mobile payments over a decade ago.

Another area where the US is a laggard, or maybe it is the same area, is the capability to move money around by phone. In rough numbers, the world has only 2B bank accounts, 1B credit cards but 7B mobile phones. If you were starting from scratch you wouldn’t base a payment system on giving every customer cards and giving every merchant a reader, you would find a way to leverage the mobiles that everyone already has.

The area where this is most advanced is the area where banking is least advanced so there is not really any infrastructure to compete with. That is the M-Pesa system (pesa is the swahili for money) first introduced in Kenya and then in Tanzania. Driving around in Tanzania there were M-Pesa signs everywhere. Every bar, every little store, even little tents set up at the side of the road. M-Pesa was launched in 2007 by Vodafone subsidiaries.

How successful is M-Pesa? In a nice coincidence the Economist published just the table that I needed over the weekend. In Kenya, there are more accounts than there are people. In Tanzania there are only about 420 accounts per 1000 people but the value of all the transactions is a staggering 65% of GDP. It is “only” 55% in Kenya with even greater penetration. It is even 18% in Afghanistan (where it is called Roshan but it is still run by Vodafone).

People use M-Pesa for all sorts of things but one thing is that children working in cities can easily transfer money back to the villages where their parents live. In the past, since there were banks only in the city, there was no way to do this other than getting on a bus for what might be a very long round trip. The child goes to an M-Pesa store and pays the money in to transfer it to his or her own phone account. Then they transfer it to the parents account using the cellphone network. The parent goes to an M-Pesa store, shows the code on the phone and collects the cash.

Another area where US centric opinion tends to underestimate things is the size of internet and mobile businesses in China. For instance, China Mobile has over 750M subscribers. So that is not just twice the entire US population, it means that it is almost 3 times as big as the US carriers (AT&T, Verizon, T-Mobil, Sprint etc) put together. They plan to put in about 500,000 LTE base stations in the next few years. The scale is amazing.

How about internet commerce? Amazon is the world leader, right? Not even close. Since Alibaba just went public in New York last week you might already have seen this, but Alibaba is over twice times Amazon’s size, with $269B versus Amazon’s $116B. They do an astounding $9,368 per second of business. I sometimes like to point out that a modern semiconductor fab depreciates at around $20/second but this is a couple of orders of magnitude larger.

There was lots of noise when WhatsApp was purchased by Facebook. In China, the equivalent service is called WeChat (you can use it in the US too but it is mostly people who know someone in China who seem to). It makes far more money per person than WattsApp (although it has fewer subscribers but is growing exponentially).

So don’t assume the US leads in everything unless you actually know the facts.

Samsung 14nm FinFET Design with Cadence Tools

Samsung 14nm FinFET Design with Cadence Tools
by Daniel Payne on 09-22-2014 at 5:30 pm
Categories: Cadence, EDA, FinFET, Foundries, Samsung Foundry

The first consumer products with 20nm processing are arriving in 2014 like the 2 billion transistor A8 chip in the iPhone 6, however at the 14nm node there are new designs underway to continue the trend of Moore’s Law. To get a better feel for the challenges of designing with 14nm FinFET technology I watched a 23 minute video presentation by Dr. K.K. Lin of Samsung over at the Cadence site. I prefer listening to real EDA tool users instead of vendor presentations, because I get to learn their methodology and the benefits compared to previous approaches.

Samsung decided to create two versions of 14nm FinFET: 14LPE (early version) and 14LPP (lower power). You can start prototypes now and expect production by end of 2014. Other foundries have re-used much of their 20nm planar technology into 14nm FinFET, resulting in little size reduction whereas Samsung has an aggressive 78nm poly pitch that enables about 10% smaller areas. Performance improves up to 20% and power is reduced by 35% when going from 20nm planar to 14nm FinFET with Samsung. Cadence users have complete PDKs (Process Design Kits) available now.

The Virtuoso tools from Cadence enable 14nm design using the IC12 tech file with features like:

Virtuoso Space-based Router (SBR)
Analog Placer (AP)
Layout Dependent Effect (LDE)
Double Patterning Technology (DPT)

Pcells provide layout automation of FinFET transistors by adding FIN dummy above and below the device, plus quantized fingers:

Layout cell instances can be abutted to avoid any of the complex violations found in 14nm. DPT started at the 20nm node and continues at 14nm, so with Virtuoso you can interactively view any of the DPT issues like: coloring loop detection, color shorts and DPT DRC errors.

For custom IC designs you can perform interactive routing with a Virtuosofeature called pin to trunk (P2T), and designers at Samsung have measured turn-around time improvements between 14% and 63% on: source/drain routing, gate routing and general routing. The new Virtuoso space-based router (VSR) used on 14nm can improve routing productivity by up to 75%.

The impact of LDE issues is reduced in Virtuoso by an architecture that enables quick iterations between layout and simulation, even before the design is LVS clean. Using three automation features (Analog Placement, P2T and VSR) provided a 24% schedule reduction compared to older, more manual methods.

View the entire 23 minute video here at the Cadence site, and there’s no registration required.

September 22, 2014

Expansion at Calypto through Real Value Addition in SoC Design

Expansion at Calypto through Real Value Addition in SoC Design
by Pawan Fangaria on 09-22-2014 at 1:00 pm
Categories: EDA

When we get the notion of expansion of a company, it always provides a positive picture about something good happening to boost that expansion. There can be several reasons for expansion such as merger & acquisition, formation of joint venture or partnership, large customer orders and so on. However, organic expansion which happens due to real value addition into the products that drives customer demand and satisfaction brings eternal cheer and confidence among company’s workforce leading to ever increasing value of the products and the company’s general ecosystem.

These are the thoughts which came to my mind when I met Sanjiv Narayan, VP & Managing Director at Calyptoin its Noida office. Sanjiv has been a good friend of mine since my Cadence days; I admired his knowledge of synthesis, optimization and verification domain. He heads Calypto’s Noida site which has a strong committed workforce of about 60 people; 90% of the workforce is involved in R&D development, that’s quite impressive. Since we had met after a while, we had a long conversation on several aspects; I am summarizing some of the prominent ones below.

Accommodating the current team comfortably and looking forward to further expansion driven by growing adoption of their products, Calypto has already moved (this is the third time in last ten years) to a new facility equipped and ready to accommodate a larger team. The India team provides major R&D support to all product lines of Calypto. Sanjiv expects the new office to be able accommodate an additional 50% growth in headcount and Calypto is already aggressively hiring for R&D and Application Engineering positions in India. Calypto is seeing rising business and increased usage of their tools in Asia Pacific (AP) region. They already set up an office in Korea earlier this year to support Calypto’s Korean customers. The expanded Application Engineering and Services workforce in Noida will support the entire AP region. Calypto is also setting up an office in Bangalore – it should be operational before the end of the year.

So, what’s driving this expansion? Of course, Calypto has a pioneering product portfolio at system and RTL level coupled with the semiconductor industry’s unique formal verification technology; Catapult HLS tool, PowerPro power optimization tool at RTL level and SLEC sequential equivalence checker. What’s unique about them – Catapult can synthesize hardware descriptions written in either C++ or SystemC to RTL, no proprietary or specific standard is needed; PowerPro is reported to provide the best power saving in the industry with functionally clean RTL proven at the gate level; SLEC is the most versatile formal verification tool that can accurately check (through its unique sequential equivalence checking capability) equivalence between C++/SystemC and RTL (SLEC HLS) and RTL and optimized RTL (SLEC RTL and SLEC Pro) which may be obtained either manually or through the use of PowerPro.

Naturally, Calypto is gaining customers’ attention, increasing customer base and seeing consistent growth in its revenue over the years with top semiconductor companies using their products. To know more about their products/technologies and general technical learning, attend some of the upcoming events where Calypto is presenting –

Sep 25, 4:00 PM – 5:30 PM atDVCon India in Bangalore

Tutorial on “Low Power Design & Verification Using HLS” to be presented by Sanjiv Narayan, Sandeep Dagar, Vikas Tyagi and Vishal Sinha

Oct 1-2, 11 AM – 6 PM atARMTechCon in Santa Clara Convention Center, CA

Exhibit at Booth #715

Also read:
Accelerating SoC Verification Through HLS
How to Reduce Maximum Power at RTL Stage
Designing the Right Architecture Using HLS

Is Number of Signoff Corners an Issue?

Is Number of Signoff Corners an Issue?
by Daniel Nenni on 09-22-2014 at 12:00 am
Categories: EDA

Semiconductor companies continue to use the traditional corner-based signoff approach that has been developed more than 40+ years ago and has since remained mainly unchanged as an industry paradigm. Initially it had 2 corners, namely Worst Case (WC) and Best Case (BC) with the maximum and minimum cell delay respectively. Note that wire and via delays were negligible. Later, the number of corners increased to 4 and after that it has been growing exponentially, especially during last 10-15 years. Figure below illustrates the spread of timing signoff corners used in different design companies.

Number of timing signoff corners
One can see that the number of corners grows exponentially with increase of variation sources for each new technology node. Some people believe that it is possible to reduce corners, but it may be risky to remove any so-called “redundant” (or dominated, or less important, etc.) corners. For example, {SS-process + Fast-Metal} is needed for the setup check, because a violation may happen in a path where launch and data paths are cell-delay dominated and capture is metal-delay dominated. So, using only {SS-process + Slow-Metal} may lead to missing violations. Some companies also ignore a need for more corners to take into account Aging Degradation (AD), multi-voltage non-correlated or partially correlated domains (supplies), the temperature inversion, other effects (like the NTBI, Hot electron injection, etc.), FinFet, DPT (Double Pattern Technology), LSE (Layout Dependent Effects), etc., which may produce the extreme delays in some intermediate points.

Even with so many corners, there is no guarantee that we do not miss some violations due to non-linearity (like the cell delay vs. voltage) and even a non-monotonic behavior (like the temperature-inversion) for some variation-factors, and because of a non-perfectness of conventional tools and derating methods, and ignoring some physical phenomena like correlations. Also, we will need to add at least two more points for Aging Degradation (AD): the BOL (Begging-Of-Life) and the EOL (End-Of-Life).

Note that one can doubt if we really need to run BOL and EOL at all the PVT corners and is it fair to multiply all corners by 2. The answer is “yes ” and an explanation is similar to already used for some other variation-factors—most corners may not need to be run for BOL and EOL for typical paths, but there may be special not typical path structures (with cell- or net-delay dominations in different sub-paths) that need not “typical” age model. Let’s consider one example for hold check. A common mistake: There is no need for using SS library & EOL model, because all cell delays become slower. In reality, for some rare path structures, SS & EOL model is needed, because a violation may occur in a path where the launch and data paths are metal-delay dominated and the capture is cell-delay dominated.

Actually, even more corners may be needed because there is a need to add vias corners (or via RC-models) that are similar to the current wire RC models. Vias delays have become significant and are not correlated with RC-wire models. Example: the worst-case situation (corresponding to the minimum setup slack) is when the RC-worst model is used for wires and the RC-best model is used for vias. The capture path has big via delays with almost no wire delays; and cell delays are irrelevant here. Adding via models will increase the corner number by 4-5x.

Using so many PVT/RC/Via corners (>1000) may be not acceptable from the design time and costs considerations. Also, the number of signoff scenarios is a product of corners and modes (functional, test, etc.) and may become too big to be handled by the IC Compiler (ICC) or PrimeTime (PT) or other similar tools. Additionally, designers need to perform 10-30 ECO iterations for all those scenarios to close timing. The runtime has become a serious issue and may be a work-stop for emerging technologies.

Thus, the question is: Is the corner-based signoff and corner number becoming a serious problem?