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November 12, 2014

Who is REALLY Using TSMC 16FF+?

Who is REALLY Using TSMC 16FF+?
by Daniel Nenni on 11-12-2014 at 7:00 am
Categories: FinFET, Foundries, TSMC

As I wrote last week there is a whole list of companies on LinkedIn with people working on TSMC 16nm. Today TSMC released a list of customers that have risk production 16FF+ silicon. Most of us knew this already but now we can talk about it in more detail. This is a really big deal for the FinFET doubters out there. Just because Intel had all sorts of yield trouble with 14nm does NOT mean that TSMC will experience the same type of issues.

Also Read: Who is Using Samsung 14nm?

According to TSMC the 16FF+ process provides 40% more performance than 20nm or consumes 50% less power at the same speed. The first applications you will see of course are mobile, specifically stated is “high-end mobile” meaning that 16FF+ is much faster than Samsung 14nm. Computing, networking, and consumer applications are also mentioned.

Also Read: Let the FinFET Yield Controversy Begin!

As an example of high performance a 2.3GHz ARM Cortex®-A57 is referenced and for low power a 75mW Cortex-A53. Yield is also mentioned as being ahead of the curve in comparison of all the other TSMC nodes. Remember TSMC used the same metals for 16nm as it did for 20nm which in hindsight was simply brilliant. Solve the double patterning riddle first then add FinFETs and address the added fin variation challenges.

Also Read:Cliff Hou at TSMC OIP

As Cliff Hou mentioned in his keynote at last month’s TSMC OIP Forum, a wide variety of EDA tools and hundreds of process design kits with more than 100 IPs, all of which have been silicon validated, is already supported for 16nm. TSMC also stated that 16FF+ has close to 60 customer designs scheduled to tape out by the end of 2015. Coincidentally, high volume 16FF+ ramp should start in Q3 2015, just in time for the next Apple iPad refresh.

“Our successful ramp-up in 20SoC has blazed a trail for 16FF and 16FF+, allowing us to rapidly offer a highly competitive technology to achieve maximum value for customers’ products,” said TSMC President and Co-CEO, Dr. Mark Liu. “We believe this new process can provide our customers the right balance between performance and cost so they can best meet their design requirements and time-to-market goals.

“TSMC 16FF+ process technology enables Avago to design highly optimized custom silicon solutions for networking applications in cloud datacenters and enterprise networks,” said Hock Tan, President and CEO of Avago Technologies Limited. “TSMC’s 16FF+ process technology in combination with Avago’s industry leading SerDes, memory, processor cores, and design implementation techniques deliver unparalleled time-to-market, performance and power benefits to OEM customers.”

“Sixteen-nanometer FinFET Plus technology provides compelling performance per watt advantages, enabling a myriad wave of market inflection points such as Internet of Things, 5G networks and software defined networks,” said Tom Deitrich, Senior Vice President and General Manager for Freescale‘s Digital Networking group. “Powering the new virtualized network, a new family of Layerscape™ multicore processors using ARM® and Power Architecture® technologies will be Freescale’s first offerings to leverage this innovative process technology.”

“Our collaboration with TSMC on 16FF+ technology will give LG strong competitiveness with respect to power, performance and area in the mobile AP market,” said Bo-ik Sohn, Senior Vice President at LG Electronics. “We believe that the product made through our partnership with TSMC will meet the widespread consumer demand for distinctive mobile technology.”

“TSMC is a trusted technology partner, helping to drive MediaTek’s success over the past decade to deliver market leading SoCs,” said CJ Hsieh, President of MediaTek. “With TSMC’s first ever FinFET 3D architecture and enhanced plus version, MediaTek advances mobile and home entertainment SoCs demonstrating even faster speed, optimized power and reduced chip size. The performance boosts and power reduction for MediaTek’s processors and modem technologies, compared to previous generations, has proven TSMC’s 16FF+ to be a highly competitive process technology for our chipsets.”

“NVIDIA and TSMC have collaborated for more than 15 years to deliver complex GPU architectures on state-of-the-art process nodes,” said Jeff Fisher, Senior Vice President, GeForce Business Unit, NVIDIA. “Our partnership has delivered well over a billion GPUs that are deployed in everything from automobiles to supercomputers. Through working together on the next-generation 16nm FinFET process, we look forward to delivering industry-leading performance and power efficiency with future GPUs and SOCs.”

“Our partnership with TSMC enables us to address evolving semiconductor technologies and to provide state-of-the-art solutions for our customers in the automotive, industrial and ICT fields,” said Hisao Sakuta, Chairman & CEO of RenesasElectronics Corporation. “Now, we want to take full advantage of the 16FF+ technology to deliver added values for our customers in the advanced automotive information and ICT markets.”

“TSMC is once again demonstrating their leadership in the industry by delivering their 16FF+ process with exceptional results,” said Moshe Gavrielov, President and CEO of Xilinx. “This risk production milestone achievement and our continued close collaboration is enabling Xilinx to realize the industry’s highest FPGA performance per watt and an unprecedented level of programmable systems integration with the industry’s first All Programmable MPSoC and 3rd Generation 3D ICs.”

About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s owned capacity in 2014 is expected to be about 8.2 million (12-inch equivalent) wafers, including capacity from three advanced 12-inch GIGAFAB™ facilities, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC China. TSMC is the first foundry to provide both 20nm and 16nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.

More Articles by Daniel Nenni…..

November 12, 2014

HP’s Multi Jet Fusion 3D Printer — Rapid Prototyping to Mass Manufacturing

HP’s Multi Jet Fusion 3D Printer — Rapid Prototyping to Mass Manufacturing
by Charles DiLisio on 11-12-2014 at 1:00 am
Categories: General

On October 29[SUP]th[/SUP] HP announced their long-anticipated entry into the 3D printing market with the HP Multi Jet Fusion. The HP Multi Jet Fusion is an industrial 3D printer that is anticipated to be 10 times faster and 50% less than current systems. The system will be beta tested by customers in 2015 and in production in 2016.

The 3D printer market is anticipated to grow at 45+% annually. While there were rumors that HP would acquire an existing 3D printer company, such as 3D Systems (DDD), Stratasys (SSYS), ExOne (XONE), Arcam AB (AMAVF) or Voxeljet AG (VJET) — HP developed a unique system on its own. Gartner estimates 3D printer spending of $669M in 2014 with enterprise representing $536M and consumer spending of $133M. Wholers Associates estimates the sale of 3D products and services, which includes printers, ink and products is expected to grow to near $11B by 2021.

HP Multi Jet Fusion relies on the company’s 30 years of experience in 2D printing and sizable R&D budget. Terry Wohlders, president of Wohlers Associates, a leading market research firm in additive manufacturing believes the speed, quality, feature details (down to 5 micron) and colors is leading edge. Wohlders said: “Its, not only a game changer, it’s going to rewrite the rules in the 3D printing industry.”

HP Multi Jet Fusion – fine-tuned detail and color

HP Multi Jet Fusion – How it Works and Why Now?
The printer works by using a print bar that looks like a scanning bar on a typical 2D printer. The 3D print bar has 30,000 nozzles spraying 350 million drops a second of thermoplastic or other powdered material as it moves back and forth across the print platform. The printer combines attributes of a binder jet printing (like 2d inkjet printing) and selective laser sintering (SLS) (where layer upon layer of powder material is fused by heat). Please see HP Multi Jet Fusion technical white paper.

Why now? Well many of the core patents like selective sintering have expired or will expire in a year or so. Thus HP can leverage existing 2D printing technology and avoid spending money on developing processes for 3D printing.

Time is Money
PricewaterhouseCoopers in a survey of 100 top manufacturers that two-thirds are using 3D printing for either prototyping, custom parts or production. However, today, 3D industrial printers are used primarily for rapid prototyping – to slash development time and costs to test parts before mass production. Why? 3D printing today is too slow for volume manufacturing like injection molding. However, the HP Multi Jet Fusion with its speed, detail and color capabilities can move from rapid prototyping to low-volume mass production.

What this means:

Legitimize 3D Printing: HP’s entry with its considerable size, resources ($112B sales and $16B cash), brand and industrial customers using its 2D systems should be able help legitimize and expand the 3D printer market.

Small, Manufacturing Lots: Envision moving the 3D printer from the engineering prototype shop to the manufacturing floor. Multiple HP Multi Jet Fusion printers making replacement parts for automobiles, appliances, Kickstarter companies.

Rethinking Manufacturing and the Experience Curve: Now you don’t have to run factories to create inventory in advance of demand. Nor will you have to stock replacement parts, but only print when necessary. Also, you can modify a part design in real time. See my previous article: “What does the Ford Mustang and Intel’s Gordon Moore Have in Common with Local Motors? Experience Curve and the Divergent Future of Manufacturing.”

November 11, 2014June 14, 2019

Using Cadence PVS for Signoff at TowerJazz

Using Cadence PVS for Signoff at TowerJazz
by Daniel Payne on 11-11-2014 at 7:00 pm
Categories: Cadence, EDA

TowerJazzis a specialty foundry that provides IC manufacturing into several markets, like: RF, high-performance analog, power, imaging, consumer, automotive, medical, industrial and aerospace/defense. In June there was a presentation from Ofer Tamir of TowerJazz at DACin the Cadence theatre, so I had a chance this week to learn about how they use the Physical Verification System (PVS) from Cadence. Other EDA vendors offering competitive tools in this space include: Mentor, Synopsys and Tanner EDA.

TowerJazz is a publicly traded company and we’ve seen the stock price increase some 75% this year, so that’s keeping the shareholders quite happy:

You’ll find fabs from TowerJazz in Israel, California and Japan. They even has a 12″ fab processing 40nm chips. Their Process Development Kits (PDKs) are filled with useful features, libraries and models for AMS design engineers:

The Cadence PVS has much more than just Design Rule Checks (DRC) and Layout Versus Schematic (LVS) tools because for signoff you need to handle more effects:

Engineers at TowerJazz create all of the files that IC designers will need to run each of the Cadence PVS tools. The PVS runset is written in the Physical Verification Language (PVL) for tools that perform: DRC, LVS, ERC and Fill. Users of the older Assura-QRC flow will find the PVS-QRC flow quite similar to run. Since the Calibre tool from Mentor is so entrenched, there’s a utility to compare DRC results between PVS and Calibre.

The PVS decks supported by TowerJazz include 180 nm to 130 nm nodes:

IC designers run the Cadence PVS tools like DRC using the PDK from TowerJazz on their layouts and get feedback as both text and location for each DRC error.

Likewise, when running the LVS tool you can see and debug each mismatch both in text and graphically by cross-probing:

Extracting a parasitic netlist from layout is done with the QRC tool:

Using this QRC created netlist in a SPICE circuit simulator is the flow to get most accurate timing and power values for custom and AMS designs.

To enforce reliability rules for detecting Electro Static Discharge (ESD) issues there’s a tool called Programmable Electrical Rule Checker (PERC):

PERC tool results are similar to DRC or LVS by pin-pointing in the layout and schematic any technology-specific ESD issues.

Very large IC layout databases can be efficiently browsed with the PVS QuickView during error browsing and debugging steps.

Within TowerJazz they are doing design signoff with both Calibre and Cadence PVS tools. Users of Cadence Assura should consider migrating and adopting the PVS tools now.

View the complete 16 minute video online, and there is no registration required to view it.

November 11, 2014June 14, 2019

How Sonics Uses Jasper Formal Verification

How Sonics Uses Jasper Formal Verification
by Paul McLellan on 11-11-2014 at 7:00 am
Categories: Cadence, EDA, IP, Sonics

The Jasper part of Cadence announced jointly with Sonics a relationship whereby Sonics uses JasperGold Apps as part of their verification. I talked to Drew Wingard, the CTO, about how they use it.

One way is during the day when their design engineers use Jasper as part of their verification arsenal. Interestingly it is the design engineers that use it, not the verification engineers.

Formal verification is especially good at finding corner case problems that simulation misses. It is almost impossible to build a cache-coherent network without formal since you will never think of everything to simulate, for example. It finds deep bugs in multiprocessor systems, which is pretty much what a modern SoC is. Sonics have a bigger problem than an SoC in that it is so configurable so it is not just a matter of running formal to prove something about a static design. It goes without saying that it is not possible to generate exhaustively all the possible configurations or even anything close, any more than you can exhaustively simulate all conditions on a modern SoC.

But the big motivation for using JasperGold was at night when they run their nightly regressions. Sonics have discovered in the past that almost any error in the design eventually shows up as a protocol error, in much the same way that stuck-at faults are surprisingly powerful in testing ICs even though many faults are technically something else. The value in a network-on-chip (NoC) is often being able to mix and match protocols: ARM, AXI, OCP, old VSIA stuff even. For a long time Sonics have developed protocol checkers that make sure that they are executed properly. They even distribute these to their customers and always the first question when a customer reports a bug is to ask if they have turned the protocol checkers on. Often the customer is soon back: “my bad.”

So the first requirement to adopt JasperGold was that the protocol checkers could be used to generate formal constraints and assertions with only minimal incremental effort, otherwise adoption would be too time-consuming and expensive. That would then make it easy to run formal techniques in the nightly regressions alongside simulation.

The Sonics nightly regressions work by generating constrained random configurations and then running constrained random simulations on them, and now JasperGold too. There is a tradeoff between how many random configurations are generated and how deeply they are exercised, either in the number of vectors or the amount formal proof time that is allowed. After all, there is a fixed size regression farm and the nightly regressions have to run in a night, by definition. That way problems can be fixed the next day and licenses are freed up for use by engineers when they arrive at work.

Sonics have discovered that it is much better to generate lots of configurations and then do relatively shallow testing on them. After all, a bug that shows up after 21 transfers but doesn’t create any issues in the first 20 is not highly likely. Better to generate more configurations and do some constrained random testing using different starting seeds. In fact Sonics generate thousands every night.

With limited modifications they could reuse their existing protocol checkers (which are standard SystemVerilog constraints). The worst case was a protocol checker requiring about 15% rewrite. So the Sonics verification approach is to generate a huge number of configurations of the NoC(s). Test them a bit with all the protocol checkers using either simulation or now formal proof techniques. The fact that the same protocol checkers work in both environments makes this very powerful.

November 10, 2014December 27, 2023

What is up with CEVA?!?!?!

What is up with CEVA?!?!?!
by Daniel Nenni on 11-10-2014 at 7:00 pm
Categories: Ceva, IP

Semiconductor IP is definitely driving the rapid mobile expansion we are experiencing today and CEVA is a glaring example of that. Mobile design cycles are a fraction of what they used to be so who has time to create, integrate, AND validate your own IP blocks, especially at multiple foundries?

Just a little background, CEVA is really a DSP core and software company. Digital Signal Processors are big in cellular and other data dependent markets (mobile, digital home, networking, and infrastructure). The CEVA cores are synthesizable so you can customize them for performance, power, and cost which gives them access to a broad range of applications and customers. They are also programmable and can be quickly upgraded through software which is a big deal. We have been working withCEVA on SemiWiki for 2+ years now and I can tell you they are a very easy company to get along with, absolutely.

Check out the CEVA Virtual Demo Showroom and see some of the clever applications. Very cool indeed!

What I do not know however is how they posted such a monster quarter:

Total revenue for the third quarter of 2014 was $14.1 million
An increase of 41% compared to $10.0 million for Q3 of 2013
Licensing and related revenue for the third quarter of 2014 was $8.7 million
An increase of 121% compared to $3.9 million reported for Q3 of 2013
Royalty revenue for the third quarter of 2014 was $5.4 million
A decrease of 11% compared to $6.1 million reported for the third quarter of 2013
CEVA signed ten new license agreements. Four of the agreements were for CEVA DSP cores, platforms and software, and six were for CEVA connectivity IPs.
Target applications for customer deployment are LTE-Advanced handsets, mobile infrastructure, vision for surveillance equipment and digital cameras, access points and wearables
Geographically, six of the agreements signed were in the APAC, including Japan, three were in the U.S. and one was in Europe.

“Our third quarter results were driven by the strongest licensing quarter in the company’s history. We continue to experience a healthy demand for our products from new customers targeting a broad range of end markets. We are encouraged by our customers’ progress in LTE and low cost smartphone shipments, both of which delivered quarter-over-quarter and year-over-year unit growth.” Gideon Wertheizer, Chief Executive Officer

CEVA even did a nice infographic to help us digest all of this:http://www.ceva-dsp.com/infographic

Can someone out there shed some light on this for me? As soon as I can gather more data I will schedule a call with a CEVA executive so post some questions that will make me sound smart or send them in private SemiWiki email.

Power-Aware Verification in Mixed-Signal Simulation

Power-Aware Verification in Mixed-Signal Simulation
by Daniel Payne on 11-10-2014 at 7:00 am
Categories: EDA

My Samsung Galaxy Note 2 phone lasts about 1.5 days on a single battery charge, thanks in part to the clever power conservation approaches like when the screen is automatically dimmed then turned off after no activity. Mobile phones and many other battery-powered devices used today all need power-saving designs, which then means that engineers needs to verify the power management approaches. The Unified Power Format (UPF) standardized as IEEE 1801-2009 or 1801-2013 is a popular way to annotate your design with both the power and power control intentions.

What if you wanted to take into account the analog effects of the power management blocks? UPF doesn’t cover that, so you’re still open to errors in the design and verification of your power distribution network and verification of power states. Engineers at Infineon and Mentor Graphics have created a methodology to extend UPF to include mixed-signal verification, presenting a paper at DVCon Europeon October 14, 2014 and also in a recentWhite Paper.

Here’s the proposed power-aware mixed-signal verification environment:

With this type of verification environment the analog power supplies get synchronized with the power state of the UPF power domain, so it’s possible to reuse the standard UPF constructs. The mixed-signal verification tool elaborates the analog-UPF boundary, and then inserts the Power-Electrical (P2E) and Electrical-Power (E2P) connect elements.

Tire Pressure Monitoring System

Infineon engineers used the power-aware, mixed-signal verification on a tire pressure monitoring system (TPMS), shown in the following block diagram:

Design blocks of TPMS

This product has ten power domains, multiple operating modes, and multiple power states like:

Low-frequency
Low-power
Ultra-low power
High performance (micro Amps)
Power down mode (a few hundred nan Amps)
Standby mode

UPF helps define the power intent during physical implementation of the digital parts of the TPMS design. The on-chip voltage regulators create and regulate voltages ranging from 1V to 5V.

Previous Approach

A manual modeling approach was used previously where the digital part of the design was wrapped in a model (blue areas), then digital signals interfaced to analog with power-conversion models (pentagon shapes).

Manually editing a netlist and inserting power conversion model instances takes time, is error prone, and may not even match the actual power distribution network used by UPF. With this approach you couldn’t check for proper level shifting, or isolation and retention cell placement.

New Approach

With the Mentor simulator Questa ADMS you can use a power-aware mixed-signal verification flow. The simulator inserts the boundary elements between UPF and analog ports, keeping the power state and value in sync between the analog and digital domains. During verification of DVFS (Dynamic Voltage and Frequency Scaling) states of the design, the A2D and D2A logic boundary element include the primary power and ground port state plus the value of power domain logic signal belongs to.

Here’s what the power-aware logical boundary elements look like:

With this approach we don’t need the power conversion models, because the power information comes straight from UPF instead. With an analog-on-top methodology there is still a wrapper used.

For the highest verification accuracy a SPICE netlist was used for the custom power switches in order to see the voltage switching and control sequence timing.

An E2P boundary element helps define the power net state:

Simulation results show the transition from a High Performance state to Power Shutoff, and then to a Low Power state:

With this new approach we can verify that:

Correct level shifter units are inserted
Proper isolation behavior
Proper retention behavior
Assertions are working

Summary

It’s now possible to use a power-aware, mixed-signal verification methodology by extending a UPF flow. Benefits of this flow include faster verification times, higher accuracy of analog design units, verification of the actual power architecture, verification of the power states, and verification of power state transitions.

Read the complete White Paper here.

November 10, 2014

Money for data and your MEMS for free

Money for data and your MEMS for free
by Don Dingee on 11-10-2014 at 12:00 am
Categories: Foundries, TSMC

An ongoing IoT debate centers on the notion that just because we can do something does not mean we should. From discussions at the recent MEMS Executive Congress, looking at what TSMC and some others see as the endgame for a trillion sensors signals possible trouble ahead. Continue reading “Money for data and your MEMS for free”

November 9, 2014

Getting a Quote Without Talking to a Salesman

Getting a Quote Without Talking to a Salesman
by Paul McLellan on 11-09-2014 at 4:00 pm
Categories: eSilicon, Semiconductor Services

VLSI Technology, for those of you not of a certain age, was one of the companies that, along with LSI Logic, created the ASIC business. One challenge in ASIC is that the customer needs to decide which ASIC company to use (since the libraries and technologies are all different) meaning they needed to get quotes from several companies. The procedure was tortuous. The customer would contact a VLSI salesperson who would collect the relevant data about the design. This would then be passed to the design center (later technology center) that was going to support the design who would estimate the cost of the design in manufacturing (and any services that were to be provided). The design center manager, who was essentially local marketing, would manually work out the die size and then use our cost model (hopelessly bad in the early days) to work out the cost. Margined up he (I don’t think we had any female design center managers) would then tell the salesperson the price. There would sometimes be a negotiation, often along the lines of Japanese semiconductor company X quoted half as much, to which we would point out that they didn’t actually have the capability to do a design that complex (usually true). LSI Logic would usually quote around the same price as we did. If the customer was sensible they would pick LSI if they decided to do a gate-array and VLSI if they decided to do a cell-based design. If they picked Japanese semiconductor X they would usually be back 6 months later when everything had gone pear-shaped (where does that phrase come from?).

The whole process might take weeks. By the way, the salesperson was never told the estimated cost, just the price, so that they didn’t assume that they had more flexibility in negotiation than their instructions. As an aside that is one reason that software negotiations are so different from hardware, the salesperson knows that the actual marginal cost is basically zero. And so does the customer.

Given that the process took weeks, it was really hard to handle the customer who came back and said “the price is too high”, what if I halve the size of the RAM and put it in a cheaper package. More weeks.

Until comparatively recently, getting a quote from anyone was basically the same process. Yes, the cost models had improved. Yes, spreadsheets had become ubiquitous. But it was basically the same: tell us about the design, here’s a price. And it still took weeks.

At its peak, VLSI Technology roughly brought 200 designs into production a year, which probably means 250 design starts (including ones that got canceled) meaning maybe 700 quotes since customers would typically get 2-3 quotes before picking a supplier. That is a lot of work, much of it busy work. The designs we won obviously also had to cover all the costs of quoting the designs we lost.

eSilicon is a fabless ASIC company. Well, and more. It does designs starting from all sorts of points depending on what the customer wants, and then delivers (usually) packaged parts to a price. Sometimes the customer does all the design and just uses eSilicon for manufacturing. Sometimes they use eSilicon IP. Sometimes eSilicon provides some level of design services. And sometimes, companies just get eSilicon to manage their production operations.

Internally, they realized that the manual process of estimating what they should quote the customer was too slow (still measured in weeks) and so they automated the process. They created a system that their experts could use to turn a quote in a day. Not only that, it meant that the internal cost of a quote to eSilicon was pretty low.

But eSilicon realized they could go one step further. Why involve their own experts at all? If they put the quote system on their website then customers could do all the work (self-service gas stations or ATMs anyone?) and get their own quotes. Not only that, since iteration was so much easier, customers could home in on the sweet-spot of their functionality/price point. They started just with MPW shuttles but then they extended it to full volume production (at this point just with TSMC). That’s right, you can go online and get a quote from eSilicon for your design in TSMC production untouched by human hand. And iterate that quote a dozen times for different configurations, packages, volumes and so on. Its online, nobody is going to complain about how much quote busy work you are creating any more than the gas station will complain if you only put in 1 gallon each day.

I’ve actually used their quote system for my (hypothetical, obviously) design. It works just like it says on the can. There is a design entry phase where you give all the parameters of the design. The actual quote takes less than a minute to generate. And it is probably worth emphasizing that it is a quote. A real binding quote. If you sign it, then eSilicon will honor the price.

See eSilicon and the 10 minute quote

If you want to know more, there is a webinar next Wednesday at 9am Pacific. Mike Gianfagna is moderating a panel so I can’t claim there is absolutely no marketing but it is mostly about people’s experience at using the quote system. The panelists are:

Bil Brennan from Credo Semiconductor
Trevor Hyatt from IDT
Mahesh Tirupattur from Analog Bits

For more details and to register for the webinar go here.

Who is Using Samsung 14nm?

Who is Using Samsung 14nm?
by Daniel Nenni on 11-09-2014 at 7:00 am
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

As I have mentioned before, there are very few secrets in Silicon Valley. Just last week I was minding my own business at a Starbucks when I overheard two engineers complaining about Samsung 14nm shuttles being delayed. They had badges on but I won’t out them because it could have easily been any of the fabless companies in Silicon Valley since just about all of them are working with Samsung this time around, even Apple.

Another good source on who is using what foundry at 14nm and 16nm is LinkedIn. If you are a premium member you can do advanced searches for the fabless company of choice with “14nm”, “16nm” or “FinFET” as key search terms. Good thing TSMC chose a different path and named it 16nm so we can get better search results. You will find Apple, Qualcomm, Broadcom, Marvell, Nvidia, AMD, Cisco, LSI, Avago, Oracle, Freescale, Jupiter, SanDisk, etc… all of the leading edge fabless semiconductor companies.

Of course I have > 20k connections so it makes it a bit easier since hundreds of my 1[SUP]st[/SUP] connections are doing FinFETs. I’m told that LinkedIn caps connections at 30k so if you want to connect to me you had better not delay. I’m linked to the majority of the SemiWiki fan base so you can do the math on that one if you really want to know how many registered members we have.

Based on the LinkedIn searches I did, all companies designing with FinFETs are using TSMC 16nm. Most are also using Samsung 14nm but some are TSMC loyal customers, Broadcom, Oracle, and Xilinx to name a few. I couldn’t find a company that is only Samsung 14nm which supports my opinion that Samsung is being used as a price lever against TSMC. Of course when I say Samsung 14nm it includes GlobalFoundries as they have a “copy exact” version running up there in Malta, NY.

Try a “10nm” search and you may be surprised at how many people are working on it already. There is also mention of work at 7nm. You can search “Intel 14nm” and see that only Altera, Tabula, and Achronix are working on it. The other Intel Custom Foundry customers must not be doing the actual AMS and layout work yet or Intel is doing it for them.

The nice thing about Apple is that they have a set annual release schedule which is in September. In order to get wafers in time for a September 2015 iProduct refresh the designs must be taped out in Q4 2014 so fabless semiconductor professionals like myself now know for sure which foundry gets what iProduct next year. It is still fun however to watch the regular journalists go all tabloid on this to get cheap clicks for their advertisements. Some of those same journalists are STILL saying Samsung is providing Apple with 20nm parts which is not true.

Where will Apple Manufacture the next iPhone Brain?
by Daniel Nenni Published on 07-17-2013

The not so nice thing about Apple is that they seem to take unfair advantage of the supply chain. This comes from the legal action between Apple and GTAT over a VERY one sided sapphire display contract that may bankrupt GTAT:

“When GTAT’s management expressed their obvious concerns to Apple regarding the deal terms during the contract negotiations, Apple responded that similar terms are required for other Apple suppliers and that GTAT should: ‘Put on your big boy pants and accept the agreement.’”

Disclaimer: The LinkedIn search engine is not great so results may vary depending on who you are connected to and what type of membership you have.

November 8, 2014

Look who is Leading the World Semiconductor Business

Look who is Leading the World Semiconductor Business
by Pawan Fangaria on 11-08-2014 at 7:00 pm
Categories: EDA, Foundries

A couple of days ago I was reading a news article which said how long the world economy will be dependent on a single engine to drive it; obviously that single engine is USA. If we consider the overall economy, definitely USA is driving it, and semiconductor is a large part of it. The semiconductor is driving electronics and that is attracting other countries across the globe to setup semiconductor shops, fabs to be specific; first to be self reliant and then to be able to supply to neighbouring countries. Sometime ago I had learnt that Chinese Govt has planned to spend ~$170B in 5 – 10 years to support chip industry within the country to reduce their import bill on semiconductor chips. India’s electronics import bill is also bulging and it has been planning since long to setup foundries to reduce chip import and develop electronics in-house. Anyway, that’s not the point; the point is who is leading this space.

What caught my attention when I looked at the IC Insights’ 2014 forecast preview reportof top 20 semiconductor companies’ sales figures for 2013 and 2014? While semiconductor industry is seeing robust growth of 9% with top 20 companies, 9 companies out of those are set to register double digit growth, and 3 companies, TSMCand Media Tekin Taiwan and SK Hynixin South Korea are set to register highest >20% growth.

Taking a closure look, I found interesting data; combine the three companies in Taiwan (TSMC, Media Tek and UMC) and two companies in South Korea (Samsungand SK Hynix) and you see ~34.5% of total sales ($89627M) of top 20 in 2014 are here! So what does it convey, with highest growth and lion’s share in total sales of top 20 semiconductor companies? Are these two countries set to drive the world semiconductor business?

Looking from a different angle, among the pure-play foundries, TSMC is the top manufacturer and supplier of chips. The only other pure-play foundry in top 20 companies is UMC, so can we say Taiwan is the leader in pure-play foundry business? They are the top suppliers for fabless companies around the world, and fabless, in my view, is the main driver of semiconductor industry today.

I see Intelat the top with 6% growth in ‘pure-play IDM’ category. Do we see Intel transforming more into pure-play now? Is IDM business sustainable?

I guess we may be able to see more detailed data when the final report gets published by the end of this month. It will be interesting to see the break up foundry, design and other businesses of Samsung and Intel, provided they publish those with break-up view.

I see that 2015 McClean Report is also scheduled to be released in Jan 2015 which has 400+ tables and graphs and there are seminars on the report scheduled in Jan, next year. It will be interesting to know about those details.