SemiWiki – Page 775 – The Open Forum for Semiconductor Professionals

January 19, 2015

FDSOI jump-start 2015 in Tokyo this week

FDSOI jump-start 2015 in Tokyo this week
by Eric Esteve on 01-19-2015 at 4:38 am
Categories: FD-SOI, Foundries, STMicroelectronics

This news in May 2014 that Samsung had licensed FD-SOI Technology from ST-Microelectronics was really amazing, as most of the industry was expecting this kind of agreement, but not with the #2 SC Company. But since May 2014 the news flow has been quite reduced, we can imagine that both SC companies had a lot work to do for transforming the agreement into real. Transferring a complete new process is certainly a heavy task (but I am not an expert), building an efficient ASIC flow, including EDA tools and maybe as much important the right IP offer can take several quarters. It seems that Samsung will unveil their FD-SOI offer during the RF-SOI and FD-SOI Forum, organized by the SOI consortium in Tokyo this Friday, January 23[SUP]rd[/SUP]. If you don’t travel to Tokyo this week (I don’t) you will have to wait for the proceedings to be released, it will certainly be worth the search on: RF-SOI and FD-SOI Forum

If you are not familiar with SOI, let’s me clarify the difference: RF-SOI is dedicated to pure analog IC (Radio Frequency), as the Silicon On Insulator technology provides strong advantages for analog designs: “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.” This sentence is extracted from this blog.

Samsung has licensed Fully Depleted (FD)-SOI, which technology is dedicated to digital designs. The supported nodes are 28nm (already in production at ST) and 14nm currently in development if not prototyping. We have covered the various application supported by FD-SOI ASIC at ST. It was surprising, but the mobile was not the preferred application! 28nm FD-SOI can also target performance hungry networking application and you can check in this recent blog for the mention of ST design-win of a communication infrastructure ASIC in 14nm FD-SOI. Nevertheless, Samsung foundry business is likely to target the very high volume applications, and what is higher than mobile? FD-SOI can provide the Holy Grail feature for an Application Processor: Ultra Low-Power and Performance.

If you take a look at the FD-SOI part of the agenda, the foundry ecosystem is represented by ST and Samsung, and I am very anxious to read Samsung presentation (and to report it in Semiwiki)… be patient.

Any designer knows that the technology availability is necessary, but no more sufficient to cope with the Time to Market and integration requirement. A complete Ecosystem has to include a strong IP (and EDA obviously) offer. The large and fast growing IP vendors, Synopsys and Cadence are presenting in Tokyo. You may be surprised not seeing ARM (the undisputed #1 vendor), but don’t worry: one of the very first chip released by ST a couple of years ago was an Application Processor, integrating ARM 9 core, and more recently an AP integrating ARM® Cortex™-A53 and Cortex™-A57 64-bit processor on 28nm FD-SOI.

The presence of Verisilicon in this agenda is very important, as the ASIC Company is very strong on the Chinese market. When I met with Mark Ma, traveling from China to IP-SoC in Grenoble last November, his first question was about FD-SOI. The technology is clearly becoming hot, generating a real interest in the country…

This SOI Forum taking place in Japan, having a company like Sony sharing about their design experiences with FD-SOI is almost a symbol: FD-SOI penetration in consumer application has started (if you agree to include mobile into consumer, as a smartphone or a tablet is definitely a consumer oriented product).

Next “rendez vous”: SOI Forum in San Francisco on February 27[SUP]th[/SUP], I was told that new names will be added to this agenda, we will disclose it as soon as it will be official, but I am sure you can guess who is missing in Tokyo and should be present in California!
From Eric Esteve from IPNEST

January 18, 2015

Wireless Charging: Magnetic Induction or Magnetic Resonance?

Wireless Charging: Magnetic Induction or Magnetic Resonance?
by Majeed Ahmad on 01-18-2015 at 7:00 pm
Categories: Mobile

Standard wars are no stranger to technology business. In fact, they are the norm. Take, for instance, the rock star technology of 2015—wireless charging. Magnetic induction or magnetic resonance: which standard will dominate the wireless power ecosystem?

That’s the crucial question while wireless charging continues to win the prominence in the technology industry, and the same time, looks akin to an assortment of workable ideas with a number of pros and cons. The stellar promise of wireless power comes down to a critical premise: clarity that OEMs like smartphone makers need for making decision about incorporating wireless charging as a standard feature in their products.

Ask Integrated Device Technology Inc., the company that offers wireless charging products for both magnetic induction and magnetic resonance technologies and is a board member of the Wireless Power Consortium (WPC) and Alliance for Wireless Power (A4WP) standard bodies. According to Arman Naghavi, Vice President and General Manager of the Analog and Power Division at IDT, “right now the wireless power technology is at step one if there are going to be ten steps.”

So it’d be worthwhile to have a look at the wireless power standards maze and make a sense of the technology merits amid this standards battle and the possible consolidation of these standards later this year.

Magnetic Induction: Device on Mat

The technology is powered by two coils of wire: the coil at the charging station produces an oscillating magnetic field, which in turn induces an alternating current that is received by the coil at the device being charged.

Image credit: IDT

Qi (pronounced as chee) is driving the magnetic induction wireless charging standard and boasts more than 200 members. The Qi standard—developed by WPC, which was established back in 2008—won early adoption but has taken the back seat due to a number of compromises. First and foremost, it’s slightly more expensive to produce compared to methods without a coil.

Second, because Qi uses tightly coupled coils for high transfer efficiency, the arrangement is sensitive to coils misalignment that eventually leads to smaller distances between device and docking station.

Another wireless power standard, which uses inductive charging, has been developed by the Power Matters Alliance (PMA). The PMA standard, which is quite similar to Qi, has Starbucks and MacDonald’s among its early adopters. It has recently joined hands with A4WP, the standards body driving the adoption wireless charging based on magnetic resonance technology.

Magnetic Resonance: Proximity

The magnetic resonance technology still uses a loosely coupled coil arrangement that creates a usable magnetic field; but it also tunes the frequency of oscillation to precisely match between transmitter and receiver. As compared to closely-coupled coils in magnetic induction, magnetic resonance technology increases transfer distance, but looser coupling between the coils leads to suboptimal power transfer.

The Rezence standard, spearheaded by A4WP, promises to charge multiple devices without having to worry about alignment and states 5 cm as a typical operating distance. The charging accessories and mobile devices based on the Rezence standard are expected to be available later this year.

Rezence block diagram (source: A4WP)

Consolidation Ahead

Chipmakers like Broadcom, IDT and MediaTek are launching board and coil designs that support both inductive and resonant coil systems. The partnership recently announced by A4WP and PMA is another harbinger of the coming consolidation within the wireless power standards domain that will encourage device OEMs to commit to the highly promising but still embryonic wireless charging feature.

Another notable indication of the imminent consolidation in the wireless power standards comes from the fact that industry heavyweights like Qualcomm and Samsung, once staunch supporters of A4WP, are now backing up Qi as well. The fragmented world of wireless power merely shows the infancy state of the technology and the fact that there are still missing links within wireless charging technology landscape.

Bridge standards and dual-standard products could fill the void and bring more OEMs into the wireless power fold. Meanwhile, the two competing wireless charging technologies will most likely continue to collide and converge. Steve Goacher, Business Development Manager for TI’s Analog Wireless Power Group, believes that both magnetic induction and magnetic resonance wireless charging standards will have relevance in the future. “Each technology has its pros and cons and I don’t see one dominating the other.”

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

January 18, 2015

Tracing methods to multicore gladness

Tracing methods to multicore gladness
by Don Dingee on 01-18-2015 at 9:00 am
Categories: EDA

Multiple processor cores are now a given in SoCs. Grabbing IP blocks and laying them in a multicore design may be the easy part. While verification is extremely important, it is only the start – obtaining real-world performance depends on the combination of multicore hardware and actual application software. What should engineers look for in evaluating a multicore design?

A new white paper series from Mentor Embedded provides a perspective on this question. Compared to the single core, or more accurately core-centric approach, author Manfred Kreutzer suggests a multicore approach must address three issues for success.

The first is obvious: software must capitalize on concurrency and parallelism. Some scenarios may have the luxury of having roughly the same number of threads and cores, but in most cases, threads will likely outnumber cores. If an overwhelming number of tasks vastly outnumbers cores, this kicks off thread migration, with a high degree of time-slicing and likely significant numbers of cache misses. Visualizing what threads are on what core provides clues into how well tasks are partitioned and assigned.

Resource utilization is the second issue. Even in simpler cases, threads are often non-symmetric; this results in some cores being near fully loaded, and some cores less loaded. There can be conflicts when I/O or interprocess communication enter the picture, throwing off an otherwise efficient thread of execution. This also hits at decisions such as core scaling; for instance, are eight cores necessarily better than four? The answer may not be so simple if more cores wait around more often, or fewer cores churn constantly at full power. Core asymmetry, such as ARM big.LITTLE or using GPU or DSP cores to accelerate tasks, may also be a consideration.

That suggests a third issue, which is a rude awakening for many designers: power consumption is highly software dependent. This is a result of a combination of factors, starting with core partitioning and DVFS, leading into caching and memory allocation, and to system issues such as waiting for I/O resources. In short, implementations must be power-aware – in both hardware and software. One of the capabilities needed is to trace thread execution and power consumption together, showing a correlation. Just as earlier generations of software tracing focused on source code constructs that were hogging execution time, newer tools can look for power hogs.

Doesn’t observing more variables mean more overhead? Most IP designs today are instrumented with performance counters, allowing sampling utilities to quickly grab snapshots. Sampling is best for a statistical overview of what is happening, not a detailed sequence of specific events. For more in depth analysis, tracing performs consistent logging of system and user application events with time stamps, without blowing up overhead.

Tracing operates all the way from the hardware performance counters up to full application code, allowing not only a view of what is happening, but exactly why. Analysis based on tracing suggests how to improve the design. For instance, applying kernel tracing – even without any intent of debugging or modifying kernel code – can show how the system interacts with the kernel. User application space tracing can expose issues such as calls to pre-packaged libraries where no source is available.

The conclusion is tracing scenarios in multicore designs need to consider mixed domain data – a combination of elements grabbed from hardware and software, in kernel and application space. Rather than doing orthogonal analysis and trying to connect the dots, tools can provide correlated data from all these domains and illustrate cause and effect. A key here is support for the LTTng open source tracing framework for Linux.

For the complete text of the white paper (one-time Mentor registration required), visit:

Development of Complex Multicore Systems: Tracing Challenges and Concepts (Part One)

Part Two of the white paper series goes deeper into a tracing cycle and use of Mentor Embedded Sourcery Analyzer tools to explore these tracing concepts. Pawan Fangaria has further analysis:

Tracing Insight into Advanced Multicore Systems

January 17, 2015June 14, 2019

Johan Peeters on quick IP check through Cdiff

Johan Peeters on quick IP check through Cdiff
by Pawan Fangaria on 01-17-2015 at 8:00 am
Categories: EDA, Fractal Technologies

On the face of it, if we consider a simple ‘diff’ utility, it doesn’t need any explanation; almost everyone in our community would have used it. But imagine the CTO of a company investing his time in explaining how beneficial a specialized ‘Cdiff’ function can be in evaluating IP. Today’s SoC design world can’t live without IP and hence it’s worth looking at it in detail. Let’s take a dig at it to find out how Cdiff can help in quickly checking an IP.

Fractal TechnologiesCTO, Johan Peeters says that Cdiff (you may call it Crossfire-diff) is a result of active discussions with the Crossfire user-community who is very explorative; which is natural as the time-to-market window is very short, they have to find alternative ways of doing their design with whatever is provided by a tool or technology. It’s the eyes of a smart tool provider who catches up on what is repeatedly being done and automates the same. It was observed that very frequently designers were inspecting new models to locate any differences with the previous ones. Although Crossfire could be used to locate those differences in other ways, a push button approach with a Cdiff option on the GUI is much smarter way to improve designers’ productivity.

One can quickly check every new IP shipment for the requested changes as well as absence of any unexpected or spurious changes to qualify the IP for use; of course Crossfire can anyway check the whole IP for quality, but the Cdiff option can quickly do the in-coming acceptance test against a standard golden. The option can be set for full diff between two .lib files with complete check of parameter values along with any tolerance limit.

It could be argued why gvimdiff can’t be used. Well, it can’t, imagine the kind of result you are going to get by comparing two .lib files; formatting, ordering and various indents can lead to very different results altogether. Cdiff on the other hand checks the .lib semantics as intended and flags meaningful real issues such as a missing pin, cell or an extra reset-to-Q arc on a flop etc. Cdiff is smart in the sense that it uses gvimdiff functionality in reporting. Above picture shows an example where two .lib files are shown in gvimdiff with identical cell order and text formatting. It highlights only an extra arc in the second .lib file with a message to locate it in the original file. Now imagine locating just this one arc difference among a large number of different process conditions and formatting differences by using gvimdiff!

Another angle to look at Cdiff from design perspective is that it lets a designer converge a design to tape-out faster. Imagine at the tape-out time, your IP supplier provided a small incremental update in the IP. You can quickly check for the intended change and if there are other changes that implicate other steps of the flow such as GDS and characterization then you can discuss with your IP supplier to know about the reasons to do that. The precious design time at the tape-out stage can be utilized in these discussions, rather than re-qualifying the whole IP through Crossfire, which is anyway a given.

From a difference from golden perspective, Cdiff does all that what Crossfire does and provides the differences in cells, pins, timing arcs, pin shapes, cell functionalities etc. However, Crossfire is much versatile in assessing the quality of an IP such as pin routability, cell-delay monotony through temperature, and so on.

Read the whitepaperwhere Johan answers in detail to intriguing queries from designer community. He also speaks about future capabilities which can be added in Cdiff, such as ‘filter on differences-of-interest’ and leveraging the concept with repositories.

Intel Q4 and 2014 Results

Intel Q4 and 2014 Results
by Paul McLellan on 01-16-2015 at 5:03 pm
Categories: Foundries, Intel Foundry

Intel announced their results yesterday for last quarter (and the year). And they were good financially. As Brian Krzanich said:The fourth quarter marked a strong finish to a great year. We began 2014 expecting roughly flat year-over-year revenue and operating income. Instead the company’s full year revenue grew 6% touching all time record of $55.9 billion. At the same time, operating income rose 25%.

We initially forecasted revenue growth [for the datacenter group] in the low to mid teens with operating profit growing faster than revenue. We exceeded those higher expectations and revenue is up 18%. The operating profit expanded by a remarkable 31%.

They beat Q4 guidance slightly and EPS by quite a lot and margins were up (all good). But Q1 guidance going forward was to lower expectations. In particular they forecast gross margins at around 60% compared to 65.3% this quarter. That is a big drop. Analysts hate this, but I think it is inevitable that as Intel starts to get traction in IoT, tablets and even mobile then margins have to go down from what you can get for top-of-the-line microprocessors for the datacenter business. Stacey, the CFO, said it was connected to 14nm ramp and margins should be up a little later in the year. So 14nm is still a bit behind on yield I’m guessing.

And they do seem to be doing something in IoT. As Brian said:Finally, you see us moving quickly to wearables, to our growing portfolio of collaborations with Google Glass, fashion and fitness brands like Fossil, Oakley, Opening Ceremony and SMS Audio along with our own products like the Basis Peak and the Curie Module, a computers the size of a button.

As always here at Semiwiki we are less interested in the financial stuff than the other color. After all we all know Intel is a powerhouse in servers and datacenters. How are they doing in mobile? How are the process ramps going? There was lots of information in the call and especially in the replies to the questions.

Firstly tablets. Intel planned on shipping 40 millions chips (along with around $50 per chip in negative revenue) to establish themselves in the market. They ended up shipping 46 million and established themselves as “one of the industries largest merchant silicon providers”. Although “merchant” is a bit of a stretch when you are losing money and making it up on volume. Going forward they expect to grow about as fast as the tablet market does, but since almost all forecasts are flat to down (iPad sales actually fell last quarter) that is not a high growth market. Of course if they can keep their market share now that they have 14nm product, and if 14nm is really a lot cheaper they can increase their profitability. It is not clear (and nobody asked) if they are still shipping negative revenue on their current chips, essentially buying market share.

Intel merged mobile with laptops into MCG (mobile and communications group). Mobile was losing $1B per quarter and will presumably continue to lose a lot of money since Brian said in the questions that:Stacy and I are committed to drive $800 million out of this business for ’15.

But in subsequent questions a lot of that was the expectations of cutting back on negative revenue. So best case is that they are only going to lose $800M per quarter.

Brian was asked about 10nm. He replied:We are timing on 10-nanometers. We are not going to come out with—we’ll be introducing a 10-nanometer to the marketplace in general, probably until the end of this year. So we will give, as we go through the year, probably by the investor meeting in November, we’ll give you an outlook on how and what timing is for 10-nanometers.

So that’s clear then!

Brian also talked about Broadwell versus similar products at the same stage of their life. His reply is again a bit opaqueI would take you back to the graph I showed at the investor meeting because I actually showed a non-normalized cost that showed Broadwell relative to other products at the same stage of manufacturing. And so what that chart shows is the churn up in the first half of this year. So the early stage of the Broadwell ramp because of some of the old issues that we’ve talked about, it is higher. On a non-normalized basis, it’s a higher cost. But by the time we get into the back half of the year on a non-normalized basis, Broadwell actually is less expensive than those other products at the same stage of their life.

I think that means that currently yields on 14nm are still not where they want them to be but by the end of 2015 they expect per transistor costs for 14nm to be below 22nm.

So how are they doing in mobile (not tablets, real mobile) where they have a product called SoFIA. Actually it is a series, the current one being SoFIA 3G (so basically already pretty obsolete), then a SoFIA LTE modem (I don’t know if this means that they will have their LTE modem on an Intel process, currently it is TSMC). Anyway, they have finished internal qualification, and now need to go to the carriers for their certification (what used to be called “type approval”). They don’t expect to ramp until the second half of the year. So it is going to be at least another year before we have a clue whether Intel is really in or out of mobile.

SeekingAlpha transcript of the call is here.

Google Glass is Dead, ARA Phone is Prototyped

Google Glass is Dead, ARA Phone is Prototyped
by Eric Esteve on 01-16-2015 at 1:00 pm
Categories: IoT, Mobile

These two products are linked because they have been invented by Google and both are disruptive technologies. Like was the Apple’s Newton tablet launched in CES Chicago in 1992 and finally stopped in 1998, due to the lack of success. To born again in 2010 as the well-known and best seller iPad in 2010, creating a new market segment (Tablet) generating 221 million units sales in 2013 (total market) and associated SC revenue estimated in the $12 to $15 billion. So when saying that Google Glass is dead, we must be cautious.

About Google ARA, I would just ask you a question: would you buy the pictured below product? Just a reminder: this is a phone…

In fact Google ARA is a “modular” phone, so you can add modules to a body from Google. The modules can be sold by any of the Google’s partners. Innovative capacitive interconnects and other new connectors have been defined to support the project. From a protocol standpoint, Google has wisely selected a proven Interface, UniPro specification and the associated MIPI M-PHY defined by the MIPI Alliance, and used for example to support Unified Flash Specification (UFS). Thus any module designer has to integrate MIPI UniPro/M-PHY to make sure that the product will smoothly interoperate with the body.

So far, so good (Except that the prototype demonstrated during Project Ara Developer Conference on the 14th of January stop working after a minute or so and could not boot anymore… but nobody’s perfect)

As far as I know from reading the press during 2014, Google has defined a rule specific to ARA: any module should have been tested and validated with any other existing module. I honestly don’t know if this rule is still valid, but in this case, such a rule would be a major drawback, as the number of required interoperability test that a new module would have to comply with would go up exponentially! Such a rule is what we could call a false good idea, working only on the paper, but not in the real world…

To come back with Google Glass, you can verify (above picture) that you can’t find it anymore on Google. I must say that I am not really surprised to see the product exiting the market! I remember some of the sales arguments for these glasses:

I you run a bicycle, you can use it to see a map or take a picture… As far as I am concerned, if I run a bicycle on a small country road, the goal is to escape my daily computer view, and to look at the landscape, not to another screen.
My thought is that Google Glass is typically a product developed by a company because it’s cool, not to fulfill a need or solve a problem. Moreover, using the product in your day to day life will rather generate problems: from eye sickness to preventing you to walk in a street!

Nevertheless, Google has appointed Nest CEO (and iPod designer) as Google Glass “big boss” or decision maker, but not asked him to run the team on a day to day basis. Maybe that Google Glass will be the next Tablet, in 15 years from now?

My 2 cents: IoT and wearable could be a decent source of SC growth, but betting huge amount of money, because you can do it like Google and because the product looks cool for a bunch of nerds will not be enough to succeed. I think that certain marketing peoples have been spoiled by the incredible success of the wireless phone (and now smartphone and tablet) and think there will be another “magic” product anytime soon. The next product passing from a couple of hundred million unit sold per year to several BILLION in less than 15 years may not come before another 15 or 20 or even 25 years!

From Eric Esteve from IPNEST

January 16, 2015

ASE and Brewer Science Win SEMI Award

ASE and Brewer Science Win SEMI Award
by Paul McLellan on 01-16-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

Tuesday night was the SEMI awards banquet at ISS in Half Moon Bay. The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

Brewer Science and Advanced Semiconductor Engineering, Inc. (ASE), are recipients of the 2014 SEMI Award for North America. The awards honor Terry Brewer of Brewer Science for revolutionizing optical lithography with anti-reflective coatings; and Jason Chang and Tien Wu of ASE for relentlessly pursuing the commercialization of copper wire bonds when gold was the industry standard. The honorees accepted their awards during the banquet.

Some innovations become such an integral part of the semiconductor manufacturing industry’s infrastructure that the technology itself becomes fundamental — such as the use of anti-reflective coatings in optical lithography and copper for wire bonding.

Currently, multi-layer systems are commonly used in optical lithography, with some processes using 5-6 layers, as well as double- or triple-patterning steps, to achieve the necessary resolution. However, in the early 1980s, 1µm was considered the limit for optical lithography and single-layer photoresist suffered from reflections that caused significant variations in critical dimensions. Dr. Terry Brewer invented an anti-reflective coating that was effective in eliminating reflective interference and provided good adhesion to multiple materials and resist. At the time, the introduction of an anti-reflective coating was a radically different approach — adding layers to the single-layer exposure films of lithography. Brewer Science, Inc., founded in 1981, developed and commercialized anti-reflective coating materials that were instrumental in the industry’s progress from g-line to 248nm to 193nm lithography, and now to extreme ultraviolet (EUV) and directed self-assembly (DSA) technology.

Due the expense of gold for wire bonding, the semiconductor industry began exploring alternatives in the 1980s. Yet manufacturers did not adopt copper wire bonds due to concerns about yield, reliability, throughput, and customer acceptance. In 2006, Jason Chang and Tien Wu of ASE committed to underwrite risk, resolve technical problems, and address customer concerns. Requiring an investment reaching hundreds of millions of dollars with no assurance of success, in 2007 they started working with materials and equipment vendors to establish a supply chain and also with foundries to establish metallurgy for bonding pads compatible with copper wire bonds.

In 2009, Chang and Wu had dramatic results with a few selected customers. By 2013, more than half of ASE production was in copper wire bonds and today it exceeds 70 percent. ASE moved copper wire bonds into volume production and the industry benefits. Today, long-term reliability of copper wire bonds exceeds that of gold.

TSMC Finishes 2014 with the Chairman on the Call!

TSMC Finishes 2014 with the Chairman on the Call!
by Daniel Nenni on 01-15-2015 at 9:30 pm
Categories: Foundries, TSMC

I’m not a financial guy, as I have mentioned before, so let me just make some comments on the technology discussed on today’s conference call. Please note that the Chairman Dr. Morris Chang was on the call which is probably why the TSM stock went up more than 8% immediately after. Of course there was plenty of good news to go along with it but having Morris on the call definitely added market confidence, my opinion.

The biggest number I noticed was that advanced nodes made up 51% of revenues meaning 28nm and 20nm. TSMC predicted a quick 20nm ramp with Q4 2014 revenues at 20% of the total which quite a few people did not believe. Well, 20nm came in at 21% so congratulations to all who made that possible. TSMC stated quite clearly that they expect a similar ramp with 16nm this year and it is very hard to doubt that. 20nm is expected to contribute 20% of the total revenue for 2015 so it may be a much longer node than expected.

TSMC is raising CAPEX again to about $12B which is a 25% increase. 80% of it is for advanced nodes (28nm, 20nm, 16nm, and 10nm). Intel on the other hand is reducing CAPEX from about $11B to $10B putting them third behind Samsung and TSMC. Morris reiterated that TSMC builds fabs based on customer orders unlike others who build fabs on speculation only to find them empty. Just a guess here but that is probably a reference to Intel and the empty Fab 42.

TSMC finished the year with a 27.8% revenue growth compared to 18% in 2013. Lets call that the “Apple Factor”. Last year Morris predicted 5% growth for the semiconductor industry 10% growth for the foundry industry and said TSMC would outperform them both. Indeed. This year Mark Lui predicts that the semiconductor industry will grow 5% and foundry revenue will grow 12% with TSMC outperforming them again.

In regards to 10nm, qualification is still scheduled for Q4 2015 with production silicon in 2017. My guess is that 10nm will be here in time for the iPhone refresh in the fall of 2017, absolutely. 10nm is going to be an interesting node but more on that later.

28nm continues to grow due to mid to low end 4G smartphones. You can probably thank Xiaomi for that since they use 28nm Snapdragons. QCOM is an investor in Xaiomi so that will probably not change anytime soon. TSMC continues to optimize their 28nm offerings and feels that they will be able to defend their dominant position with which I agree. C.C. Wei also siad in her prepared statement that 16nm production started in Q3 2014 with meaningful revenue scheduled for Q1 2015. My guess was first 16nm revenue will be reported in Q2 2015 and based on the Q&A session I will stick with that.

I had to see the Q&A session in print before I commented because it was probably one of the more confusing ones I have heard/read. I don’t know who transcribes these for Seeking Alpha but they could do a better job for sure. And the analysts need to do a much better job preparing. Take a look at the transcript and let me know what you think in the comments section. The question about the server market was interesting but here is my favorite exchange:

Roland Shu – Citibank
Yes I think maybe I should rephrase my question —

Morris Chang– Chairman
Why do you have to rephrase your question all the time?

January 15, 2015June 14, 2019

Verification of Wireless RFIC Designs

Verification of Wireless RFIC Designs
by Daniel Payne on 01-15-2015 at 1:30 pm
Categories: Cadence, EDA

Wireless technology is all around as I use cellular on an Android phone, WiFi to connect my MacBook Pro to the internet, Bluetooth for a headset, ANT+ for my cycling computer, and NFC to speed up electronic payments on the Android phone. Here’s a big picture look at some of the modern wireless standards available to choose from:

On the design side you choose which standard to implement, create block diagrams, add models to each block, then start the verification process to see if you’ve implemented the standard correctly. Co-simulation is one approach used in RFIC verification where an envelope simulator is connected to a wireless system simulator:

For verifying the IEEE 802.11 standard (WiFi) you would need to understand the documentation, then extract the needed frequency values:

Fundamental frequency
Step period
Frequency of resolution

Next up is manually configuring and controlling the simulation. On the wireless simulator you would generate an input, simulate one period of the carrier, go to a later time and then repeat the process. To evaluate a period the simulator could use the transistor-level (standard envelope) and run harmonic balance analysis at each time interval, although that is limited to just small RF modules and not for an entire RFIC.

Another approach is to characterize the circuit before the first period, write a behavioral model and then simulate the behavioral model through each time interval. Benefits of this behavioral model approach is a much faster simulation speed which then enables the entire RFIC to be simulated. Engineers at Cadence propose improving RFIC verification by following three steps:

[LIST=1]

An accurate characterization and modeling of the RF design

Use wireless standard-compliant modulation sources

Apply automation for system-level performance: Error Vector Magnitude (EVM), spectrum, Adjacent Channel Power Ratio (ACPR) and Bit Error Rate (BER) measurements

This methodology uses one design environment along with a single kernel simulation engine, shown below:

Designers would characterize each circuit using large signal analysis (harmonic balance). Next, a behavioral model is built. Now the time evaluations are started. The behavioral model is run to evaluate the circuit for each time interval, which produces quicker results than running a complete harmonic balance analysis for each interval.

Cadence EDA Tools

The design capture tool for Cadence is called Virtuoso Analog Design Environment, and the simulator is Spectre RF. You can use standards-based stimulus, saving verification time: IEEE 802.11 family, LTE, LTE-A, ZigBee and 802.15.4g. Modulated sources are found as components in a library, and they are used as input to the Design Under Test (DUT), making your simulation setup time a lot quicker.

In the GUI you select the wireless modulated source from a library, then the simulation engine automatically fills in the parameters: sampling rates, stop times, strobe options and carrier frequencies to comply with the standards.

In Spectre RF the fast envelope simulation engine can characterize and then create a model of the DUT, giving you up to 1,000X faster simulation results compared to a transistor-level envelope simulation approach. RFIC architects and designers can see plots with constellation and ACPR, the critical measures of distortion:

Summary

RFIC designers and architects have choices when it comes to their design and verification methodology. The approach offered from Cadence has useful automation to reduce verification times in a single-vendor flow. View the complete 6 page white paper here for more details.

January 15, 2015

eSilicon Try IP Before You Buy

eSilicon Try IP Before You Buy
by Paul McLellan on 01-15-2015 at 10:00 am
Categories: eSilicon, Semiconductor Services

I’ve written before about eSilicon’s IP Marketplace. This is the latest in several steps to automate more and more of the interface between eSilicon and its customers: MPW quotes, production quotes, tracking orders through manufacturing, and now IP quotes. There is a phrase in software development called “eating your own dogfood” meaning making yourself use the software and techniques that you develop. That way you find problems and fix them really fast. As an industry, semiconductor enables the entire internet and all the various businesses on it but we have not been very good at eating our own dogfood and using the e-commerce techniques that we enable others to use. eSilicon is on the cutting edge for this today.