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CDN is Live in Silicon Valley!

CDN is Live in Silicon Valley!
by Daniel Nenni on 03-03-2015 at 10:00 pm
Categories: Cadence, EDA

As big of a fan as I am of Social Media there is still nothing like getting up close and personal when collaborating with the fabless semiconductor ecosystem. After 30+ years in Silicon Valley if there is one thing I have learned it’s that “showing up” is the #1 key to success, absolutely.

Speaking of showing up, each year there are three big user group meetings here in Silicon Valley. The first one is CDNLive(Cadence, March 10-11), then SNUG(Synopsys, March 23-24), and User2User (Mentor, April 21st). Thousands of people will attend, executives will keynote, fellow users will present, marketeers will dance, and of course there will be a free lunch and parting gifts. Not a bad way to spend a day. The best part of course is meeting fellow semiconductor professionals and networking. Remember, it’s not so much what you know but who you know in this ultra-fast-paced world changing industry. Where would we be without this level of collaboration? Still using flip phones…

The best parts for me are the customer presentations which is the meat of any conference. For CDNLive it is: Cisco, TI, FreeScale, Broadcom, AMD, PMC-Sierra, Broadcom, Oracle, ARM, Xilinx, Samsung, SanDisk, Altera, and a whole host of others. Several of the SemiWiki bloggers will be there blogging live and you can even use the promo code “SemiWiki” for $50 off, such a deal.

What’s Happening at CDNLive Silicon Valley 2015

Each year, CDNLive Silicon Valley brings together a record number of Cadence® technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for designing advanced silicon, SoCs, and systems.

Papers: Choose from a wide variety of user-authored papers addressing all aspects of design and IP creation, integration, and verification. Discover how others are using Cadence technologies and techniques to realize silicon, SoCs, and systems—efficiently and profitably.

Techtorials: Participate in a variety of interactive techtorials to get a more in-depth look at specific Cadence products, new solutions, and feature enhancements.

Keynote speakers: Hear from industry leaders who influence the global electronics marketplace. They will discuss industry trends in silicon, SoC, and system realization and share their thoughts on the most pressing design challenges.

Designer Expo:Learn more about the collaborative ecosystem available to support you. Cadence and our partners will showcase the latest results of our joint efforts. Explore new products and services from our many exhibitors.

Networking opportunities:Engage in stimulating technology discussions with your peers and stay connected after the conference.

Join us at CDNLive Silicon Valley 2015!
March 10-11, 2015
Santa Clara Convention Center

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Where a New IP Company Could Invest

Where a New IP Company Could Invest
by barun on 03-03-2015 at 7:00 pm
Categories: IP

Which IP which will give substantial return in next 3 – 5 years and where a company will invest as well as how it will differentiate itself from others, particularly the big ones, are key discussion topics for any start-up entering into semiconductor IP business.

In the last few decades we have seen a tremendous growth of interface IPs due to the standardization of chip-to-chip or system-to-system communication process. Lot of IP companies have heavily invested in developing interface IPs and get benefit of those investments by providing license of those IPs to several SoC companies.

But the market is slowly getting saturated and entry barrier is increasing to the new start-ups. One of the reason is not many new protocols are coming out. In most of the cases either it is upgrading of existing protocol (like PCI-E, USB etc) or fusion of two existing protocols (like M-PCIE). An existing IP vendor will always incur much less investment to upgrade their IP than a company who is completely new in that domain. Also customers, particularly, who has licensed the IP of old version will most likely go with the existing vendor for IP based on recent versions. Moreover these IPs are very much standardized in nature, needs less customization and hence a big company, with much larger sales network, can get more benefit by investing in those IPs. That is why we have seen two big IP vendors Synopsys and Cadence are focused on interface IP segments and have even acquired small IP companies in those domains.

The question will then come where a new IP company can invest. The old traditional IPs like data converter, power management, clocking circuit modules with a focus on application areas like automotive, medical, industrial can be potential areas for new IP companies. Let us look why

  • Automotive, medical and industrial SoCs have seen 7% to 9% growth which is way above than semiconductor average growth (some reports have even predicted 10%+ growth in automotive IC area). Also these segments commands more than 40% market share in analog IC market
  • All of these sectors have significant usage of analog IPs. As per several reports analog IC constitutes more than 40% share of total semiconductor devices sold in those segment
  • The IPs in data converter, power management etc areas need significant customization in every SoC depending on applications environment likes power, environmental noise, operative voltage etc. A start-up can take those customization requirements more effectively than the big guys. If we look none of the big IP companies actually have significant offerings in these areas
  • In significant cases customers request complete SoC design with some embedded software development with these IPs. The reason is in good amount of cases the IPs with some peripheral logic form a SoC itself. As a result a start-up, with more adoption capability, can provide a solution comprising of both IP (product) and services
  • Also OEMs, sometimes, directly becomes customers for these kind of project and in those situation even post GDSII manufacturing is involved

But there are significant challenges also to develop and market IPs targeted for specific application segments

  • The most important is it needs significant amount of domain specific knowledge like application environment, certification/ compliances etc
  • Typically the areas like automotive, medical, industrial have more stringent requirement in terms of certification, qualification and hence the chance of success of IP in the first tape-out becomes low. Hence the time of get benefit of the investment also becomes longer
  • The processes used in these areas are not always normal CMOS process. Bipolar, BiCMOS, HV-CMOS processes etc are used significantly in these areas. Hence besides design knowledge the process knowledge also becomes a critical to develop the right IP in these areas
  • The SoC used in automotive, medical, industrial application has 10+ years of lifetime and hence customers expect longtime support from IP vendor. They may be reluctant to rely on a start-up for this

Regards,
Barun Kumar De

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Exensio: Big Data in the Fab

Exensio: Big Data in the Fab
by Paul McLellan on 03-03-2015 at 7:00 am
Categories: EDA, Semiconductor Services

For 20 years PDF Solutions have been working with fabs on yield enhancement. Today, they announced their Exensio Platform for big data manufacturing environments. They haven’t really been keeping it a secret and have been talking about it at events since late last year, but it has basically been in stealth mode for the last 3 years. The primary focus of Exensio is to help fabs ramp to production volumes and then keep yield up once they are there.

There are 700-800 steps in a typical production process today. However, inspection is only done every 40 or 50 processing steps. This makes it hard to identify exactly what a problem is caused by. What is really wanted is to catch the problem when it happens and identify the tool (or material) causing the issue, a huge Fault Detection and Classification (FDC) system. But there are tens of millions of datapoints per second and so to do this would require hooking up every tool in the fab to a huge central database, capturing data within milliseconds so as to be able to catch even small excursions, uploading terabytes of data every day, and analyzing it all in real-time. Ideally the system would be able to react before the wafer was even finished processing.

And that is just what Exensio does. For example, every 300mm tool at TSMC is hooked up to Extensio. They started with beta customers such as Sony four years ago in 2011.


I talked last week to John Kibarian, CEO of PDF, about the Exensio announcement. He said that a lot of this is being driven by the explosive growth in data availability across the manufacturing flow (not just in the fab but in packaging, assembly and test too). There are more types of data collected, including data that has not really been used before. Larger factories and larger wafers generate more data. Plus there is a need for fast decisions so that corrective action can be taken immediately, as well as the slower analysis of longer term trends such as the day of the week, the specific operator, the specific tool and so on.

Most customers can and do conduct some of this analysis themselves. But typically this takes days or weeks to complete as opposed to minutes or hours. At some level, it is all about driving variability reduction which is the key to ramping a process to high volume manufacturing (HVM) and gradually driving yields even higher once that is achieved. With yield now sometimes driven by single layer atomic variation, the analysis can be very complex.


Exensio is built on top of the Cassandra database for scalability (as, by the way, is Facebook who have perhaps the biggest scalability problem of anybody). One top of this are:

  • Exensio-yield (dataPOWER)
  • Exensio-control (maestra)
  • Exensio Yield Analysis Services


PDF solutions have more process yield ramps to HVM than any other company, with over 60 below 90nm. They are the established leader with connections to all the major foundries such as TSMC, GF, ST, On, TowerJazz and more, along with relationships with the major fabless companies such as Qualcomm, NXP, Silicon Image, CSR and many more who work closely with their foundries as “virtual IDMs”. Exensio is the next step in the evolution of PDF, successfully leveraging big data architecture and technology. 80% of their business is leading edge with 28/22/20nm now just a niche and most work going on at 16/14/10nm.

PDF Solutions website is here.

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All things being unequal for NXP and Freescale

All things being unequal for NXP and Freescale
by Don Dingee on 03-02-2015 at 4:00 pm
Categories: General

When I read the news that NXP was buying Freescale, it felt like a part of me – and a big part of the history of high tech industry in Arizona – died. There was a time not that long ago where Motorola was the biggest employer in this state, way before Freescale and ON Semi separated from the mothership. Somehow, even with moving headquarters to Austin and downsizing and changes in leadership, Freescale still felt like an old friend who lived just down the street. Continue reading “All things being unequal for NXP and Freescale”

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Simple Analog ASIC Solves Thermal Analysis Problems

Simple Analog ASIC Solves Thermal Analysis Problems
by admin on 03-02-2015 at 1:00 pm
Categories: EDA

In a world where Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) are dominating every conceivable application, greater attention is being applied to their long term reliability. These chips are being built on smaller lithographies, running at higher speeds, dissipating more power and to make things worse, they are being encapsulated in ever decreasing package sizes.

Higher device performance comes at a price; higher temperatures. And with higher temperatures comes lower reliability if thermal considerations aren’t carefully controlled. Semiconductor manufacturers have long been aware of the problems associated with heat. Most have application notes and white papers plastered across their web sites espousing the benefits of careful calculation of power management using their values of [SUB]JA[/SUB] and [SUB]JC[/SUB] (Junction-to-Ambient and Junction-to-Case thermal resistance, respectively) often with sidebars suggesting various heat sinks to use in marginal situations. This puts the burden of solving temperature related problems on the backs of the user.

Recent technology advances and the proliferation of the use of Thermal Test Chips (TTCs) like those developed by JVD, Inc. for Thermal Engineering Associates of Santa Clara, CA is allowing semiconductor manufacturers and companies designing their own ASIC/ASSP devices to get ahead of the curve by thermally engineering their silicon before going to production. These TTCs allow system designers to fully model, measure and modify their designs before committing to costly silicon. They are special Analog ASIC that are used to model and measure the thermal performance of your chip design in situ before you commit those tooling dollars for masks and wafers. , the use of these Analog ASIC Thermal Test Chips play an important role in allowing semiconductor manufacturers and companies designing their own ASIC/ASSP devices to get ahead of the curve by thermally engineering their silicon before going to production.

Modeling allows you to create multiple individual heat sources on the TTC die, identical to the heat sources that will occur on your final IC. Temperature sensors, strategically located throughout the TTC give you precise measurement of the temperature of the die at multiple locations simultaneously. The heat sources can be modulated to replicate various portions of your IC being power on, off or in an intermediate mode. By tracking the absolute or changes in temperature at any point on the TTC, you can determine if one or more heat sources combine to exceed safe operating temperatures of the intended IC design. If temperatures are problematic, you can go back to your IC design and modify the chip?s layout to isolate the heat sources and alleviate the potential problem.

FULL WHITE PAPER HERE

Bob Frostholm – JVD, Inc.

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DAC: March Update

DAC: March Update
by Paul McLellan on 03-02-2015 at 7:00 am
Categories: EDA, IP

DAC is coming up. It is already March. If you are in the EDA industry then it is basically three months away, which sounds a lot until you actually have to get everything pulled together so that your booth is ready to go on Monday June 7[SUP]th[/SUP]. Exhibit hours have been extended and now run from 10am to 7pm (only until 6pm on Wednesday). To ensure attendance that late in the day, the executive committee will be walking around the halls with rawhide whips…no wait, the evening receptions at the end of the first couple of days will be moved to the show floor. The poster sessions will also be moved to the show floor to give them more visibility. So you can read the posters while you sip a DACquiri.

Usually at DAC there turns out to be a theme, not something official but a sort of collective wisdom of the industry. My prediction for 2015 is that this is going to be the year of 10nm. Of course 10nm is not ready but the tools need to be ahead of the curve: no point in having a process ready to go and nothing to run in it. That is the semiconductor equivalent of “all revved up with no place to go.” That means that if you don’t have 10nm tools close to being shippable to early adopters and teaching customers then you are probably going to be late to market. Test chips are being designed now. IP will be needed before anyone other than the biggest, most leading edge, companies can tape out designs.

New this year is DACtv. It will be showing videos for both exhibitors and attendees. You can find it here. If you are an exhibitor and have a YouTube channel then you can be listed as an associated channel. Send a link to pr@dac.com. Videos already up on the site are Rich Nass on embedded, Daniel Bourke on the designer track, “Mac” McNamara on IP, and an interview with General Chair Anne Cirkel. Anne has also been blogging once a week here.

There is no free Monday for the exhibits, just like the last 4 years. But there will be free access through the I love DAC scheme, as there has been for those 4 years. Details nearer to the time. And if you miss the cut for I love DAC you will still be able get in for free. Email Anne Cirkel with the titles of her last three blogs and she’ll give you a free exhibit badge. I think you can thank SemiWiki blogger Daniel Payne for that last offer.

A few upcoming deadlines:

  • Submissions for the Marie Pistilli Women in EDA award are due by March 6[SUP]th[/SUP]
  • Submissions for the Richard Newton Young Student Fellow Program are due March 26[SUP]th[/SUP]
  • Submissions for the P.O. Pistilli Undergraduate Scholarship are due March 6[SUP]th[/SUP]
  • Work in Progress submissions are due March 2[SUP]nd[/SUP]. That would be today!

The DAC website, as always, is here.

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3D-IC: Embedded Passives

3D-IC: Embedded Passives
by Arabinda Das on 03-02-2015 at 1:00 am
Categories: EDA, Foundries

IEDM 2014 was held in the second week of December 2014 in San Francisco. The excitement is over now and the dust has settled. Last week, at my leisure, I was glancing through the conference proceedings and short course material from IEDM 2014, when a slide from the 3DIC short course caught my attention. The slide presented below gives an overview of different interposer substrates used in the industry.


One of the things that I remembered during this short course was the discussion about how the industry has changed its outlook on interposers. In the initial phase, it was conceived to facilitate devices with a very large number of I/O counts and thus the interposer was an extension of the packaging platform. But now it is being considered as a real estate saver, where passive devices can be embedded to reduce the overall footprint. Passive devices such as capacitors, resistors, and inductors can occupy more than 50% of the precious die area and thus if they can be removed from the processor die, it would lead to more efficient integration. This slide made me think about integrated passive devices (IPD) in an interposer and their cost evaluation. I was curious to know if any device manufacturers have got their hands dirty on this topic.

To my surprise, there was one paper from TSMC in IEDM 2014, in which they described a MIM capacitor on a Si-interposer, using Cu-Damascene process. The Si-interposer had the possibility of connecting to external devices both on the top and the bottom side. On the top portion of the topmost metal layer, a re-distribution layer is connected to a μ-bump to facilitate connection to a processor die; while at the bottom part of the substrate, a TSV is connected to a C4 bump pad to attach to the packaging substrate. I believe, at present, this is the most cutting edge story of passives in a Si-interposer.

I also searched for embedded passives on glass substrates. Glass substrates have attracted a lot of attention, especially for high frequency applications because glass has low loss properties over a wide range of operating frequencies and temperatures. Some of the main players are Georgia-Institute Technology, IMEC, ST-Micro, Frauenhofer Institute, Schott AG, Asahi Glass and Dow Corning. All these companies have very strong R&D activities in glass interposers and all of them have fabricated passives on glass and have presented their findings in several conference proceedings. In most cases, an organic BCB layer is deposited on the glass substrates and passives have been made in the organic layer. Georgia-Institute’s web site also shows passive devices using through-glass-vias.

However, in my limited search, I could not find a commercial product with IPD on an interposer, and where the interposer is connected to a processor. If so, this would make truly a 2.5D integration scheme. The same question applies also to glass substrates. Glass interposers are probably lagging behind silicon interposers as glass has some inherent manufacturing challenges compared to Si. For example, in Si substrates, all the know-how of semiconductor industry can be applied. Fine dimensions can be patterned using advanced lithography techniques, a high density of TSVs can be made on the substrate, and the carrier wafer can be easily thinned down to below 50 μm. On the other hand, glass is difficult to work with and thinning the glass substrate is quite challenging. Nevertheless, glass has its positive attributes; it can be made into panels of 900 mm x 900 mm and these large panels can generate a very high number of glass interposer substrates, almost an order of magnitude higher than Si-interposers can be diced out from a 300 mm Si-wafer, thus reducing the overall price of the glass substrates. And the low lossy behavior of glass is suitable for high frequency applications; especially for passives like inductors. Both materials have their advantages and disadvantages.

Based on research and conference proceedings, it is clear that the industry is going to use embedded passives in the interposers for miniaturization and increase of functionality. It is probably delayed because of yield, test & quality standards, and reliability issues. The processor is a product of high quality standards but if it were connected to an interposer with a passive device in it, then there would be some additional reliability concerns; especially at the connection of the processor and the interposer. The fact that rework of embedded components is not possible, it is crucial that embedded passives have a high yield. But knowing the advantages of embedded passives for system in package (SIP), the industry would soon determine the most cost effective process for 2.5D integration. There is a tremendous R&D activity by major device manufactures, research consortiums and OSAT players on interposers; so most likely, we do not have to wait long before commercial products with IPD in interposers are the mainstream and the missing blanks on the slide presented during the short course of IEDM 2014 would be completed and fully understood.

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STMicro to Showcase Turnkey NFC Design at MWC

STMicro to Showcase Turnkey NFC Design at MWC
by Majeed Ahmad on 03-01-2015 at 10:00 pm
Categories: EDA, IoT, Mobile, STMicroelectronics

Near-field communication (NFC) technology is finally realizing its potential, thanks to the impetus provided by Apple Pay, and it’s becoming evident from the pre-Mobile World Congress (MWC) buzz coming from several makers of chips, smartphones and wearable devices.

Among the companies displaying NFC products at the 2015 MWC in Barcelona is STMicroelectronics, a leading supplier of Secure Element, a special storage block typically built into an NFC controller chip that safeguards vital information like bank account numbers. The other key building block of the contactless access solution is NFC radio for which STMicro is joining hands with ams AG to put together its analog front-end chip featuring NFC booster technology in the turnkey design.

The outcome of this collaboration is a turnkey NFC design solution, which comprises of ams’ boostedNFC chip combined with ST’s system-in-package (SiP), which in turn, contains controller and 32-bit secure microcontroller for Universal Integrated Circuit Card (UICC), embedded Secure Element and microSD-card applications. According to Laurent Degauque, Embedded Security Marketing Director at STMicroelectronics’ Secure MCU Division, the common reference design can be easily integrated into mobile phones, smart watches, wearables, and Internet of Things (IoT) devices.

ST claims that the turnkey NFC design supports all important NFC standards governing card emulation, including ISO14443 type A/B, FeliCa at data rates of up to 424 Kbps, active peer-to-peer bit rates of 212 Kbps and ISO18092 communication at up to 424 Kbps. Moreover, it boasts major certifications, including Common Criteria, EMVCo and GlobalPlatform as well as certifications from Visa, MasterCard, American Express and People’s Bank of China (PBOC).

ams, the Austria-based supplier of analog ICs and sensors, claims that its AS39230 RF chip boosts the signal on the antenna while increasing the signal strength by up to 10 times when compared with conventional passive load modulation (PLM) methods of transmitting a signal from an NFC tag, card or card emulator to an NFC reader. Moreover, ams promises help for space-constrained designs through reduction in the size of the antenna by as much as 20 times, down to 100mm[SUP]2[/SUP] or less, while maintaining the same signal strength.


Block diagram of ams’ RF front-end for NFC

ST’s part in the turnkey solution—rolled into an SiP device—is made up of the ST21NFCC controller and the ST33G1M2 Secure Element. ST’s Secure Element is based on the ARM SecurCore SC300 32-bit RISC core and it comes with Common Criteria-certified security features and a large and flexible embedded eFLASH. It boasts Trusted Service Management (TSM) infrastructure compatibility and supports banking and digital access applications through compliance with Global Platform GP2.2 OS and the complete MIFARE portfolio, including MIFARE Classic and MIFARE DESFire.

ST will be exhibiting the new reference design in Hall 7, Stand 7B146 at the Mobile World Congress (MWC) in Barcelona being held on 2-5 March 2015.

2015: The Year of NFC

ST’s partnership with ams for creating an NFC system reference design underscores two crucial facts. First, ST seems to have acknowledged the critical importance of turnkey solutions after the failure of its ST-Ericsson joint venture in mobile baseband business. Chipmakers like MediaTek and Qualcomm provided complete design solutions to a horde of smartphone makers in China and won a very lucrative market.

Second, after going through a number of pain points, the NFC technology finally seems ready for a mass adoption. There had been an industry joke about “The Year of NFC” that perpetually moved to the following year. But now 2015 actually looks like the year of NFC with a number of manufacturers of smartphones and wearable devices lining up to make product announcements at the MWC floor in Barcelona.

The NFC-centric mobile payment ecosystem—mired by security concerns, resistance from mobile operators and a complicated tap-to-pay retail market—had largely been limited to pilot projects. Then, there came Apple Pay, which not only played a significant role in the astounding success of the iPhone 6, but also reinvigorated the sleepy mobile commerce market.


(Image courtesy of Visa)

Apple came up with a simple and effective solution that left mobile operators out of the mobile payment and transaction system. The Cupertino, California–based consumer electronics firm incorporated a Secure Element inside the iPhone 6 so that the Apple Pay service could be provisioned over the air by the issuing bank or the credit card company. Mobile consumers using the Apple Pay app took a picture of the debit or credit card, and after a security check, Secure Element would allow the service to mobile users with the right credentials.

Don Tait, senior analyst at IHS, had told Reuters at the launch of the Apple Pay service back in September 2014 that ST’s strong presence in Secure Element chips would give it a plenty of scalability when NFC takes off. Apparently, NFC’s moment of glory has come, and for ST it’s about time to build a leading NFC position on top of its strong presence in Secure Element components.


STMicro’s ST33G1M2 Secure Element

There is a lot of talk in the technology press about NFC coming to new smartphone models such as Samsung Galaxy S6 and connected wearables like Apple Watch. That could lead to a much bigger market for the NFC silicon—1.64 billion sockets in 2018, according to market research firm IHS.

Majeed Ahmad is the author of Mobile Commerce 2.0: Where Payments, Location and Advertising Converge. The book outlines the major building blocks of the mobile commerce business while providing success and failure stories and profile of key industry players.

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IP for IoT: Thanks for the Memory

IP for IoT: Thanks for the Memory
by Paul McLellan on 03-01-2015 at 4:57 pm
Categories: eSilicon, Semiconductor Services

The Internet of Things (IoT) is clearly the buzzword of the moment, and like many catchy phrases it also tends to mean what you want it to mean, rolling up some things that exist like the automotive market or industrial automation, along with markets for things like wearables and healthcare that are largely in the future. But however you look at it, it is clear that a lot of devices are going to be connected to the internet and so it is big opportunity even if the estimates of its market size are all over the place.

eSilicon have been looking at the success factors for IoT. They discovered that all markets can be broken down as:

  • Consumer

    • lifestyle, home, mobility (automotive), healthcare
  • Industrial

    • manufacturing, logistics, retail, services
  • Government

    • buildings, city, infrastructure, services
  • Infrastructure

    • communications, security

The (semiconductor) market leaders right now are automotive, communications, industrial and home-automation. These are segments where products are being designed and shipped now rather than just appearing as a colored bar on somebody’s 2020 powerpoint slide.

eSilicon’s approach to the IoT market is two-fold. Firstly, to automate as much as possible of the process of choosing a semiconductor process and supplier, getting quotes, getting prototypes, ramping to volume. Gartner reckon that over 50% of IoT solutions will be provided by startups less than 3 years old. Startups do not have whole departments dedicated to getting quotes or managing production operations and so reducing the friction is very important.

The second area of importance is IP. There are a number of factors that are important for IoT depending on the application, but one that is pretty much universal is power. Many IoT devices are battery powered. At the very least the battery can only be recharged or changed occasionally and, in some cases, never: the battery the product ships with has to last the lifetime of the product.


Standard power reduction techniques such as clock gating and power down will continue to be important. eSilicon have a lot of experience given the wide range of chips they build for a broad spectrum of customers. Almost any feature you can think of they already have in production or at least have seen silicon. See the table above.

Most IoT devices seem to contain a lot of memory and as a result the most important area of IP are ultra-low-power memories. For example the SoC analyzed below has 96% of the chip is memory.

eSilicon has done lots of designs incorporating 3rd party IP. They don’t design their own microprocessors, for example. But one area that eSilicon does invest in, is building differentiated memory IP. And in the context of IoT, ‘differentiated’ means ultra power (ULP), both during operation, and, especially during the long periods of time when the chip is idle, waiting for something interesting to happen. They have ULP memories available in many processes, which is important since IoT SoCs are largely not going to be designed on the most bleeding edge processes due to cost, difficulty of incorporating analog and RF, and possible sensor integration.

For many applications such as automotive the characterization of the SoCs and so also the IP contained within, is over an extended range. Your car has to work in both a Minnesota winter and an Arizona summer, and not just when the chip ships but also 20 years later. So it is not good enough to build memories that look good in typical operating conditions, they have to cover the extremes too. For example, eSilicon have delivered memory IP that is qualified up to 175°C operation.

In networking applications, the normal sorts of memories used in other applications are not enough. For packet matching they also need ternary content addressable memories (TCAMs). These allow loading and matching through “don’t care” masks. eSilicon is the largest supplier of TCAMs in the market, having delivered solutions over many years from 180nm down to 14nm and all stations in between.

On March 11th fromm 9am to 9.30am pacific, eSilicon are presenting a webinar Winning the IoT Race with the Right Chip: Customizing Memory IP for IoT Applications. It will presumably also be available for replay later like all other eSilicon webinars (which you can find here). More details on the webinar, including a link for registration, are here.

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Xilinx’s 16nm UltraScale+ FPGA is Revolutionary

Xilinx’s 16nm UltraScale+ FPGA is Revolutionary
by Luke Miller on 03-01-2015 at 7:00 am
Categories: FinFET, FPGA, Xilinx

Well a very belated Happy New Year dear reader. I must admit, it has been a very long winter and it has caused the Miller’s to rethink this vital question. “What in the world are we doing living in NY”. So we are moving, and hopefully this is my last ‘real’ winter as we headed down south. To perhaps alleviate some of the winter blues from you a bit I see Xilinx has released their16nm UltraScale+ Product Tables. You can read them here.

While much of the news and attention is on the MPSoC and the VU13P that has like near ~12,000 DSP, 128 30g SERDES, ~500Mb RAM and the kitchen sink. I really could put a complete RADAR on that chip, Amazing! Just study this figure for a few minutes.

Being a Xilinx employee I can personally attest that these parts were intelligently designed, no evolution here. There was many, many hours of hard work across all disciplines to create these FPGAs. I personally like working for Xilinx for that reason, you can participate in the product of hard team work. Then to see the FPGAs working in real systems, at the least is very satisfying. Almost like watching a mom giving birth. (Believe that do you?) Miller #8 is expected end of March Lord Willing. I shall name him “Zynq MPSoC Miller”.

Over the last few months, I heckled Xilinx via email, nicely of course, “hey can I leak just a little bit about the 16nm FPGAs?” I mean they were great written emails, proof read by the wife. I eagerly awaited my response which was ‘No’. I understood, but boy the suspense was killing me but after some patience testing, this was the week. My kids were as excited as Christmas Day. Xilinx revealed what was in store at 16nm. By me not being ‘leaky’ prevented any type of miscommunication.

Speaking of miscommunication, this is a REAL conversation I had with the wife, really. Can any of you readers of the male persuasion relate here?

  • Luke: “I’m going out, do you need me to pick up anything.” (Safe question, and necessary, 50 points)
  • Wife: “Well, we are out of hamburger, so do not get that.”
  • Luke: “huh” …(With a very complicated look on my face)

Now in ‘marriage conversation’, I believe the Lorenz dilation does in fact take place and hours go by when talking with the wife on such subjects. Men speak blue, Women pink. Please translate accordingly. Can any of you guess what she really meant?

Back to Xilinx but I needed to get that off my chest.

At 16nm remember this phrase “Tools, Tools, Tools”. I must admit you simply cannot just pick up one of these devices and start coding blindly. It is now about Tools and Architecture. The MPSoC, has ARMs, Legs, R5’s, GPU, H.264/265 , Power Management and Programmable Logic. I believe it is the time to embrace across team disciplines (systems, software, and hardware) and High Level Synthesis. You cannot simply be competitive and program these puppies by hand. C/C++, OpenCL are the key to stay portable and to keep from wheel spinning. Xilinx Vivado HLS will give you better QoR (Smaller, Faster, Denser designs).


What does 12,000 DSP and 128, 30g SERDES give you. About 20 TMACs of processing power and a plethora of options to all the revolutionary serial standards like JESD204b (c is chartering out) and Hybrid Memory Cube. Friend DDR has died, and I believe we are about to witness the death of wide LVDS ADC/DAC devices soon when lower latency is achieved in the JESD204 devices. This is why you need 128 GTs. Five years ago you probably did not. A 32 channel RADAR receiver is cake in such a part. 30g is all important. The next gen HMC, and JESD204 will need that rate, 28g will not cut it. What should you do next? Read ALL the materials which Xilinx has posted. Contact you sales rep and get more info. Get a 16nm evaluation board when available. You simply cannot beat having a fully working framework ready to go. Get HLS training, Start C/C++, OpenCL coding. Get Vivado training and for goodness sake stay warm and safe the rest of this winter!