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Intel Q4 and 2014 Results

Intel Q4 and 2014 Results
by Paul McLellan on 01-16-2015 at 5:03 pm
Categories: Foundries, Intel Foundry

Intel announced their results yesterday for last quarter (and the year). And they were good financially. As Brian Krzanich said:The fourth quarter marked a strong finish to a great year. We began 2014 expecting roughly flat year-over-year revenue and operating income. Instead the company’s full year revenue grew 6% touching all time record of $55.9 billion. At the same time, operating income rose 25%.

We initially forecasted revenue growth [for the datacenter group] in the low to mid teens with operating profit growing faster than revenue. We exceeded those higher expectations and revenue is up 18%. The operating profit expanded by a remarkable 31%.

They beat Q4 guidance slightly and EPS by quite a lot and margins were up (all good). But Q1 guidance going forward was to lower expectations. In particular they forecast gross margins at around 60% compared to 65.3% this quarter. That is a big drop. Analysts hate this, but I think it is inevitable that as Intel starts to get traction in IoT, tablets and even mobile then margins have to go down from what you can get for top-of-the-line microprocessors for the datacenter business. Stacey, the CFO, said it was connected to 14nm ramp and margins should be up a little later in the year. So 14nm is still a bit behind on yield I’m guessing.

And they do seem to be doing something in IoT. As Brian said:Finally, you see us moving quickly to wearables, to our growing portfolio of collaborations with Google Glass, fashion and fitness brands like Fossil, Oakley, Opening Ceremony and SMS Audio along with our own products like the Basis Peak and the Curie Module, a computers the size of a button.


As always here at Semiwiki we are less interested in the financial stuff than the other color. After all we all know Intel is a powerhouse in servers and datacenters. How are they doing in mobile? How are the process ramps going? There was lots of information in the call and especially in the replies to the questions.

Firstly tablets. Intel planned on shipping 40 millions chips (along with around $50 per chip in negative revenue) to establish themselves in the market. They ended up shipping 46 million and established themselves as “one of the industries largest merchant silicon providers”. Although “merchant” is a bit of a stretch when you are losing money and making it up on volume. Going forward they expect to grow about as fast as the tablet market does, but since almost all forecasts are flat to down (iPad sales actually fell last quarter) that is not a high growth market. Of course if they can keep their market share now that they have 14nm product, and if 14nm is really a lot cheaper they can increase their profitability. It is not clear (and nobody asked) if they are still shipping negative revenue on their current chips, essentially buying market share.

Intel merged mobile with laptops into MCG (mobile and communications group). Mobile was losing $1B per quarter and will presumably continue to lose a lot of money since Brian said in the questions that:Stacy and I are committed to drive $800 million out of this business for ’15.

But in subsequent questions a lot of that was the expectations of cutting back on negative revenue. So best case is that they are only going to lose $800M per quarter.

Brian was asked about 10nm. He replied:We are timing on 10-nanometers. We are not going to come out with—we’ll be introducing a 10-nanometer to the marketplace in general, probably until the end of this year. So we will give, as we go through the year, probably by the investor meeting in November, we’ll give you an outlook on how and what timing is for 10-nanometers.

So that’s clear then!

Brian also talked about Broadwell versus similar products at the same stage of their life. His reply is again a bit opaqueI would take you back to the graph I showed at the investor meeting because I actually showed a non-normalized cost that showed Broadwell relative to other products at the same stage of manufacturing. And so what that chart shows is the churn up in the first half of this year. So the early stage of the Broadwell ramp because of some of the old issues that we’ve talked about, it is higher. On a non-normalized basis, it’s a higher cost. But by the time we get into the back half of the year on a non-normalized basis, Broadwell actually is less expensive than those other products at the same stage of their life.

I think that means that currently yields on 14nm are still not where they want them to be but by the end of 2015 they expect per transistor costs for 14nm to be below 22nm.

So how are they doing in mobile (not tablets, real mobile) where they have a product called SoFIA. Actually it is a series, the current one being SoFIA 3G (so basically already pretty obsolete), then a SoFIA LTE modem (I don’t know if this means that they will have their LTE modem on an Intel process, currently it is TSMC). Anyway, they have finished internal qualification, and now need to go to the carriers for their certification (what used to be called “type approval”). They don’t expect to ramp until the second half of the year. So it is going to be at least another year before we have a clue whether Intel is really in or out of mobile.

SeekingAlpha transcript of the call is here.


More articles by Paul McLellan…

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Google Glass is Dead, ARA Phone is Prototyped

Google Glass is Dead, ARA Phone is Prototyped
by Eric Esteve on 01-16-2015 at 1:00 pm
Categories: IoT, Mobile

These two products are linked because they have been invented by Google and both are disruptive technologies. Like was the Apple’s Newton tablet launched in CES Chicago in 1992 and finally stopped in 1998, due to the lack of success. To born again in 2010 as the well-known and best seller iPad in 2010, creating a new market segment (Tablet) generating 221 million units sales in 2013 (total market) and associated SC revenue estimated in the $12 to $15 billion. So when saying that Google Glass is dead, we must be cautious.

About Google ARA, I would just ask you a question: would you buy the pictured below product? Just a reminder: this is a phone…

In fact Google ARA is a “modular” phone, so you can add modules to a body from Google. The modules can be sold by any of the Google’s partners. Innovative capacitive interconnects and other new connectors have been defined to support the project. From a protocol standpoint, Google has wisely selected a proven Interface, UniPro specification and the associated MIPI M-PHY defined by the MIPI Alliance, and used for example to support Unified Flash Specification (UFS). Thus any module designer has to integrate MIPI UniPro/M-PHY to make sure that the product will smoothly interoperate with the body.

So far, so good (Except that the prototype demonstrated during Project Ara Developer Conference on the 14th of January stop working after a minute or so and could not boot anymore… but nobody’s perfect)

As far as I know from reading the press during 2014, Google has defined a rule specific to ARA: any module should have been tested and validated with any other existing module. I honestly don’t know if this rule is still valid, but in this case, such a rule would be a major drawback, as the number of required interoperability test that a new module would have to comply with would go up exponentially! Such a rule is what we could call a false good idea, working only on the paper, but not in the real world…

To come back with Google Glass, you can verify (above picture) that you can’t find it anymore on Google. I must say that I am not really surprised to see the product exiting the market! I remember some of the sales arguments for these glasses:

  • I you run a bicycle, you can use it to see a map or take a picture… As far as I am concerned, if I run a bicycle on a small country road, the goal is to escape my daily computer view, and to look at the landscape, not to another screen.
  • My thought is that Google Glass is typically a product developed by a company because it’s cool, not to fulfill a need or solve a problem. Moreover, using the product in your day to day life will rather generate problems: from eye sickness to preventing you to walk in a street!

Nevertheless, Google has appointed Nest CEO (and iPod designer) as Google Glass “big boss” or decision maker, but not asked him to run the team on a day to day basis. Maybe that Google Glass will be the next Tablet, in 15 years from now?

My 2 cents: IoT and wearable could be a decent source of SC growth, but betting huge amount of money, because you can do it like Google and because the product looks cool for a bunch of nerds will not be enough to succeed. I think that certain marketing peoples have been spoiled by the incredible success of the wireless phone (and now smartphone and tablet) and think there will be another “magic” product anytime soon. The next product passing from a couple of hundred million unit sold per year to several BILLION in less than 15 years may not come before another 15 or 20 or even 25 years!

From Eric Esteve from IPNEST

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ASE and Brewer Science Win SEMI Award

ASE and Brewer Science Win SEMI Award
by Paul McLellan on 01-16-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

Tuesday night was the SEMI awards banquet at ISS in Half Moon Bay. The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

Brewer Science and Advanced Semiconductor Engineering, Inc. (ASE), are recipients of the 2014 SEMI Award for North America. The awards honor Terry Brewer of Brewer Science for revolutionizing optical lithography with anti-reflective coatings; and Jason Chang and Tien Wu of ASE for relentlessly pursuing the commercialization of copper wire bonds when gold was the industry standard. The honorees accepted their awards during the banquet.

Some innovations become such an integral part of the semiconductor manufacturing industry’s infrastructure that the technology itself becomes fundamental — such as the use of anti-reflective coatings in optical lithography and copper for wire bonding.

Currently, multi-layer systems are commonly used in optical lithography, with some processes using 5-6 layers, as well as double- or triple-patterning steps, to achieve the necessary resolution. However, in the early 1980s, 1µm was considered the limit for optical lithography and single-layer photoresist suffered from reflections that caused significant variations in critical dimensions. Dr. Terry Brewer invented an anti-reflective coating that was effective in eliminating reflective interference and provided good adhesion to multiple materials and resist. At the time, the introduction of an anti-reflective coating was a radically different approach — adding layers to the single-layer exposure films of lithography. Brewer Science, Inc., founded in 1981, developed and commercialized anti-reflective coating materials that were instrumental in the industry’s progress from g-line to 248nm to 193nm lithography, and now to extreme ultraviolet (EUV) and directed self-assembly (DSA) technology.

Due the expense of gold for wire bonding, the semiconductor industry began exploring alternatives in the 1980s. Yet manufacturers did not adopt copper wire bonds due to concerns about yield, reliability, throughput, and customer acceptance. In 2006, Jason Chang and Tien Wu of ASE committed to underwrite risk, resolve technical problems, and address customer concerns. Requiring an investment reaching hundreds of millions of dollars with no assurance of success, in 2007 they started working with materials and equipment vendors to establish a supply chain and also with foundries to establish metallurgy for bonding pads compatible with copper wire bonds.

In 2009, Chang and Wu had dramatic results with a few selected customers. By 2013, more than half of ASE production was in copper wire bonds and today it exceeds 70 percent. ASE moved copper wire bonds into volume production and the industry benefits. Today, long-term reliability of copper wire bonds exceeds that of gold.


More articles by Paul McLellan…

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TSMC Finishes 2014 with the Chairman on the Call!

TSMC Finishes 2014 with the Chairman on the Call!
by Daniel Nenni on 01-15-2015 at 9:30 pm
Categories: Foundries, TSMC

I’m not a financial guy, as I have mentioned before, so let me just make some comments on the technology discussed on today’s conference call. Please note that the Chairman Dr. Morris Chang was on the call which is probably why the TSM stock went up more than 8% immediately after. Of course there was plenty of good news to go along with it but having Morris on the call definitely added market confidence, my opinion.

The biggest number I noticed was that advanced nodes made up 51% of revenues meaning 28nm and 20nm. TSMC predicted a quick 20nm ramp with Q4 2014 revenues at 20% of the total which quite a few people did not believe. Well, 20nm came in at 21% so congratulations to all who made that possible. TSMC stated quite clearly that they expect a similar ramp with 16nm this year and it is very hard to doubt that. 20nm is expected to contribute 20% of the total revenue for 2015 so it may be a much longer node than expected.

TSMC is raising CAPEX again to about $12B which is a 25% increase. 80% of it is for advanced nodes (28nm, 20nm, 16nm, and 10nm). Intel on the other hand is reducing CAPEX from about $11B to $10B putting them third behind Samsung and TSMC. Morris reiterated that TSMC builds fabs based on customer orders unlike others who build fabs on speculation only to find them empty. Just a guess here but that is probably a reference to Intel and the empty Fab 42.

TSMC finished the year with a 27.8% revenue growth compared to 18% in 2013. Lets call that the “Apple Factor”. Last year Morris predicted 5% growth for the semiconductor industry 10% growth for the foundry industry and said TSMC would outperform them both. Indeed. This year Mark Lui predicts that the semiconductor industry will grow 5% and foundry revenue will grow 12% with TSMC outperforming them again.

In regards to 10nm, qualification is still scheduled for Q4 2015 with production silicon in 2017. My guess is that 10nm will be here in time for the iPhone refresh in the fall of 2017, absolutely. 10nm is going to be an interesting node but more on that later.

28nm continues to grow due to mid to low end 4G smartphones. You can probably thank Xiaomi for that since they use 28nm Snapdragons. QCOM is an investor in Xaiomi so that will probably not change anytime soon. TSMC continues to optimize their 28nm offerings and feels that they will be able to defend their dominant position with which I agree. C.C. Wei also siad in her prepared statement that 16nm production started in Q3 2014 with meaningful revenue scheduled for Q1 2015. My guess was first 16nm revenue will be reported in Q2 2015 and based on the Q&A session I will stick with that.

I had to see the Q&A session in print before I commented because it was probably one of the more confusing ones I have heard/read. I don’t know who transcribes these for Seeking Alpha but they could do a better job for sure. And the analysts need to do a much better job preparing. Take a look at the transcript and let me know what you think in the comments section. The question about the server market was interesting but here is my favorite exchange:

Roland Shu – Citibank
Yes I think maybe I should rephrase my question —

Morris Chang– Chairman
Why do you have to rephrase your question all the time?

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Verification of Wireless RFIC Designs

Verification of Wireless RFIC Designs
by Daniel Payne on 01-15-2015 at 1:30 pm
Categories: Cadence, EDA

Wireless technology is all around as I use cellular on an Android phone, WiFi to connect my MacBook Pro to the internet, Bluetooth for a headset, ANT+ for my cycling computer, and NFC to speed up electronic payments on the Android phone. Here’s a big picture look at some of the modern wireless standards available to choose from:

On the design side you choose which standard to implement, create block diagrams, add models to each block, then start the verification process to see if you’ve implemented the standard correctly. Co-simulation is one approach used in RFIC verification where an envelope simulator is connected to a wireless system simulator:

For verifying the IEEE 802.11 standard (WiFi) you would need to understand the documentation, then extract the needed frequency values:

  • Fundamental frequency
  • Step period
  • Frequency of resolution

Next up is manually configuring and controlling the simulation. On the wireless simulator you would generate an input, simulate one period of the carrier, go to a later time and then repeat the process. To evaluate a period the simulator could use the transistor-level (standard envelope) and run harmonic balance analysis at each time interval, although that is limited to just small RF modules and not for an entire RFIC.

Another approach is to characterize the circuit before the first period, write a behavioral model and then simulate the behavioral model through each time interval. Benefits of this behavioral model approach is a much faster simulation speed which then enables the entire RFIC to be simulated. Engineers at Cadence propose improving RFIC verification by following three steps:

[LIST=1]

  • An accurate characterization and modeling of the RF design
  • Use wireless standard-compliant modulation sources
  • Apply automation for system-level performance: Error Vector Magnitude (EVM), spectrum, Adjacent Channel Power Ratio (ACPR) and Bit Error Rate (BER) measurements

    Related – Cadence Mixed Signal Technology Forum

    This methodology uses one design environment along with a single kernel simulation engine, shown below:

    Designers would characterize each circuit using large signal analysis (harmonic balance). Next, a behavioral model is built. Now the time evaluations are started. The behavioral model is run to evaluate the circuit for each time interval, which produces quicker results than running a complete harmonic balance analysis for each interval.

    Cadence EDA Tools

    The design capture tool for Cadence is called Virtuoso Analog Design Environment, and the simulator is Spectre RF. You can use standards-based stimulus, saving verification time: IEEE 802.11 family, LTE, LTE-A, ZigBee and 802.15.4g. Modulated sources are found as components in a library, and they are used as input to the Design Under Test (DUT), making your simulation setup time a lot quicker.

    Related – How ST Designs with Layout Dependent Effects (LDE)

    In the GUI you select the wireless modulated source from a library, then the simulation engine automatically fills in the parameters: sampling rates, stop times, strobe options and carrier frequencies to comply with the standards.

    In Spectre RF the fast envelope simulation engine can characterize and then create a model of the DUT, giving you up to 1,000X faster simulation results compared to a transistor-level envelope simulation approach. RFIC architects and designers can see plots with constellation and ACPR, the critical measures of distortion:

    Summary

    RFIC designers and architects have choices when it comes to their design and verification methodology. The approach offered from Cadence has useful automation to reduce verification times in a single-vendor flow. View the complete 6 page white paper here for more details.

    Related – What’s New with Circuit Simulation for Cadence at DAC

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    eSilicon Try IP Before You Buy

    eSilicon Try IP Before You Buy
    by Paul McLellan on 01-15-2015 at 10:00 am
    Categories: eSilicon, Semiconductor Services

    I’ve written before about eSilicon’s IP Marketplace. This is the latest in several steps to automate more and more of the interface between eSilicon and its customers: MPW quotes, production quotes, tracking orders through manufacturing, and now IP quotes. There is a phrase in software development called “eating your own dogfood” meaning making yourself use the software and techniques that you develop. That way you find problems and fix them really fast. As an industry, semiconductor enables the entire internet and all the various businesses on it but we have not been very good at eating our own dogfood and using the e-commerce techniques that we enable others to use. eSilicon is on the cutting edge for this today.

    See also eSilicon’s IP Marketplace

    There is a webinar coming up next week on IP Marketplace called Try IP Before You Buy. It will include a live demo of the system. The webinar is on Wednesday January 21st from 9.00am to 9.30am Pacific. So what will you see?Within the IP MarketPlace environment, we’ll explore real-time PPA evaluation and memory instance generation, followed by Q&A.


    In a little more detail: you will see real-time PPA analysis: See how you can get immediate answers to your power, performance or area (PPA) questions on eSilicon memory compilers and I/Os using the IP MarketPlace environment:

    • Generate dynamic, graphical PPA analyses
    • View your chosen data graphically, in table format, or download to Excel
    • Build and download a complete chip memory subsystem
    • Generate and download IP front-end views
    • Run simulations in your own environment
    • Purchase the right IP when you’re ready

    Like the rest of the eSilicon Online Tool Suite, the IP MarketPlace tool is available at no charge or obligation.

    eSilicon regards this whole Online Tool Suite as a competitive advantage. In fact the CEO of eSilicon, Jack Harding, has an interesting blog entry on the topic:Approximately two decades ago Michael Porter observed, “There are no longer any low-tech industries, only low-tech companies.” Ironically, the very semiconductor industry that has contributed enormously to Mr. Porter’s declaration now finds itself a laggard in the same ecosystem it has enabled: the e-business community. For how long will we crush the grapes barefooted? Or will we embrace the inevitable, drive our own efficiencies and tame the complexity curve that provides both our challenges and opportunities?

    Read Jack’s blog entry here.

    You can register for the webinar here.


    More articles by Paul McLellan…

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    Customizable IP for HP and LP Audio Subsystems

    Customizable IP for HP and LP Audio Subsystems
    by Pawan Fangaria on 01-15-2015 at 4:00 am
    Categories: Cadence, IP

    Today, Smartphones and mobile devices have become center of innovation with multiple functions getting into them. Considering the audio or voice application, there can be multi-way conferencing, video chat, complete audio/video streaming, gaming, voice triggering and recognition,… you name an application, and it will be there on your Smartphone in most probability. While it has created so easy and flexible use of all these features in the hands of user, it has very significantly increased complexity in the hands of mobile SoC designers who need to deliver these features with high-performance, high-resolution, multi-channel audio stream processing, high quality speech recognition, always-on voice trigger, and all that at extremely low-power.

    In audio/voice subsystems, DSP cores are used to handle data processing, compression, sample rate conversion, encoding/decoding, noise suppression etc. The audio DSP can be on an SoC along with the application processor or connected to the processor through a dedicated bus interface. The DSP core also connects to audio peripherals such as microphones and speakers, and cellular modem or WiFi/Bluetooth/FM radio combination through audio interfaces.

    While this system is reasonably fine, the demand for high-performance audio data processing and voice over IP (VoIP) with improved noise suppression and noise-dependent volume control raises the DSP complexity and needs further improved architecture of the DSP and audio subsystem. Considering battery life criticality for mobile devices and always-on voice trigger, the system also needs to have very low-power profile. To satisfy these requirements, the DSP architecture must be very efficient with configurable memory and I/O partitions, advanced power management and scalable instruction set extensions. Along with DSP architecture, it is critical that audio data transport takes place in most efficient and optimized manner for low-power and high-performance. Interestingly, MIPI Alliance has also come up with new audio interface standards to optimize audio subsystem connectivity for the benefit of mobile industry. Let’s see in a greater detail the audio subsystem with improved architecture and new audio interface standards.

    Here, the audio data transport is based on DSP-tunneled model instead of a common system memory to avoid multiple traversals of data on the bus hierarchy and the need to keep system memory and the bus hierarchy always powered. In the DSP-tunneled model, the audio data processing and transmit/receive through the audio interface are localized to the DSP processor with dedicated local memory and highly efficient FIFO-style interfaces; thus significantly reducing the power consumption.

    The brand new audio interface standard used is Soundwire that is designed to support multiple devices including audio peripherals and DSP codec. It easily can be scaled up to support multiple data lanes to transport wide PCM audio samples between the application processor and the DSP codec. It can also be optimized to support the transport of narrow PDM samples to microphones and speakers on a single data lane. To minimize power, the standard defines a modified NRZI data encoding and double data rate for data transmission that minimizes active driving and switching of the bus wire load. The clock rate changing and clock stop protocols are well defined to minimize power consumption in always-on applications.

    Cadenceis the leading provider of silicon-proven wide range of customizable IP for audio subsystem development. Cadence also leads the definition and development of the MIPI Soundwire standard.

    Among Audio DSP IP, Tensilica Xtensa processor family offers highly customizable processor cores with high-efficiency instruction set architecture (ISA) extensions. A class of optimized HiFi processors targets various segments – HiFi Mini for voice trigger and recognition; HiFi EP for consumer electronics; HiFi 2 for mobile audio and voice; HiFi 3 for high-performance audio.

    Among Audio Interface IP are I2S master/slave controller, S/PDIF controller, and MIPI Slimbus manager/device controller.

    Cadence’s leading-edge audio DSP processor IP cores and audio interface IP cores are most suitable to build audio subsystems for high quality audio effects for multiple audio channels. Don’t forget to look at Cadence IP portfolio, if you are planning to build a low-power, high-performance, high quality, optimized audio/voice subsystem. Refer to the whitepaper for more details.

    More Articles by PawanFangaria…..

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    Which Foundry will be First to FinFET?

    Which Foundry will be First to FinFET?
    by Daniel Nenni on 01-14-2015 at 8:00 pm
    Categories: ESD Alliance, Events, FinFET

    The final session of the SEMI Industry Strategy Symposium (The CxO Panel) was the most interesting for me because executives from three of the four most influential semiconductor companies were on the panel: Dr. Goeff Yeap of Qualcomm, Dr. Jack Sun from TSMC, and Mr. Mark Bohr of Intel. Who is fourth you ask? That would be Apple of course. In my opinion the most interesting question asked of the panel was: Which foundry will be first to FinFET?


    The CxO panel closes the conference with a conversation between Dan Hutcheson and several esteemed executives at a CxO level. This year, we will be examining what it takes to practically transition a new technology to manufacturing and through its yield ramp. There’s no magic in it for these execs: they have to make finFETs yield today while rolling 10nm and 7nm processes down the gangway    from pathfinding into development. It is a task that has consumed many at prior nodes. They have closed their doors on Moore’s Law. Our panelists are the champions who won at these nodes and will keep moving down the scaling path. They will do this with a combination of their own internal excellence and an unparalleled ability to partner with others to align a global base of researchers and engineers — all towards hitting a specific ramp date that is exactly two years after the last one. They’re going to talk about how it’s done against a background in which every node gets bigger, faster, and riskier. They’ll provide their vision about the future, the challenges, and the opportunities.

    Before I give you my ranking of which foundries will ship 16/14nm FinFETs first let me say a few words about Mark Bohr. I have always said the key to success in the semiconductor industry is showing up. Meeting customers and partners, writing papers or blogs, and attending conferences. Some call it collaborating but I call it showing up. Speaking at conferences is important too but if you only speak and do not actually attend that does not count. And don’t think we do not know who arrives right before their time slot and leaves right after because we most certainly do.

    Mark Bohr not only spoke at ISS he showed up. I sat in the row next to him and chatted with him during breaks. He was not on his phone, he paid attention and took notes. He also graciously accepted a copy of “Fabless: The Transformation of the Semiconductor Industry” and I sincerely believe he will read it.

    Which Foundry will be First to FinFET according to me:

    [LIST=1]

  • Samsung 14nm LP Q1 2015
  • GlobalFoundries 14nm LP Q2 2015
  • TSMC 16nm FF+ Q2 2015
  • Intel 14nm 2H 2015
  • UMC 14nm 1H 2016

    Mark’s answer to the question by the way was “not Intel Foundry”. Another interesting comment from Mark was that Moore’s law will continue another 10 years but he says that every 10 years. Mark also explained to me the difference between the 14nm processes used for the Intel CPUs and SoCs. It really is the same process, same basic transistor structure, materials, design rules, and minimum interconnect pitches at the lower layers. The SoC version however has a wider range of devices (high-voltage and ultra-low leakage transistors) and a few more process steps. The bottom line is the processes are similar enough to run in the same “copy exact” fabs and that is quite an achievement, absolutely.

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    SEMI ISS: The Outlook

    SEMI ISS: The Outlook
    by Paul McLellan on 01-14-2015 at 12:11 pm
    Categories: ESD Alliance, Semiconductor Services

    I spent Monday at the SEMI ISS meeting in Half Moon Bay. There is a lot of stuff to choose from, the entire day was interesting throughout. The day started with a keynote from Scott McGregor, the CEO of Broadcom. I’ll cover that in a separate posting.


    Next up was Andrea Lati of VLSI Research on The Cycle: Is It Different This Time?He started with a review of 2014. Things that went right:

    • Apple’s A8 in 20nm at TSMC
    • Intel’s 14nm FinFET
    • EUV moving to production insertion at N10

    And what went wrong:

    • 450mm put on back-burner, won’t happen until 2023 or later (or never in my opinion)
    • 3D TSV still three years out
    • Electronics market continued to grapple with falling ASPs (commoditization of smartphones, tablets fizzled, electronic market overall growing slower than semiconductor)

    The answer to the question in the title of his talk was that magnitude of swings in the silicon cycle are much dampened when looking back as far as the 1980s. Equipment seems to be on a 2 year cycle for a couple of decades and based on history 2015 should be a good year. The big unknown: China goes nuclear to expand its semiconductor industry (for the 3rd time, maybe it will work this time).


    Next up, Mario Morales of IDC on What’s Next for the Semiconductor Market. By the end of 2015 he expects:

    • A base of 680M iOS and 1.7B Android devices
    • 3.3M apps available, 45-50 apps downloaded per year per device
    • But key market indicators are slowing
    • Tablet market his wall (iPad shipments actually declined) partially due to cannibalization by Phablets

    IoT will start in industrial where there are already massive amounts of data coming online. One machine at one plant might produce 1TB/day of data to be analyzed. IoT will then expand into the home. Challenges are low power, cost and security.


    Mike Corbett of Linx-consulting talked about materials. One interesting datapoint is that wafer cost is growing 41% node to node but the material node to node growth rate is 43%. As a result, materials are growing as a portion of wafer cost, especially sub 20nm due largely to all the additional material required for double patterning. DRAM is similar, with 9% node to node wafer cost growth but materials cost growing at 14%.


    Nariman Behravesh had his Top 10 Economics Predictions for 2015. So here they are:
    [LIST=1]

  • US growth will be solid in the 2.5-3% range
  • The European recovery will proceed at a sluggish pace but UK growth will be robust
  • Japan’s economy will regain weak growth momentum
  • China’s growth will decellerate more but remain stronger than most
  • A few emerging markets will struggle (Brazil, Russia) whilemany will see above average growth
  • Commdity prices will slide further (oil $60-70)
  • Inflation will remain a distant threat while deflationary worries persist
  • The US Fed, Bank of Canada, Bank of England will likely being raising rates while other central banks will be on hold or provide more stimulus
  • The US dollar will rise against most currencies while the Euro and Yen will fall
  • Perennial downside risks will be balanced by some upside risks (delveraging is largely over in US and UK, rising US oil production and the fall in prices is a $1.5T transfer, 2% of world GDP, from oil exporting to oil consuming countries)

    Finally, to wrap up the morning, Roger Baker of Stratfor gave a Geopolitical Forecast: Trends Shaping Semiconductor Manufacturing Countries. There was so much information it was like drinking from a fire-hose. But here are his key issues:

    • China is in a heightened sense of security and attempting an economic rebalancing towards consumption
    • Japan is attempting to brek from a 20-year malaise
    • Korea and Taiwan will be squeezed in the middle
    • ASEAN will exploit a slow but increased integration
    • US opportunities are expanding


    To pick one slide, China is attempting to push urbanization from 51% in 2011 to 70% by 2030. It plans to do in 17 years what took the US 50 years.

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    The Dynamics of the China Semiconductor Industry

    The Dynamics of the China Semiconductor Industry
    by Daniel Nenni on 01-14-2015 at 7:00 am
    Categories: ESD Alliance, Events, Foundries

    Paul McClellan and I are at the SEMI Industry Strategy Symposium this week in Half Moon Bay. Honestly there is too much to blog about here so I will have to pick the topics most interesting to me. The full capacity audience is also impressive. SEMI provides a list of attendees on their website which reads like “Who’s Who” of the semiconductor industry, myself included. I may not be a “Who’s Who” yet but according to LinkedIn my profile is one of the most searched, so I have that going for me.

    One of the best presentations today was by Dr. Simon Yang of XMC in regards to the dynamics of the Chinese semiconductor industry. It was not canned, it was very real and full of experiences, observations, and opinions which is much more interesting to watch of course.

    XMC is China’s leading 300MM semiconductor manufacturing company. It was founded in 2006 in Wuhan, China and first began production in 2008. XMC provides its professional foundry service offerings to leading electronics companies worldwide. XMC focuses on developing specific customized solutions with its partners. Among its key area of expertise are memory and sensor manufacturing solutions. XMC is a recognized leader in NOR Flash memory production and BSI technology. XMC focuses on developing deep partnership and providing partners with tailored technology solutions to drive more innovation in the market.

    The Chinese government has been trying to bring semiconductor manufacturing to China for the past 25 years with very little success. The first China fab was a 6” established in 1990. An 8” fab was added in 1996. SMIC was established in 2000. 12” fabs were then added in 2006 and 2010. Unfortunately semiconductor demand in China has by far outweighed the ability to manufacture them. Currently China imports more than 50% of the world wide semiconductor supply while manufacturing less than 10%. Even worse, wafer manufacturing in China is less than 2.5% of the world wide production and is only at mature nodes (40nm and above).

    Simon quite honestly suggested that China manufacturing is much better at chasing slow versus fast moving technologies. Space travel and high speed transportation are two examples he gave. Another way to look at it is that with an advanced wafer manufacturing project you need to “do what you do not know how to do.” China is much more comfortable doing what they know how to do.

    Today semiconductor technology moves at lighting speed to satisfy the mobile SoC demand which drags along many more applications behind it. I do not see that changing anytime soon so this is a defining point for any country planning to make semiconductors part of their national agenda. For China it is not just satisfying internal semiconductor demand or national pride. In my opinion it is all about security. Electronics begin with semiconductors and so does the security of EVERY product that contains a semiconductor device, absolutely.

    Think about it, your smartphone knows your every move, your thoughts and secrets. Inside are billions of transistors that are “touched” by thousands of people. So how do you guarantee that all of those transistors are for good and not evil?