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Unit shipments of both PCs and smartphones versus a year ago have turned positive. According to IDC, PC shipments in 1Q 2024 were up 1.5% from 1Q 2023, the first positive year-to-year change since 4Q 2021. Smartphone year-to-year growth turned positive in 4Q 2023 at 8.5%. The growth continued in 1Q 2024 at 7.8%. 4Q 2023 was the first positive year-to-year smartphone change since 2Q 2021. Despite the positive trend in 1Q 2024, IDC projects modest year 2024 growth of 2.4% for PCs and 2.8% for smartphones.
Electronics production for most key countries in Asia is on an upward trend. Taiwan electronics production was the strongest, with three-month-average versus a year ago (3/12) change in February 2024 at 19.7%, the strongest growth since November 2022. China electronics returned to double-digit 3/12 increases in January at 11.6% after declines in early 2023. March 3/12 growth was 13.3%. Vietnam electronics production 3/12 change increased 3.0% in March, the sixth consecutive positive month after eight months of declines. Japan and South Korea were the weakest countries. Japan had a 3/12 decline of 1.4% in January, the second consecutive monthly decline following 14 months of increases. South Korea electronics production 3/12 change decreased 4.2% in February after slightly positive growth in December 2023 and January 2024.
Electronics production in the United States and Europe was not as robust as in most of Asia. U.S. 3/12 change was 1.1% in February 2024. Growth has been in the 1.1% to 1.2% range for the last seven months, slowing from 4% to 8% growth in each month of 2022. The 27 countries of the European Union (EU 27) reported 3/12 change in electronics production of minus 7.2% in January, the seventh consecutive monthly decline. The United Kingdom (UK) 3/12 change turned positive at 0.8% in February after five months of declines.
The global economic outlook looks steady for 2024 and 2025 according to a recent forecast from the International Money Fund (IMF). IMF’s April projection has world GDP growth at 3.2% in both 2024 and 2025, the same rate as in 2023. Among the advanced economies, the U.S. is expected to show one of the strongest growth rates in 2024 at 2.7% before moderating to 1.9% in 2025. The Euro area and the UK are below one percent in 2024, accelerating to 1.5% in 2025. Among emerging and developing countries, China is forecast to have growth moderate from 5.2% in 2023 to 4.1% in 2025. Much of the growth in the emerging and developing economies will be driven by India with GDP increasing 6.8% in 2024 and 6.5% in 2025. The countries of the ASEAN-5 (Indonesia, Malaysia, the Philippines, Thailand, and Vietnam) are projected to have GDP growth accelerate from 4.1% in 2023 to 4.6% in 2025.
India is replacing China as the key economic growth driver in Asia. Based on IMF data, India was the world’s eleventh largest economy in 2013. India’s GDP grew at a 6.8% compound annual growth rate (CAGR) from 2013 to 2023 to become the fifth largest economy. If India’s growth continues at that rate, it could become the world’s third-largest economy by 2028, behind only the U.S. and China. A recent CNN article explored the drivers of India’s growth as well as its lingering problems with poverty.
While overall electronics growth in 2024 looks encouraging, there are signs of frailness. Although the key drivers of PCs and smartphones are back to growth, annual growth is expected to be low. Electronics production is increasing strongly in Taiwan and China. However, key countries such as South Korea, Japan, the U.S., UK and EU 27 are experiencing slow growth or declines.
Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.
Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com
Ben Packman, Senior Vice President at PQShield, leads global expansion through sales and partner growth across multiple vertical markets, alongside taking a lead role in briefing both government and the supply chain on the quantum threat.
Tell us a little bit about yourself and your company.
PQShield is a post-quantum cryptography company creating the global standards and core technologies that will form the future security layer protecting the world’s leading organisations. Its quantum-secure cryptographic solutions work with companies’ legacy systems to protect sensitive data now and for years to come
As Senior Vice President, I am responsible for leading PQShield’s strategy and development. Our team is shaping the way our digital world is protected against the threats of tomorrow. In a time when quantum computers will soon be able to break current cryptography methods, we’re focused on empowering organisations, industries, and nations, with the ultimate quantum-resistant cryptography solutions.
What do you think the biggest growth area for 2024 will be, and why?
NIST’s post-quantum cryptography standards are due to be published within months, which will become the benchmark for cybersecurity globally. This will serve as a major growth area for PQShield as we expect to see a lot more companies taking the migration to post-quantum cryptography seriously.
We are able to guarantee to customers that our IP licensed products will be compliant with NIST standards giving them the confidence to incorporate our solutions into their post-quantum cryptography transition planning.
One area in particular where we expect to see growth is in the semiconductor and defence sectors, given their key position within the global supply chain and their need to secure highly sensitive data respectively.
How is your company’s work addressing this growth?
PQShield has already developed a mature suite of NIST compliant solutions across software, hardware and cloud applications and is already licensing its IP to strategic partners.
Several of PQShield’s customers that produce both software and hardware products are set to launch new solutions in 2024 that are already utilising PQShield IP. We have already partnered with industry leading semiconductor manufacturers like Microchip, AMD and Lattice, and world renowned defence contractors like MBDA and Collins Aerospace.
We’ve also focused on real-world implementation issues such as side channel and fault injection protection – we have our own lab in Oxford that we developed and verified working with Riscure and eShard. PQShield is leading the way in this area to ensure that our post-quantum cryptography solutions are robust.
What conferences will you be attending this year? We’ll be on the road a lot this year. We already have over 13 under our belt including Mobile World Congress Barcelona and OFC US. We’ve also had the pleasure of co-exhibiting with partners like AMD and Lattice at some of these events to showcase our products on the ground.
Coming up we have IQT Europe, RSA Conference, The Economist Commercialising Quantum, HOST, CyberUK, FPGA Conference, RISC-V Summit, CHES and many others. By the end of the year we’ll have done around 50 events!
We are also very privileged to be co-hosting PQCrypto in our home in Oxford this year – gathering some of the brightest cryptographic minds from across the globe at the Oxford University Maths Institute, where PQShield began.
Additional questions or final comments?
Within a decade, the mathematical defences that currently keep online information safe will be at risk from a cryptographically relevant quantum computer, sufficiently powerful to break those defences. In fact, even before quantum technology exists, there’s a significant risk of ‘harvest-now-decrypt-later’ attacks, poised to extract stolen encrypted information when the technology to do so becomes available. We believe it’s critical that industries, organisations, governments, and manufacturers are aware of the threat, and follow the best roadmap to quantum resistance.
We are at a critical moment in this transition. With a recent wave of early legislation in the US, such as NSM-10 and HR.7535, as well as CNSA 2.0 and the National Cybersecurity Strategy, federal agencies and government departments are now mandated to prepare and budget for migration to full PQC by 2033. Simultaneously in Europe, cybersecurity organisations such as ANSSI (French Cybersecurity Agency) and BSI (German Federal Office for Information Security) have published key recommendations on the quantum security transition, and in the UK, the National Cyber Security Centre (NCSC) is recommending clear next steps in preparing for post-quantum cryptography. Internationally the awareness is growing among governments of the challenge ahead. We recently presented at the European Parliament, attended a roundtable discussion at the White House, and we’ve been key contributors to the World Economic Forum on regulation for the financial sector.
When it comes to the security of tomorrow, the time to prepare is today, and at PQShield, we’re focused on shaping the way the digital world is protected from the inevitable quantum threat.
“Real men have fabs” was an insult AMD founder Jerry Sanders hurled at his poor competitors who could not afford to build fabs. A few years later, AMD would be fabless, spinning off its manufacturing facilities as GlobalFoundries. This was the beginning of a transformative period for the industry.
Lisa Su could rightfully retort: “Real women don’t need fabs!”
Before the transformative era, all semiconductor companies were Integrated Device Manufacturers (IDM) that held the reins of designing, manufacturing, packaging, testing, and selling all their semiconductors.
Being a leader in all aspects of Semiconductor Manufacturing was becoming increasingly complex and expensive. Only a few companies had the market position and the financial strength to continue as IDMs.
The first elements to be outsourced were the backend manufacturing, the packaging and testing. It was labour-intensive and not a part of the manufacturing process that added significant economic value. First, operations were moved to Asia, and later, they were outsourced entirely as specialised companies started to appear. The Outsourced Assembly and Test (OSAT) market was born.
The IDM age was a boring time for market analysts.
The individual companies still did the front end (Wafer processing) of the Manufacturing.
In the late 1980s, the Taiwanese government offered Morris Chang, the founder of TSMC, a blank check to establish a local semiconductor industry. He had been working for Texas Instruments and observed that Japanese semiconductor factories outperformed US fabs significantly. The Japanese successfully transformed their society into a technology-based economy that would outcompete the US for over a decade.
Morris offered Intel and Texas Instruments to invest in the company, but they declined. Philips decided to trade their manufacturing technology and IP for a quarter stake in the new company, and the first foundry was born.
The increasing cost of building fabs and developing new technologies limited the number of new startups in the industry. However, new companies could enter the market with TSMC carrying the Capex cost of developing technologies and building factories. The fabless companies created a new market segment competing in design and let TSMC handle the manufacturing. In 2008, AMD gave up and became fabless themselves.
The current market structure
Since then, the Semiconductor market has become an even more complex web of submarkets and categories. This is happening as the industry has risen from an economic engine to become a matter of national security.
Understanding what happens in the semiconductor industry has never been more critical or challenging.
We continuously develop our industry model to analyse the industry and provide data and insights to our customers. This allows us to study the interfaces between the different submarkets of the value chain and detect market ripples early.
In a value chain, somebody’s future might be somebody else past.
We are not arguing that our model is correct or cannot be improved; we only know that it works for us now and that we must continue improving it.
A graphical representation of our industry model can be seen below:
The model has zones representing the different stages of the Semiconductor business. The design zone in the middle is where the design authority and absolute product ownership reside.
The manufacturing zone on the left represents front-end wafer manufacturing, and to the right is an assembly of systems by EMS or OEMs and the distribution channel, if applicable.
The brand zone is introduced as some semiconductor design owners also have a visible brand towards the end users of their products.
At the right are the end users of the Semiconductor products. We work with four different categories. The latest are large capital projects representing the large cloud and AI projects that have changed the dynamics of the industry lately.
The investment zone at the top represents what is needed to enable design and manufacturing. At the bottom, the supply zone represents the supply channels for front-end and back-end manufacturing.
We monitor the boundaries between these zones for insights that can enlighten us on what happens in the semiconductor market.
The major semiconductor business models
The industry’s most traditional business model is the integrated device manufacturer (IDM), responsible for both the design and manufacturing of the value chain.
Only the largest and most profitable companies have been able to maintain this business model due to the increasing costs of building wafer fabs. Memory companies also follow this model, as being competitive in memory is linked very closely to being competitive in manufacturing.
The rise of TSMC allowed semiconductor companies to go Fabless and outsource front-end manufacturing to foundries, concentrating on the design, sales, and marketing of semiconductor products.
A handful of companies use a mixed model, where they own their fabs and also use foundry. This Fab/Foundry model is popular amongst analogue and power companies that can operate analogue and power fabs, even though the leading edge digital manufacturing is outside their reach.
Some semiconductor customers with specialised demand are now so large that they design silicon for internal use. The Chip Designing Customers are mainly the large cloud and AI data centre-owning tech companies.
The last category is the Brand Customers. In this category, the semiconductor cannot be directly bought but is part of a system. The semiconductor inside is “branded” to the market as part of the system. Apple started this category, and the company promotes the semiconductor content of its products in its marketing. Recently, Nvidia also entered this category with its GPU-based AI systems.
There will be future categories as a result of two intertwined trends. The move from CPU to GPU requires a move from components to systems to work.
The owners of bricks
As the semiconductor sector has changed from an economically driven global industry to a politically influenced area of national security, the level of education on the market composition has deteriorated.
Because of the complexity of the industry, no good information is available about where the chips are physically made. Each chip has several countries of origin as it moves through the value chain.
Most chips are not made in Taiwan or by TSMC.
We base our research on the country of incorporation, where the political influence is most substantial and on financial Property, Plant and Equipment (PPE). Manufacturing capacity is not the same as that of PPE, but in the semiconductor industry, the most significant part of PPE is manufacturing.
Using this with our industry model, we get the following view of the distribution of PPE:
This gives a more nuanced image of what authority the properties are under rather than where they are located. This is increasingly important as governments are starting to lean on their local Semiconductor companies for patriotic investments.
In Q4-24, the most significant growth of PPE was in China, while Taiwan was declining. Europe also showed strong growth, which needs to be added to the political dialogue.
Applying our industry model gives the following output:
This is a different image than the broader press paints. From a PPE perspective, the two large IDMs with a foundry model (Intel and Samsung) dominate. The Foundry PPE is actually in decline while all other areas are growing.
The growth of the companies with mixed Fab/Foundry models is fascinating. This shows that the smaller mixed Fab/Foundry companies are adding PPE faster than the other models, a sign of them becoming more of a manufacturing company than a fabless company.
Traditionally, they have been unable to participate in the crazy manufacturing race of processing semiconductors, which they have outsourced. At the same time, these companies have manufactured analogue and power products on their fabs. While still expensive, these fabs don’t need the same insane technology as the processing parts.
The investment situation
As PPE depreciates quite fast in the Semiconductor industry, representing the rapid technological developments, the manufacturing part of the Semiconductor industry is dependent on high-octane Capital injections revealed in the cash flow statements under Capital Expenditure or Additions to PPE.
While fabless semiconductor companies can get away with a CapEx-to-revenue ratio (how much of revenue is spent on CapEx) of 3-4%, the IDMs need to shovel 28% of their income back into CapEx, as seen below.
This chart also reveals the manufacturing appetite of the mixed Fab/Foundry model companies. While Analog Devices and NXP are closer aligned with the Fabless model, Infineon and ST of Europe are pursuing more manufacturing. At the top is Texas Instruments, with a 29% Revenue to Capex Ratio in Q4-23.
TI’s recent Q1-24 result revealed that the company now has a ratio of 34%, showing a steadfast commitment to more manufacturing. The company also expect to be able to capture a $1B grant from the US Chips Act.
The Foundry investment situation
The “Most chips are made in Taiwan” story should be “Most Foundry manufacturing is in Taiwan” instead. In Q4-23, TSMC represented 62% of the revenue and 87% of the operating profits in the Foundry market, so it is undoubtedly the gold standard. (A deeper dive into the Foundry market is here.)
The CapEx to revenue ratio for the foundries can be seen below:
China foundries outspend all Others.
While the investments from the Taiwanese foundries have been high, they have been significantly outspent by the Chinese foundries. At times with CapEx that a higher than revenue, revealing the foundries operate in a different economical system than the reset. Recently also the American foundries have climbed higher and now has a CapEx to Revenue ratio slightly higher than Taiwan.
We keep monitoring the dynamics in the Semiconductor Industry using our proprietary models based on facts. If you want access to our data or neutral input to your strategy process, please contact us at: claus.aasholm@SemiBizIntel.com
How much can running on a multi-core (Arm) CPU speed up fault simulation? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.
This paper on fault simulation throughput exploits parallelism on a multi-core CPU. Curiously there is no mention of safety applications in this or in a recent reference they cite, suggesting an enduring interest in China for fault sim for regular test grading, here I would imagine for communications systems? The authors mention GPU-based and distributed compute as acceleration alternatives but note these suffer from multiple drawbacks. In contrast, they claim their proposed solution using 128 cores is much easier to program and offers meaningful acceleration.
Paul’s view
Verification of test patterns is an N x M style problem where N is the number of patterns and M is the set of possible faults (stuck-at-1, stuck-at-0, …). Each pattern-fault pair can be simulated in parallel, but for commercial scale designs N x M is in the billions so there is still a massive amount of serialization of sims even if thousands of CPU cores can be allocated.
This paper shares 3 insights parallelizing pattern-fault sims on modern high core-count Arm servers to maximize throughput. Results are presented on a 128-core Huawei Kunpeng 920 server.
The first insight relates to vectorizing faults, what commercial EDA tools call “concurrent fault simulation”. A 64-bit word can be used to represent the value on a wire across 64 different fault simulations. The authors observes that the SIMD capabilities in the Arm NEON unit can be used to increase the number of concurrent fault sims per core from 64 to 128. This gives a ~1.6x speed-up.
The second insight relates assigning pattern-fault pairs to cores. The authors observe that it’s better to parallelize patterns across cores rather than faults across cores. This gives an impressive 2.2x speed-up.
Lastly the authors observe that the 128 cores are split across 4 dies, each die with a direct link to “local” DRAM memory. Any core in any die can access DRAM from any die, but the latency for local DRAM access is 3-4x faster. By replicating the design data (which is constant and shared across all sims) in local DRAM for each die they get a 1.2x speed-up.
Overall, tight paper with clear insights and real benefits directly applicable to commercial EDA use today. Nice.
Raúl’s view
Fault simulation can be accelerated by simulating faults or test patterns in parallel; faults are independent of each other as are test patterns. This paper evaluates simulating faults and test patterns in parallel on a specific non-uniform memory access (NUMA) architecture, Kunpeng 920. It consists of 2 CPUs with two nodes each, each node having 32 ARM cores. The local node memories have varying access times depending on which node is accessing them.
The paper explains all the methods used to accelerate simulations: As usual many bits are packed into a word; using a particular data type in the ARM NEON architecture, 64 or 128 patterns can be simulated simultaneously; Execution threads are bound to cores and memory based on the memory access delay (binding optimization). The simulated netlist is replicated to optimize cross-node memory access; Fault data is segmented and allocated to the four memories.
The experimental results for 5 circuits (ITC99 and IWLS2005 benchmarks and industrial circuits, presumably their own) show that, as expected, pattern parallelism is faster than fault parallelism by a factor of 1.11-3.74, around 2 on average. This is because in pattern parallelism fault simulations can be started right after each pattern is simulated correctly (on the faultless design), while in fault parallelism first all patterns must be simulated correctly. However, pattern parallelism consumes more memory. Other results reported are: Parallel simulation of 128 patterns is about 1.6 times quicker than 64; Binding optimization gives 1.06x to 1.29x speedup; Lastly, cross-node memory access optimization gives 1.13x to 1.52x speedup.
The paper does not review or compare the state of the art, does not contextualize the work, and makes unsupported claims such as “Compared with the previous technical scheme, the ARM multi-core CPU used in this paper has the advantages of low cost and low energy consumption…”. I found the paper a valuable report that contains many details of the implementation, and a helpful insight into how to speed up fault simulation.
There has been much interest in Huawei’s and SMIC’s plans for 5nm production in the near future. Since there is no use of EUV in China, immersion DUV lithography (with a 76 nm pitch resolution) is expected to be used along with pitch quartering to achieve pitches in the 20-30 nm range expected for the 5nm and 3nm nodes [1].
However, Samsung and TSMC were early adopters of EUV technology, and had not demonstrated the use of immersion lithography with pitch quartering in their metal layers, for 7nm onwards. Intel used pitch quartering with an extended effort to bring 10nm (now Intel 7) to production. This effort spanned years, with Intel subsequently adopting EUV. One thing in common with all these 7nm developments was that they all had been disclosed in the 2017-2018 timeframe. Hence, all three companies have not had the chance to digest the latest improvements in multipatterning productivity at the time. In this article, we will cover how these developments can be used to eliminate the expected burden of multipatterning involving pitch quartering, as expected for 7nm, 5nm, and 3nm nodes.
Self-Aligned Blocks
The first key development to highlight is the use of self-aligned blocking. This was published in 2017 [2-4]. The motivation here is that in order to cut lines with pitches between 20 and 40 nm into interconnect patterns, many (4 or more) additional block masks would be needed [2]. Moreover, the tight placement control for the individual patterns for blocking the trench etch due to rounding [5] is still thwarted by stochastic behavior. To alleviate this, self-aligned blocking arranges the lines to be alternately divided into two groups, each consisting of a different material to be etched (Figure 1). The two materials may be silicon dioxide and silicon nitride, for example. This division into two etch material groups naturally occurs with pitch quartering by self-aligned quadruple patterning (SAQP) [2].
Figure 1. Self-aligned blocking scheme. Left: original block arrangement has four separate cut masks (each indicated by different color). Right: self-aligned blocking allows two cut masks for the block arrangement.
By ensuring that the adjacent line material is not etched, the blocking pattern can be elongated, merging aligned cuts on every other line, as well as circumventing rounding consequences. As shown in Figure 1, four cut masks can be reduced to two. As EUV also needs to avoid the effects of stochastic rounding and edge placement error, self-aligned blocking has been incorporated into the well-known SALELE scheme [6].
Block/Cut Redistribution/Expansion
The second key development to highlight was disclosed even earlier [7-9]. The idea here is to redistribute cut locations by extending and/or shifting line segments (wires) as needed. Figure 2 shows an M0 (lowest metal layer) example [8].
Figure 2. Left: Original M0 layout requiring six cut masks. Center: Wire shifts and extension applied. Right: Self-aligned blocking applied, resulting in only two cut masks.
The extension and shifting of wires is effectively imposing a lower limit on wire length, allowing the minimization of cut mask cost, becoming two cut masks for either DUV or EUV case. Wire lengths going lower than this limit would entail two cut masks per etch material. Note that a single cut mask exposure using EUV is still at least 20% more expensive than two exposures using DUV [10-12]. Also, the cost of two EUV exposures for generating sub-40 nm pitch lines is more than 30% higher than that of SAQP with a single DUV immersion exposure [10,13].
For the longer lines on higher metal layers, like M2, the extra capacitance from extending the lines can be a concern [9]. An alternative to the cut approach may be letting the lines stagger with extended gaps between line ends (Figure 3) [9].
Figure 3. Left: M2 lines with assigned etch material in different colors. Center top: line extension applied for blue cut distribution. Center bottom: Without extension, an expanded block is used. Right: Expanded block for red cut.
The line end gaps are naturally filled by expanding the block patterns instead of extending the affected lines. Perhaps the final shapes of the expanded block patterns can be fine-tuned by computational lithography such as NVIDIA’s cuLitho.
Vias in Self-Aligned Blocking Scheme
As a third key development, the patterning of self-aligned vias [14] in the self-aligned blocking scheme should follow the splitting into two etch materials, and can also take advantage of the doubling of the etch mask pitch (Figure 4). This leads to two via lithography masks corresponding to the two etch materials.
Figure 4. Self-aligned via with self-aligned blocking. Left: Block mask (green) for red etch material. Center left: Via photoresist mask (gray) for red etch material. Center right: Partial etch for via (brown) in red etch material, and removal of via mask. Right: Removal of block mask, revealing previously patterned blue etch material and via.
What If…?
If the start of 7nm development happened after 2017, most likely DUV immersion lithography would have been used not with brute-force multipatterning but with self-aligned blocking and block redistribution / expansion. There would be a maximum of two cut masks per metal layer (with an additional two in worst case for M0) and two masks per via layer (with an additional two in worst case for V0), corresponding to the two etch materials.
Once in use, the 5nm and 3nm nodes would also have been covered. EUV development would of course still be continuing to keep pace, and perhaps the NA would have been increased earlier. It would have been an interesting alternative history but now, going forward, it appears only new semiconductor players at advanced nodes can exploit the full benefit of 20-20 hindsight.
Securing the data and all the associated transactions that comprise our hyper-connected world is a daunting task. Security touches the hardware, software and all the channels connecting every device and every transaction. Threats can be embedded in software, hardware or systems can be compromised externally using a large array of active and passive technologies. The breadth of this problem can be overwhelming, and the coming maturity of quantum computers promises to make it a lot easier to break current state-of-the-art encryption. Fortunately, there is growing focus on holistic security and some companies are dedicated to this cause. Secure-IC is one such company that brings a wide array of technologies to bear on this problem. Recently, I had the opportunity to speak with a couple of veteran technologists at Secure-IC to explore some of the company’s capabilities and impact. Let’s explore how Secure-IC is making the cyber world a safer place.
Stepping back a bit, the collection of hardware and software tools and technologies from Secure-IC are offered under the Securyzr™ brand. Capabilities to evaluate the robustness of a system are offered under the Laboryzr™ brand. Let’s explore each of these offerings through the eyes of my contacts at the company.
Brice Moreau is a Product Management Engineer at Secure-IC. He has been with the company for over 11 years. His focus for our discission was Securyzr. Brice began with an overview of the architecture of Secure-IC’s hardware, including the RISC processor, the various system interfaces, monitors, accelerators and memories. There are many dimensions to the technology, and I began to see how everything fits together.
Brice took me through a demo for the boot-up of a system, all the safeguards required, and a view of the data transactions monitored. In-system operation was then shown with many of the safeguards active. This includes sensing an externally driven temperature overload intended to put the system in a non-standard state. This event is logged, and appropriate action is taken. In this short demo, I got a feeling for the robustness of the Secure-IC solution. An overview of the wide range of applications supported was also provided, which paved the way for our next discission.
Next, Brice discussed the Securyzr S700 Series, which provides capabilities focused on security for the automotive market. Specific capabilities required for automotive applications were reviewed, along with a discussion of how these technologies can be embedded in ECUs in the vehicle, such as telematics, ADAS, gateway, control units, powertrain, V2X, and infotainment. Compliance with associated standards was also discussed.
Fleet management vie the cloud
After that, Brice discussed the Securyzr integrated Security Services Platform, describing how to implement secure device fleet management via the cloud. The demonstration he provided illustrates the hardware and software required and how the interfaces and monitors are set up. How new devices are provisioned was also shown, as well as checking devices for overall health and managing exceptions.
Our discussion ended with an overview of the PQC Evaluation Kit. This product focuses on implementation of security in the Post-Quantum Cryptography (PQC) era. New algorithms to fortify security against quantum computing capabilities has been defined by the NIST and NSA. The evaluation kit contains the hardware and software required to prototype and test the new NSA algorithms against target system implementations. An important step toward making systems robust in the PQC era.
Brice concluded our discussion by commenting, “From fortifying automotive ECUs to managing device fleets securely in the cloud, Secure-IC’s Securyzr solutions can safeguard devices and networks against emerging threats and vulnerabilities.”
Valentin Peltier is a Cryptography Engineer at Secure-IC. He has been with the company for over 10 years. His focus for our discission was Laboryzr. Valentin began by discussing how Secure-IC helps its customers verify the robustness of systems with essentially a security evaluation laboratory. He explained that while cryptographic algorithms are claimed mathematically impossible to attack, the implementation of those algorithms in a physical chip can open up the system to multiple threats, such as side-channel analysis, fault injection attacks, or hardware trojans injected during manufacturing.
First, he described how Laboryzr delivers hardware and software capabilities to analyze the robustness of hardware as it is designed and after it is manufactured. There are also tools to analyze the software that runs on the system, creating a complete view, right down to the line of code that may be causing a problem.
Digging a bit deeper, he discussed the Analyzr™ SCA for Reverse Engineering (SCARE). Here, methods of using side channel analysis to reverse engineer the target system (the memorable acronym SCARE) are used with a particular focus on the robustness of the all-important AES encryption. He detailed the hardware and software technology used to implement target system evaluation, including some unique sensor probes developed by Secure-IC.
Valentin concluded with a review of side-channel analysis on smartphone devices. Here, he presented the details of how to use side channel analysis on a cell phone to examine the robustness of the RSA algorithm. An electromagnetic probe is used to gain access to internal operations on the cell phone. The resultant data then goes through extensive analysis. The adage “you can run, but you can’t hide” came to mind during this part of our discussion.
Valentin concluded our discussion by commenting, “With Laboryzr, we offer a comprehensive solution for evaluating hardware and software security, providing our customers with insights from chip design to post-manufacturing analysis.”
To Learn More
My discussions with Brice and Valentin were quite useful and eye-opening. If security is on your mind, you can also reach out to Secure-IC to discuss your requirements here. And that’s how Secure-IC is making the cyber world a safer place.
TechInsights recognizes Earth Day 2024 by lifting the screen on smartphone semiconductor sustainability
Smartphones are typically compared based on screen size, processor speed, and camera resolution. But when TechInsights looked at carbon footprints for manufacturing just the semiconductors of three flagship phones, they found a 20% difference in carbon output. Multiply that against TechInsights’s forecast that 1.16 billion new smartphones will be shipped in 2024, and the difference in carbon emissions is similar to what you’d see from a passenger car circling the globe more than 46,000 times.
Semiconductor manufacturing is energy intensive and uses a variety of high Global Warming Potential (GWP) gases to create intricate circuitry patterns on silicon wafers. Yet, despite the growing importance of sustainability considerations to consumers, reviews of mobile phones typically focus on cameras, battery life, cellular connectivity, and overall performance, rather than carbon emissions associated with these mini-super computers.
That’s unfortunate, as not all semiconductor manufacturing processes are created equal when it comes to their impact on the environment. Greenhouse gas (GHG) emissions from semiconductor manufacturing can vary greatly depending on the technology process node being manufactured and the location of the wafer fab.
Whether you favor the a Samsung Galaxy, all smartphones have a sizeable lifecycle carbon emissions footprint, and approximately 80% may come from manufacturing. To better understand what emissions are associated with the manufacture of mobile phones, three processors used by Apple, Huawei, and Samsung in their most advanced phones were evaluated by TechInsights.
One of the most significant impacts on semiconductor carbon emissions is die size. When die size increases, the yields go down, and you end up with higher emissions per good die. Reviewing Scope 1 and Scope 2 emissions per wafer in terms of carbon dioxide equivalents, the Qualcomm SM8650-AB has the lowest emissions per wafer, followed by the A17 and Kirin 9000s. When emissions per die are evaluated, the trend reverses; the largest processor, the Qualcomm SM8650-AB, has the highest emissions per die, while the smallest processor, the Kirin 9000s, has the lowest total emissions.
Now compare the carbon emissions numbers and you can quickly find that there is a 20% difference in the carbon footprint for manufacturing just these three chips. That might not immediately sound like much, but the impact of one versus the other is equivalent to what the US EPA estimates as the carbon footprint of the average gas-powered passenger vehicle. Still not adding up to much? Multiply that against the 1.16 billion smartphones TechInsights forecasts will be shipped in 2024, and you’re looking at the equivalent of driving around the Earth 46,000 times.
Of course there are hundreds of semiconductors in smartphones which have their own carbon footprint. In this preliminary analysis, it was found that process node, fab location, and abatement efficiency have a strong impact on semiconductor emissions from manufacturing. However, die size had the most significant impact on the carbon intensity on the processors evaluated. An opportunity exists for Scope 2 emissions associated with the A17 and Qualcomm SM8650-AB to be significantly lowered by utilizing lower carbon electricity.
For more details and data pulled from TechInsights latest Semiconductor Manufacturing Carbon Model, read Analyst Lara Chamness’ Earth Day article: “A Tale of Three Phone Chips: Eco Version.”
About TechInsights’ Semiconductor Manufacturing Carbon Model
The TechInsights Semiconductor Manufacturing Carbon Model is the first of its kind to detail Scope 1 and Scope 2 carbon emissions at a wafer and die level. This is achieved by bringing together the equipment, processes, and manufacturing steps for Logic, DRAM, and NAND into a single tool for leading 300mm wafers produced by 184 total fabs. Updated in April 2024, the tool allows users to create their own unique analyses of carbon emissions through editable fields like utilization, abatement, and electric carbon intensity.
Synopsys recently hosted an information rich-webinar, modestly titled “Improving Quality, FuSa, Reliability, and Security in Automotive Semiconductors”. I think they undersold the event; this was really about managing all of those things through the lifecycle of a car, in line with auto OEMs strategies for the future of the car. The standout message for me was total lifecycle management, from initial semiconductor architecture and design through end-of-lifecycle. I heartily recommend watching this webinar.
Heinz Wagensonner on an OEM perspective
Heinz is Manager of the Audi Progressive Semiconductor Program. He opened with a reminder of how an auto OEM sees the electronics future – advanced driving support, immersive experience and rethinking how to monetize added value options. One interesting set of stats is around mission profiles measured in hours of active operation over the car lifetime. For a traditional ICE car this has been 8000 hours (about 1.5 hours per day over a 15-year life). For an EV the mission profile extends to 55,000 hours, perhaps providing power to the house at night, and during the day charging or operating while supporting more functions than in earlier models. Heinz sees future EV profiles running to 130k hours, supporting multiple always-on functions such as face-id to enter and start the car, always on networks for OTA updates, and security to guard against threats.
Today advanced systems build on advanced processes (TSMC are already offering a 3nm early automotive development kit), very capable but with minimal track record in reliability (automakers used to require 5 years minimum). Domain specific devices with complex mission profiles compound the lack of track record. Mission profiles, advanced processes and advanced designs together point to a potential crisis for OEMs; an NHTSA report cites nearly 5 million ADAS-related recalls in 2022. At $1,000 per car, this is already a very expensive problem.
While mitigating the problem starts with strong design, Heinz also stresses in-service monitoring and compensation as an important part of the solution. On-chip sensors are central to these techniques. Such sensors play a role in preventive maintenance, perhaps warning the driver of an anticipated problem calling for a near term service visit. Or an imminent problem demanding the vehicle be switched to a safe state and the driver take immediate action (pull over to the side of the road).
Those features can prevent or mitigate a hazard in use before it happens. What happens when the car is taken in for a service? Heinz elaborated the highly complex and apparently quite brittle path to diagnose a root cause from initial service down through the value chain. As an example, 80% of ECUs assumed to be a problem root cause (and then replaced) prove on more detailed analysis not to have been the source of the problem! Yet following all diagnostic steps from initial service to a Tier 2 (semi supplier) can take 30 days if the root cause can be isolated. This overhead is unsustainable for managing warranty costs, potential for a recall, or worse.
He sees the path forward as a combination of on-chip sensor data, learning from prior problems through AI, combining in Signature Failure Analysis (SFA). Accumulating learned experience will lead to high confidence fixes which can be applied cost-effectively during a service call and can also provide effective and accurate feedback to Tier 1 and 2 suppliers. Some signatures may not map to a known problem and will still need to follow the long diagnostic path. However once resolved, they too can be added to the training database.
Alessandra Nardi on an EDA perspective
Alessandra is a Distinguished Architect in the Systems Solution group at Synopsys and a guru in automotive IMHO; every Alessandra talk I have attended has given me a better understanding of automotive system design and directions, with little to no product marketing. Her talk called for a holistic view of lifecycle challenges, starting with design then running through ramp, production, and in-field monitoring.
In-design optimizations for PPA and robustness are already well understood though still suggest opportunity for further advances. Here she highlighted need for improved modeling of uncertainty, through refined sensitivity analyses of variations based on different factors (voltage, temperature, etc) rather than blanket margins. Data gathered during ramp and production analyses through in-chip monitors placed during design will drive this learning. In turn that can drive yield and reliability optimizations and improvements to PPA, safety and other metrics. The same monitors can capture data during in-field analysis, feeding back information to the supply chain to drive additional optimizations while also enabling real-time tuning through techniques like adaptive voltage scaling.
The central component of in-chip monitor methods is a machine-learning system, gathering mission feedback from monitors to learn sensitivities/signatures for trends or outlier behaviors. In ramp or production these may suggest need for silicon or process revision fine-tuning. Similarly, an ML model can support in-field diagnoses and tuning.
Alessandra hinted that such lifetime optimization systems are not only important for automotive markets. Everything she and Heinz talked about is likely also important in aerospace and defense, industrial, medical and infrastructure markets though with different thresholds across the various metrics discussed in this webinar. I would imagine that even sustainability may play an increasing role, at least in product lifetimes and power consumption.
Fascinating discussion. Again, you can access the webinar HERE.
Dan is joined by Robert Ruiz, product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys, Novas Software, and Viewlogic Systems. He has more than 30 years of experience in advanced EDA technologies and methodologies and spent several years designing ASICs.
Robert talks about the rising verification challenges for debug and coverage closure for advanced designs with Dan. The time spent on these activities is rising, with data suggesting debug and coverage closure can occupy 75% of the verification cycle.
Robert describes several approaches from Synopsys that can provide a 10X – 60X improvement in productivity for these activities. New software tools, methodologies and the application of AI are all discussed along with an overview of the new UI for Verdi and how it impacts the process.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
ASML- better EPS but weaker revenues- 2024 recovery on track
China jumps 10% to 49%- Memory looking better @59% of orders
Order lumpiness increases with ASP- EUV will be up-DUV down
“Passing Bottom” of what has been a long down cycle
Weak revenues & orders but OK EPS
Reported revenue was Euro5.3B and EPS of Euro3.11 versus expectations of Euro5.41B and EPS of Euro2.81.
Guidance was for revenues of between Euro5.7B and Euro6.2B versus street expectation of Euro6.49B.
While reported revenues were less than expected its obvious that Q2 outlook was more of a concern and significantly less than what was expected by the street.
A Lumpy business gets lumpier as ASPs increase
With High NA EUV systems costing many times the cost of an ArF tool, it should be no surprise that EUV and high NA EUV systems ordered or delivered in different quarters will cause significant variation in revenues and guidance. This is obviously exacerbated by the highly cyclical nature of the industry and fickle customers that can turn spending on or off very quickly.
In 2023 we saw some huge order numbers, way above expectations.
It would likely be better for investors to look at averaging orders and revenue over a longer time period.
At the very end of the day, the need for lithography systems is both increasing along with the average selling price.
We have covered ASML since working on its IPO in 1995 (almost 30 years!) and when we look back over the long term trend line of revenue, the story is quite amazing and not likely changing much going forward…
Memory will be up in 2024 and Logic will be down
There have been significant logic orders over the past year or more with very little memory business as memory had significant excess capacity. Going into 2024 we will see memory orders picking up as the memory industry continues to recover while we will go through a digestion period in Logic of all the equipment previously ordered and delivered.
Memory bookings jumped from 47% of orders to 59% in the quarter while logic dropped from 53% to 41%.
We have already heard from several memory makers that their overall Capex will start to recover in 2024. We would caution investors that while memory is getting better we still have strong supply and pricing is still a bit flakey.
High bandwidth memory will be a very bright point but investors still need to remember its only 5% of the overall memory market, although growing very quickly
China is up to 49% in revenues but down in actual amount
On face value 49% of revenue from China seems concerning but we would point out that this represents a smaller actual dollar amount than China’s peak business last year. China has increased as a percentage as the rest of the world has slowed more. The more interesting thing we would point out is that while China was 49%, the US was almost a rounding error at 6%, which continues to show how the US is being outspent by China by a huge margin. This is not something new but is a long term ongoing issue. It will be difficult for the US to catch up spending such a paltry amount.
2024 is second half weighted
Given the long lead times of equipment and production planning, ASML’s 2024 will be back end loaded. Overall we are still looking like 2024 will have similar business levels as 2023.
Essentially what we have is a U shaped curve with the end of 2023/beginning of 2024 being the bottom point of the somewhat symmetrical curve. While 2023 was logic dominated, 2024 will be more memory dominated
EUV will be up while DUV will be down in 2024
It should be no surprise that EUV will be up in 2024 as it is becoming the mainstay of lithography in the semiconductor industry.
Much as “G Line” and “I Line” lithography have become relics of the past that most current industry analysts have never heard of, so will DUV fade into history as EUV takes over.
We would point out that the wavelength to cost ratio of lithography systems is quite exponential when we compare the cost of G Line to I Line and DUV to EUV and finally High NA it is an exponential curve.
We wonder if a “Hyper NA” system could crack a Billion dollars?
Congratulations to Peter Wennink…Mr EUV
Peter Wennink, the CEO of ASML will retire after 10 years at the helm of the company. In our view he will clearly will be most remembered for navigating the company through the transition to EUV which was quite difficult and quite treacherous with many ups and downs. The final product is nothing short of amazing.
While Martin van den Brink was the technology visionary, Peter Wennink made it actually happen and turned ASML into the number one semiconductor equipment company in the world and the technology leader that is driving the industry creating many Billions of dollars in value.
The Stock
Investors will be disappointed with the weaker than expected revenues and the weaker outlook.
The stock looks to be down around 6-7% which we view as a bit of an over reaction and an opportunity for those investors with more of a longer term view past the lumpiness.
We remain positive on the stock and the story overall which has not changed.
We don’t see as much impact on other companies in the semiconductor space as ASML is a significantly different company with much longer lead times .
We expect most semiconductor equipment companies to be down in sympathy to ASML but we would remind investors that we have been saying for quite some time that the stocks had gotten way ahead of themselves with valuations that reflected a recovery that had already happened and quite strong.
The real reality is that we are at the beginning of a recovery that may not be as strong as expected and may take a while. As pointed out by ASML, we are just now passing the bottom of what we view as a “U” shaped downcycle and expect 2024 to be somewhat of a mirror to 2023 and not a significantly up year overall and stocks have to get in line with that thought.
About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.
