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proteanTecs at the 2024 Design Automation Conference

proteanTecs at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 4:00 pm

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Meet with proteanTecs at DAC. Explore our full set of health and performance monitoring solutions. We’ll be showcasing our latest products and solutions, and we’d love to connect while you’re there. Visit booth #2417 to explore our health and performance monitoring solutions.

Also – Don’t miss out on our daily sessions in our in-booth theater, featuring guest speakers from top companies in ASIC, design, IP, services, cloud, and proteanTecs.

We are also accepting booking for a private session in our meeting room, presenting new solutions and features tailored to your needs

proteanTecs offers a first-of-its-kind, in-system self-monitoring solution. With machine learning, we unlock deep insights increasing reliability, optimizing power, and enhancing quality.

During the show, we will be presenting multiple solutions, including:

  1. Power and Performance
  2. Reliability, Availability, Serviceability
  3. Functional Safety & Diagnostics
  4. Product Bring-Up
  5. Operations & Quality
  6. Die-to-Die Interconnect
Meet us at Booth 2417, 2nd floor

See the full booth agenda, and book a meeting at –

Meet proteanTecs at DAC 2024

About proteanTecs

proteanTecs is the leading provider of deep data analytics for advanced electronics monitoring. Trusted by global leaders in the datacenter, automotive, communications and mobile markets, the company provides system health and performance monitoring, from production to the field.  By applying machine learning to novel data created by on-chip monitors, the company’s deep data analytics solutions deliver unparalleled visibility and actionable insights—leading to new levels of quality and reliability. The company is headquartered in Israel and has offices in the United States, India, South Korea and Taiwan. For more information, visit www.proteanTecs.com.

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Sigasi at the 2024 Design Automation Conference

Sigasi at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 2:00 pm

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Sigasi® will demonstrate its Sigasi Visual HDL™ (SVH™) portfolio during DAC, showing how it supports the shift-left methodology for chip design, catching specification errors early in the design cycle and fixing the inefficient HDL-based design flow.

The traditional HDL workflow cannot accommodate the massive amounts of design specifications from GenAI creations, high-level synthesis results, and other complex SoC IP. These new levels of abstraction need to plug and play alongside large HDL files—that contain functionality created with domain-specific knowledge—to integrate hundreds of billions of transistors on a chip.

The comprehensive Sigasi Visual HDL portfolio is an HDL platform able to take advantage of the shift-left methodology and give hardware designers and verification engineers better insight during the design progress. They can easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. SVH does so by standardizing the concept of an HDL design project, bringing simulation and synthesis projects into a world of integrated development, synchronous visualization, and shift-left validation.

Integrated Development: SVH is fully integrated with Microsoft’s Visual Studio Code (VS Code), the most popular IDE, according to Stack Overflow’s 2019 survey, with a rich marketplace of productivity tools. It includes sophisticated applications to easily use git and GitHub Source Control Management, as well as a selection of utilities to facilitate mundane tasks like extracting TODO comments or bookmarking important sections in HDL code.

Synchronous Visualization: SVH lets users move seamlessly through hierarchy views and graphics that update instantaneously as they make changes in their code.

Shift-Left Validation: SVH flags problems while users enter HDL code. Starting with syntax and semantics, it enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches UVM abuses.

SVH comprises a tiered portfolio, offering three commercial editions meant to meet specific SoC design and verification challenges. The new offering also unveils Sigasi’s new AI chatbot, SAL, a chatbot that works with a local model or a remote OpenAI API and can generate, check, and explain HDL code. Each tier of SVH offers a comprehensive package of features, including type-time syntax and semantic checks and guardrails that enforce coding styles, policies, and standards. Regardless of which tier they use, engineers receive instant feedback and warnings for all files associated with a project.

Additionally, Sigasi offers a fully functional Community Edition that lets users explore its features for non-commercial uses, especially students and teachers learning and teaching the fundamentals of HDL design.

Sigasi will fly its new logo and tagline “Put Your Semicolons to Work” while exhibiting and demonstrating Sigasi Visual HDL at DAC Booth #2416 (second floor). DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

More details can be found on the Sigasi website or by emailing sales@sigasi.com.

To arrange a demo or private meeting to talk about Sigasi Visual HDL, send an e-mail to: dacmeeting@sigasi.com.

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Innova at the 2024 Design Automation Conference

Innova at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 12:00 pm

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Design projects are becoming more and more complex. The success of a design project is tightly linked to the best preparation. Having an accurate and precise prediction of either project design resources or design parameters, with a plan to react in an appropriate way is crucial and cost saving.

A typical example is the availability of licenses for all designers during experimentation and production. Either pre-synthesis which may require running parallel flows, each flow with needed licenses for restructuring a design, run several synthesis runs, etc. And also, post-synthesis when running tools with significant runtime such as simulation and placement and routing.

Having the possibility to define precisely the number of licenses, knowing peak usage and threshold, and predict the related period this will happen is key to negotiate contract with Vendors (we all know how much a license increment can cost). Same for the hardware resources, anticipate the period we will need additional resources, on cloud for example can lead to a different resource allocation strategy.

Innova leverage advanced artificial intelligence algorithms to provide a design environment and infrastructure to collect data, predict the expected resources, and predict also how design parameters may evolve given data from previous design projects.

For a particular SoC design flow, Innova’s prediction capabilities can even be applied as a “correlation dashboard” between design steps. This means that Innova PDM software can easily answer the question of how much the execution of a given design step would impact the result of a subsequent other design step.  In summary, Innova PDM’s advanced algorithms analyze historical project data to provide accurate predictions, enabling design teams to make informed decisions at each stage. This reduces the risk of unforeseen complications and ensures a smoother progression from one design step to another.

Innova brings also another dimension to the SoC design process and project, which is the eco-compliance of the entire design environment. Innova PDM gives to the user, the ability to start a new design project with a limited impact on ecology and better control on power consumption. Thanks to its qualification metrics of designs flows, design data and related compute resource configurations, Innova PDM helps filtering between different design flow options and possibilities through a unique eco-friendly score.

If you are a designer or a CAD manager, involved directly or indirectly in success decisions of complex design projects, visit the Innova booth (#1528, first floor) and hear about this new and unique automation solution whose customization capabilities will help anticipate needed resources for future projects.

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Defacto at the 2024 Design Automation Conference

Defacto at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 10:00 am

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Defacto continues to confirm its SoC Compiler as becoming the “de facto” SoC integration solution for large SoC designs. This year they are coming to DAC to share customer success stories of building the largest SoCs in the market from specification to RTL + collaterals such as UPF by including thousands of IP cores! All done within in less than an hour! It’s quite impressive to see this kind of results because with such short runtime, designers can afford to rerun several configurations in a single day!

Beyond RTL, SoC Compiler is now fully supporting all IP-XACT versions. In particular, even though their specialty remains RTL, they now offer full support for the IP-XACT format with joint management between the two formats. This joint management has enabled several major semiconductor companies to increase their use of the tool and test it on very complex designs.

This year, Defacto also closely collaborated with Arm to offer a joint and fully automated SoC generation solution. Indeed, if you have seen Arm’s latest announcements on their new IP configuration and SoC architecture description tool called IP Explorer, Defacto’s SoC Compiler tool is automatically plugged in order to generate Arm-based SoCs described by the user. In summary, this joint IP Explorer/SoC Compiler solution is the shortest path from defining ARM-based system architecture to implementation and design verification.

This year at DAC, Defacto is also promoting the ease of use of its solution, especially with its Python APIs. It’s true that today the use of Python is increasingly frequent, particularly among young engineers. Python also offers a wide range of advantages, such as: its very active community, ease of debugging, execution speed (compared to Tcl), and the vast number of available open-source libraries. Therefore, it can no longer be ignored in the use of EDA tools, and it is no longer possible to continue making Tcl and Python coexist in design flows knowing the heaviness of the process. Defacto made the choice two decades ago to build its software so that Python would be a built-in API, and today this allows many users to benefit from the power of this language. Defacto estimates that today more than 60% of its users switched to its Python API.

Last and not least, Defacto is revealing at this DAC and for the first time AI prediction capabilities with an opportunity for only few customers to start experimenting in 2024 unique capabilities and adding predictability to complex SoC design projects.

As a conclusion, Defacto’s solution has greatly progressed since last DAC, and this DAC looks promising if we consider these first announcements.

Defacto will be exhibiting at DAC, June 24-26 at first floor (booth #1528), Their technical experts will be present to provide more detailed product update. Make sur to contact them here (https://defactotech.com/contact)  to schedule a meeting at their booth. Hope to see you there!

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Codasip at the 2024 Design Automation Conference

Codasip at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 9:00 am

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Codasip will be demonstrating its new L110 core alongside Codasip Studio Fusion at #61DAC. Codasip L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market. ​The core offers extensive configurability, allowing different area/performance trade-off levels, and support for standard RISC V code-size extensions. Additionally, the L110 is fully customizable allowing designers to extend the processor to achieve massive PPA improvements to differentiate their products. Designed by the Codasip team using Codasip Studio Fusion, L110 is ideal for small-area, low-power applications, such as state machine replacements, sensor controllers, and IoT edge.

Codasip Studio has been the toolset to generate both the RTL and the software development tools from one processor model for years. The latest version, Codasip Studio Fusion, improves this fundamental capability and adds a layer of segmentation. You can configure the core from set options, create custom instructions within set bounds, or design freely.

Codasip will be showcasing both of these new products at the 2024 DAC show through the, Anomaly Detection in Near-Sensor Embedded Devices Demo. Which enables for AI/DSP on Tiny Processors optimized through Bounded Customization.

Codasip is a processor solutions company which uniquely helps developers to differentiate their products. We are Europe’s leading RISC-V company with a global presence. Billions of chips already use our technology.

In today’s technology market, differentiation is everything. The difference between success and failure. And, in chip design, this difference is quite literally wafer thin. With increasing transistor costs, your developers can no longer rely on semiconductor scaling and legacy processors to achieve your goals. The only way forward is to implement custom compute with designs tailored to your applications.

We deliver custom compute through the combination of the open RISC-V ISA, RISC-V ISA processor design automation and high-quality processor IP. Our innovative approach lets you easily customize and differentiate your designs. You can develop high-performing, and game-changing products that are truly transformational.

Unlike traditional design approaches, our custom compute enables you to take control of your destiny. We allow you to set free your creativity and to use your ingenuity. We’re at the leading edge of a transformation in processor design, providing our partners, the most innovative companies on the planet, with a proven alternative to the norm.

At Codasip, we enable you to design different.

It’s time to take the leap.

Architect your ambition.

See you at DAC!

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Siemens Hardware-Assisted Verification at the 2024 Design Automation Conference

Siemens Hardware-Assisted Verification at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 8:00 am

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Visitors to Siemens’ booth (#2521) at the 61st Design Automation Conference (DAC) will see on display the Veloce™ CS system that unifies hardware emulation, enterprise prototyping and software prototyping into one hardware-assisted verification and validation platform.

The display will feature the three single-blade system designed for engineering teams to add scalability and capacity as needed: Veloce Strato CS for emulation, Veloce Primo CS for enterprise prototyping, and Veloce proFPGA CS for software prototyping.

The evolution of SoC and system level design made the use of hardware-assisted verification a necessity, an opportunity Siemens embraced. It worked with key customers and partners to develop Veloce CS’ new, fully unified software architecture and innovative hardware built on two highly advanced ICs –– Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC for enterprise and software prototyping.

Architected for congruency, speed, and modularity across all three platforms, the Veloce CS system supports design sizes from 40 million gates up to designs integrating more than 40+ billion gates. Veloce CS executes full system workloads with superior visibility and congruency by selecting the right tool for the task, as each task has unique requirements. The result is faster time to project completion and assists in decreasing cost per verification cycle.

Veloce CS system addresses the specific needs of hardware, software and system engineers who play an essential part in delivering the world’s most advanced electronic products by providing the right tool for the task:

  • Veloce Strato CS delivers significant emulation performance improvement over Veloce Strato, up to 5x maintaining full visibility and it scales from 40 million gates (MG) to 40+ billion gates (BG).
  • Veloce Primo CS, based on AMD’s latest Versal Premium VP1902 FPGA, a congruent enterprise prototyping system that scales from 40MG to 40+BG.

Both the Veloce Strato CS and Veloce Primo CS solutions run on the same operating system for congruency while providing the freedom to seamlessly move between platforms. This can dramatically accelerate ramp up, setup time, debug, and workload execution.

  • Veloce proFPGA CS also leverages the AMD Versal Premium VP1902 FPGA-based adaptive SoC, which delivers a fast and comprehensive software prototyping solution, scaling from one FPGA to hundreds. This performance, together with its flexible and modular design, can help engineers accelerate firmware, operating system, application development and system integration tasks.

The entire Veloce CS system is available in a modular blade configuration fully compliant with modern datacenter requirements for easy installation, low power, superior cooling, and compact footprints. Further, the Veloce proFPGA CS solution provides a desktop lab version for additional user flexibility.

General availability of the three hardware platforms is planned for < >2024. Pricing is available upon request. For more information, visit the Siemens website. To arrange a demonstration or private meeting at DAC, send email to

DAC registration is open.

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Verific at the 2024 Design Automation Conference

Verific at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 6:00 am

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Verific Design Automation will host two well-funded AI EDA startups and latest users of Verific’s front-end platform in its Design Automation Conference (DAC) booth, affirming its position as the leading provider of front-end platforms powering an emerging market.

Primis.ai and Silimate, both founded by former chip designers, will be in the Verific AI showcase in booth #1414 presenting their unique use of AI technology to eliminate error-prone repetitive tasks for efficient and more productive chip design. They employ Verific’s unsurpassed language support for fast, accurate LLM development, speeding time to market for products that range from functional verification, chip design to code development.

PrimisAI offers a generative AI solution for chip design with advanced language-to-code and language-to-verification capabilities through its interactive AI assistant to address complex hardware challenges across the entire design stack from concept to bitstream/GDSII. RapidGPT, unveiled earlier this year, lets engineers interact with their design and the entire EDA ecosystem with a natural language interface, boosting productivity and accelerating time-to-market. Founded by serial entrepreneur Naveed Sherwani who serves as chairman and CEO, Primis.ai is backed by two early-stage investors.

Silimate, backed by Y Combinator, is building the co-pilot for chip designers to help build better chips faster. Silimate finds functional bugs, predicts power, performance and area (PPA) issues, and recommends real and accurate fixes in real time, and is already being used by chip teams building complex IP and SoCs. Co-founders Ann Wu and Akash Levy previously built chips and EDA tools at Apple, Stanford, NVIDIA, and Synopsys.

Metalware, co-founded by Ryan Chow and Andrew Nedea, is also an AI EDA startup employing Verific’s front-end parser platforms. With initial funding from Y Combinator, Metalware has the mission to accelerate embedded development using AI technology after personally experiencing repeated bottlenecks in embedded software at SpaceX. The Metalware AI EDA tools help designers rapidly write HDL and embedded C/C++ by combining insights from manuals, datasheets and code, offering 10x faster development by automating low-level programming.

Another AI EDA startup in stealth mode is also a new Verific customer that will be announced shortly.

PrimisAI and Silimate will be in the Verific DAC Booth #1414 at various times of the day to give 10-minute presentations. Stop by the booth for a listing of times.

Verific will also demonstrate the latest releases of its SystemVerilog, Verilog, VHDL and UPF front-end parser platforms.

Of course, this year’s giveaway will be the Verific Giraffe. Stop by to get one. To arrange a demonstration or private meeting, send email to info@verific.com

DAC registration is open.

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SmartDV at the 2024 Design Automation Conference

SmartDV at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 8:00 pm

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SmartDV’s presence at 61st DAC centers on connections, support, and the human side of IP. Over the past 18 months, we have been laser-focused on focused on overhauling and streamlining our customer support model to provide our global IP users with the best possible service. Vice President of Application Engineering Sergio Marchese has redoubled his AE team’s efforts to ensure that each user has the experience of a true partnership around their design success. This includes both customer-facing and internal improvements, such as:

  • Implementation of a customer success portal for improved ticketing, tracking, and responsiveness
  • Refinement of the product delivery process and related specification documents
  • Overhaul of the AE onboarding process to afford new members of our team a smoother, more efficient, and thoroughly supported path to getting up to speed and becoming successful in their roles
  • Strengthened lines of communication with our R&D team

We recently received the following generous feedback from longtime VIP user Ricoh, via a manager in their development department: “SmartDV’s strength lies in the individualized customization of VIP and the speed of their support. SmartDV has been flexible in responding to our requests for additional features and improving the readability of our development manuals. This is what differentiates SmartDV from other VIP vendors.”

We strive to offer exceptional support to each of our IP users, and ensuring that we hit the mark is our top priority. We can only achieve this goal through building strong relationships with our customers, taking on board their feedback, learning from our missteps, and challenging ourselves to consistently improve our processes. We’d love the opportunity to work with, and learn from, you and your team!

Whether you’re designing SoCs, ASICs, or FPGAs, SmartDV has design IP and VIP to suit your needs in the following categories:

  • Controllers, Peripherals, and Interface IP
  • Simulation VIP
  • Emulation/FPGA Transactor VIP
  • Formal Assertion VIP
  • Post-Silicon Validation VIP

We invite all IP enthusiasts to stop by our DAC booth (#2429) to share what you’re planning for your next chip design. We’d love the chance to investigate how we can be of service with our broad portfolio of design IP and VIP—and our ability to customize our offerings to meet your unique design needs. To give a nod to relationships and the human connection, you’ll have the chance to customize your own LEGO Minifig to look like yourself or anyone else of your choosing as you select hair, facial features, and other unique components. We’ll also have a giant LEGO wall where you can leave your mark as you chat with our team about upcoming design projects.

At SmartDV, we look forward to building things with you—at DAC and beyond.

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Blue Pearl Software at the 2024 Design Automation Conference

Blue Pearl Software at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 6:00 pm

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Twenty years ago, Blue Pearl showcased its first-generation ASIC and FPGA static verification solution at the 2004 Design Automation Conference. If you are attending DAC 2024, stop by booth 1439 and see how 20 years of product development on the Visual Verification Suite has made chip design much more efficient.

The Visual Verification Suite offers project level verification as you code, for ASIC, FPGA, and IP RTL with advanced RTL structural and formal linting and constraint generation. An optional integrated low-cost glitch, clock and reset domain crossing analysis package, complete with our Advanced Clock Environment providing visualization of clock domains to help designers set up and analyze designs for CDC/RDC caused metastability. The suite’s usability for bug hunting and fixing is proven to help design teams accelerate development while ensuring high reliability designs.

In addition, the suite’s Management Dashboard provides progress reports for audits and design reviews ensuring that all tests have been completed and passed prior to tape out and signoff.

What’s special with our latest release is that we have been partnering with Accellera to develop a standard format to capture CDC/RDC/Glitch intent and have our initial release with the new standard.

The challenge we are addressing is design teams cannot reuse IP-level CDC collateral in their environments if both teams use different CDC verification tools. This scenario is causing a CDC verification problem when the development teams source IP from IP providers that use a different tool for their own CDC verification. To perform holistic top-level verification, additional resources are needed to reconverge the IP with the verification tool used by the other team. Redoing IP-level CDC verification is time consuming and labor intensive.

The Accellera CDC working group’s objective is to develop a standard format to capture CDC/RDC/Glitch intent. This will enable interoperability of CDC collateral generated by different CDC verification tools. The working group is focused on the effort to produce a formal Language Reference Manual. Blue Pearl is actively engaged and adding new features to support this endeavor.

In addition, as an EDA tool provider that tailors to military, aerospace, medical, communications and safety critical design companies our Visual Verification Suite now supports Lattice and EFINIX FPGAs as well as AMD, Intel/Altera, Microchip and NanoXplore SAS FPGAs.

Finally, Adam Taylor a world recognized expert in design and development of embedded s system and FPGA’s , as well as CEO of Adiuvo Engineering and Training will in the BPS booth talking about his use of the Visual Verification Suite and the benefits to his team’s development efforts.

You can contact Blue Pearl here to schedule a meeting at booth #1439 or just stop by. We hope to see you there!

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Cycuity at the 2024 Design Automation Conference

Cycuity at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 2:00 pm

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Cycuity is looking forward to showcasing the latest updates and new capabilities of its Radix security technology at their booth this year, once again located near the DAC Pavilion. Radix offers a systematic and robust approach to hardware security verification, helping organizations identify and address security weaknesses early in the chip design lifecycle.

Cycuity’s security solutions accelerate detection of security weaknesses and deliver comprehensive security assurance through scalable, repeatable and traceable security verification from the beginning of chip design to delivery. The company’s proven methodology ensures security by design through a unique approach rooted in hardware security expertise.

With Radix, defining clear and measurable security requirements becomes a seamless process. This capability is crucial for creating a strong security foundation that can be monitored and verified systematically throughout the design process. Radix does this by simplifying the creation of security rules and ensures these rules are consistently applied and validated across chip design.

Radix’st in-depth security analysis capabilities enable visualization and exploration of every aspect of a chips’ design, providing unique insights into previously unknown or unexpected behaviors, allowing users to pinpoint security weaknesses and strengthen security measures.

Radix’s patented information flow technology tracks information about critical assets and attack surfaces throughout design at all times to identify weaknesses that could otherwise go undetected. Additionally, Radix’s security analytics quantify and verify the completeness of security test coverage, ensuring existing security measures are both effective and comprehensive, making it easier to demonstrate security rigor to customers and regulations.

Semiconductor security continues to be a growing and urgent focus across both commercial and government sectors, and Cycuity CEO, Andreas Kuehlmann, will be joining other industry security experts in the Advancing Chip Security to Meet Heightened Requirements panel discussion on Tuesday, June 25.  The panel will delve into how emerging standards and a growing threat landscape  are driving the necessity for enhanced cybersecurity measures across all industries.  Stop by to meet team Cycuity in Booth 2351 before or after the panel session.

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