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Semiconductor Expert Forum

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Pathfinding to an Optimal Chip/Package/Board Implementation

Pathfinding to an Optimal Chip/Package/Board Implementation
by Tom Dillinger on 02-04-2016 at 4:00 pm
Categories: EDA, Siemens EDA

A new term has entered the vernacular of electronic design engineering — pathfinding. The complexity of the functionality to be integrated and the myriad of chip, package, and board technologies available make the implementation decision a daunting task. Pathfinding refers to the method by which the design space of technology options is reduced to a viable solution, evaluating system parameters and goals against different technical alternatives. The increasing momentum in (2.5D/3D) packaging technology has added significantly to the choices available for implementing and interconnecting the functional design, making path finding a prerequisite to implementation.

Pathfinding is much more intricate than simply partitioning functions between chips. Partitioning algorithms generally seek to minimize some objective by clustering system functions with “high affinity” together into distinct subsets for physical implementation. Conversely, path finding requires exploring the impact of implementation decisions across disparate physical domains — it encompasses a much larger space of chip/package/board design considerations:

  • chip macro floorplan, redistribution layer (RDL) routing, and I/O bump patterns
  • optimal package fan-out trace patterns
  • interposer (or TSV) via and RDL design, for multichip packaging options
  • board routing complexity

All these options have a direct bearing on product cost, to be sure. These implementation decisions much also ultimately satisfy signal integrity, power integrity, and thermal reliability requirements, as well.

A major concern in enabling engineering teams to pathfinding is that the physical and electrical data for chip, package, and board reside in different data formats and unique representations. Making implementation decisions across these design domains requires a single, consistent view — resulting project edits and revisions require appropriate communication of ECO’s back to the original databases.

At the recent DesignCon 2016, I had an opportunity to meet John Park, Methodology Architect at Mentor Graphics, and learned how Mentor has addressed these difficult pathfinding issues in their recently announced Xpedition Package Integrator product. John emphasized that their approach was architected to utilize design data coming from various sources, and that the development team provided the interfaces necessary to incorporate the requisite information into Package Integrator.

In John’s words: “The approach we followed had to be EDA neutral.”

All system connectivity is maintained within Package Integrator, while designers are pursuing their path finding optimizations, as highlighted in the figure below.


A key design data interface into Package Integrator provides a Virtual Die Model, an abstract of the detailed chip layout data suitable for pathfinding. For existing die, a simple abstract of area + pad array + pin name data will suffice. Yet, initial pathfinding will involve chip designs that are still fluid. In these cases, the Virtual Die Model includes the additional data necessary to evaluate chip-interposer-package implementation decisions. As illustrated in the figure below, chip floor plan data — e.g., macro placements, blockages — are required with the die bump pattern. Edits to the floor plan, chip RDL, bumps, and/or package traces are enabled in Package Integrator, to provide visual feedback as to routing congestion (and thus, cost).


The figure below illustrates a specific example of using the Virtual Die Model to evaluate die and package implementation data in a single view. A die floor plan macro (in light blue) is depicted, with the corresponding bump pattern-to-BGA package ball placement and trace connectivity. Edits to the macro LEF placement are enabled, with any resulting proposed ECO’s maintained by the project management supervisor functionality within Package Integrator. These ECO’s can then be reviewed, approved and forwarded, or rejected.


These pathfinding edits must be rule-driven, to ensure a design requirement is not violated. For an example of a user-defined rule, John described the definition of a specific (+ve, -ve, IOVDD, GND) bump array configuration to be used for a differential signal — any edits to bump locations are verified to be consistent with the rules database. John also briefly highlighted examples of the pathfinding activity and rules checking associated with die-to-interposer via and bump assignment, as well.

A path finding solution requires a view of all domains, as illustrated in the die/package/board example below.


The connectivity flightlines between die, packages, and board-level connectors illustrate how congestion can be alleviated by path finding decisions on pin assignment and placement. Specific pin-to-pin routes can be applied. If routed traces are available, an interface to EM model generation and signal integrity analysis is also provided in Package Integrator. Utilizing thermal models for the individual die, a computational fluid dynamics (CFD) thermal analysis of the full system is enabled, as well.

The optimization of a product implementation across the physical boundaries of each die, (2.5D/3D) packages, and board requires a single view of the design data, with a corresponding connectivity model. This view must be agnostic to the source of the data, and must provide ECO project management. This complex co-design activity, aka pathfinding, must also support appropriate rules and constraints, verifying proposed edits within each domain.

Mentor Graphics has recently announced Xpedition Package Integrator to assist product architects and designers with the pathfinding task. They focused on developing data interfaces and model abstracts to be independent of the EDA source. They have successfully bridged the gap between the different physical domains, to enable key (and early) implementation optimizations.

-chipguy

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Here is what ‘‘Internet of Things’’ will do for Intelligent Transportation

Here is what ‘‘Internet of Things’’ will do for Intelligent Transportation
by Raj Kosaraju on 02-04-2016 at 12:00 pm
Categories: Automotive, IoT

Transportation sector is growing, and we can already see that a fleet of autonomous, shared vehicles – connected to the road infrastructure, to the Internet and to a broader network of public transit options – will create incredible value. The transport sector is trying its level best to improve the safety, reliability, and cost of transportation. And, there is no doubt that if they are provided with better information and connectivity, they will do lot more.


It has made one thing very clear and that is the more, the smart devices are used in the transport, the lesser traffic, parking and vehicles issues are likely to take place. This is where Internet of Things sounds helpful. It has not only taken the lead in the healthcare and automobile sector, but has also left a big impact on the transport. The internet of everything (IoE) promises to disrupt every aspect of our lives and the Transportation experience is no exception. Internet of Things enabled devices equipped with sensors are highly used in the transport sector.

However, the system is down right scary as it exists today! In 2015 DOT officials emphasize on the reports that we need to spend $120 billion on highways and bridges between 2015 and 2020, while spending at all levels of government is just $83 billion; we need $43 billion for public transit, while it’s currently at a dismal $17 billion. Today, our road system scores a mere “D+” grade when compared to the rest of the world. ( Beyond Traffic: The Blue Paper, Feb 2015)

1) Creating Rapid Strides
A whole new world is coming our way. Technology is allowing us to reimagine our future transportation system. It’s hard to be precise, but I think we’ll be cycling and walking more; in crowded urban areas we may see travellators – which we see in airports already – and more two-wheelers and scooters. It’s not difficult to predict how our transport infrastructure will look in 25 years’ time – it can take decades to construct a high-speed rail line or a motorway, so we know now what’s in store. Advances in connected automation, navigation, communication, robotics, and smart cities—coupled with a surge in transportation-related data—will dramatically change how we travel and deliver goods and services. Automation in the field of transportation is everywhere. We are going to see a LOT of multi-level, roads and highways in the near future.

2) How IoT will affect traffic technology over the next 10-20 years
For the most part transportation will be a thing of the past, with most people working at home. Smart connectivity with existing networks and context-aware computation using network resources is an indispensable part of IoT. With the growing presence of WiFi and 4G-LTE wireless Internet access, the evolution towards ubiquitous information and communication networks is already evident. Moreover individual vehicles, freight, and public transport can all be improved by online information and communication between drivers and a central information hub.

Intelligent Transport systems for buses, trains, and passengers themselves will combine to make traveling easier and less stressful. One of the ways IoT can benefit the UK is “Intelligent Transport Systems” (ITS). And it is noteworthy to be mentioned about Ofcom. Ofcom’s vision is a world where cars communicate with each other, making traveling from A to B “smoother and safer.” It is assumed these systems could be in place in the next 10-30 years. Many city centres in Europe are banning the private car. So, there are now and will be more places that are free of traffic. Mobility – the speed and directness of travel – and the density of activities are the two determinants of a city’s accessibility and thus economic vitality. Moving people faster and more directly in order to expand accessibility should be the primary mission of transport agencies.

3) To make Routes Safer and Transport more Reliable
They can make transport safer, more efficient and more sustainable by applying various information and communication technologies to all modes of passenger and freight transport. Moreover, the integration of existing technologies can create new services. ITS are key to support jobs and growth in the transport sector. But in order to be effective, the roll-out of ITS needs to be coherent and properly coordinated across the EU. It also mentions less air and noise pollution as a result – even talking about traffic free zones in cities. There are companies that mention the technology could help cars take the shortest possible route, thereby reducing CO2 emissions. It could even warn drivers about school zones to avoid going into busy areas with lots of children, and even cooperate with pedestrians’ mobile phones to alert drivers and help them navigate fewer hazards. Today, drivers themselves react to transport systems: warning signs on bridges, real-time information on digital alert boards.

4) Seeking Assistance from the Cloud
Transportation is an enormous issue for cities in regards to commerce, environmental impact, and quality of life. Within transportation, parking is an issue that affects everyone – from drivers to merchants, to city governments. Both transportation and parking are quickly gaining traction as key priorities for cities as metropolitan area populations continue to increase and cities examine how to leverage technology to make their communities more liveable. There are already several apps that help drivers find parking spaces. But imagine a car that could identify an empty parking space as it passes by and then upload that information to the cloud. New and existing apps could then use the real-time data to improve alerts to drivers about open spaces nearby.

This new functionality could also help eliminate the time and resources we waste parking our cars. This is where vehicles and roadside units communicate through nodes in order to provide each other with information, such as safety warnings and traffic information. The information is then applied to solutions that can be utilized by road users such as red light warnings, automatic tolling, and routing and navigation information. The wants to change the way people live through parking, a universal challenge that’s seen little innovation in years. There are several companies which are helping cities utilize Smart Parking technology to realize the benefits of smarter transportation, including reduced traffic and emissions, more vibrant local economies, and better quality of life for citizens.

In closing,
Over the next few years, we see Internet of Things becoming an integral part of our lives, whether it is through Smart homes, Smart cars, Transportation or smart health care. It’s clear that the IoT will disrupt most industries. The transportation systems around which the modern world has been built are on the verge of a significant transformation. Intelligent transportation systems (ITS) are making driving and traffic management better and safer for everyone. New technology for on-road communications will dramatically change how vehicles operate and provide information and capabilities for better, real-time traffic management — if the necessary network infrastructure is in place.

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Cadence Adds New Dimension to SoC Test Solution

Cadence Adds New Dimension to SoC Test Solution
by Pawan Fangaria on 02-04-2016 at 7:00 am
Categories: Cadence, EDA

It requires lateral thinking in bringing new innovation into conventional solutions to age-old hard problems. While the core logic design has evolved adding multiple functionalities onto a chip, now called SoC, the structural composition of DFT (Design for Testability) has remained more or less same based on XOR-based compression since long. Increasing SoC design sizes are pushing up increased test logic, tester time and test resources, thus increasing the test cost to the tune of billions of dollars. Alternatives to reduce such high test costs are awaited since long.

Typically shorter scan chains require lesser number of clock cycles to shift test bits and thus reduce test time, but that leads to far increased number of scan chains compared to the number of scan pins. This requires decompression logic between scan-in pins and the scan chains and at the other end compression logic between scan chains and scan-out pins; also the connections between scan chains and compression/decompression logic consumes significant routing resources. Increase in compression ratio (i.e. number of scan chains to number of scan pins) increases compression/decompression logic impacting the die size and routing resources. Also, higher compression ratio beyond certain limit can no more reduce the test time and can adversely impact on test coverage too.

Although about 100x compression ratio is seen optimal with current XOR architecture of compression logic, it consumes a significant ~4% of total chip routing; that increases to 10% if compression ratio is increased to 400x which outweighs the saving in test cost. Do we have alternatives to achieve higher compression ratio yet consume lesser routing resource and achieve higher test coverage?

Here comes Cadencewith its new Modus[SUP]TM[/SUP] Test Solutionwith physically aware 2D Elastic Compression architecture integrated into Cadence digital flow. This innovative solution has several patents pending.


The Modus Test Solution is integrated with Cadence’s Genus[SUP]TM[/SUP]Physical Synthesis, Innovus[SUP]TM[/SUP]P&R system, and Tempus[SUP]TM[/SUP]Timing Signoff solution in a common environment to provide a seamless flow for digital designs which can achieve up to 2.6x lesser routing for compression logic and up to 3x lesser test time with the new 2D elastic compression technology compared to conventional 1D XOR-based compression logic.

To know more details about this new dimension in test compression, I had a nice opportunity talking to Paul Cunningham, VP R&D at Cadence, responsible for front-end digital design solution; earlier Paul was co-founder and CEO of Azuro which was acquired by Cadence in 2011.

In the 2D compression architecture, the compression logic forms a 2D grid across the chip. This allows the routing between the compression logic and the scan chains to be distributed evenly on the grid, thus requiring lesser wire lengths. With 2D compression, various types of designs including CPU, GPU, Networking, DSP and Automotive chips in the range of 1.3 to 2.5 million instances require same wire length at 400x compression ratio as compared to that at 100x compression ratio with traditional 1D XOR compression.


Another innovation added to the compression technology is to add elasticity by embedding registers and feedback loops in the decompression logic. This allows controlling care bits sequentially across multiple scan cycles during ATPG (Automatic Test Pattern Generation), thus maintaining fault coverage at high levels. With 2D elastic compression, compression ratios beyond 400x can be easily achieved without loss of fault coverage. And test time can be reduced by up to 3x compared to that with traditional 1D XOR compression. The designs discussed above have shown test time saving in the range of 1.6x to 3.6x, all with fault coverage > 99%; a little more than that achieved with 1D XOR compression.

Also, the Modus Test Solution allows automatic insertion of a single shared test access bus to enable one MBIST controller to service multiple memories, thus separating CPU for higher performance.

Cadence Modus Test Solution provides complete test features for scan, MBIST, logic BIST, ATPG, and self diagnostics in a common environment with synthesis, implementation, and timing signoff including debugging and scripting.

This new innovation in test solution for SoCs is a solid opportunity for Cadence to improve their market share in test automation business, currently dominated by Mentor’s TestKompress. There are good customer endorsements on this technology which can be seen in Cadence’s press release on Modus Test Solution HERE.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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Updated tool cuts through DO-254 V&V chaos

Updated tool cuts through DO-254 V&V chaos
by Don Dingee on 02-03-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA

Audits. The mere mention of the word keeps project managers up at night and sends most designers running. However, in the case of FPGA designs seeking DO-254 compliance, the product doesn’t ship until the audit is complete – there is no avoiding it, or skating around it. Continue reading “Updated tool cuts through DO-254 V&V chaos”

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Expanding 3D EM Simulation Access to All

Expanding 3D EM Simulation Access to All
by Tom Dillinger on 02-03-2016 at 7:00 am
Categories: Cadence, EDA

James Clerk Maxwell’s eponymous equations are the basis for simulating electromagnetic wave propagation. In school, EE majors tended to fall into two camps: (a) those that thoroughly enjoyed their fields and waves classes, who liked doing surface integrals, and who were adept at demonstrating the “right hand rule”, and (b) those that took the required courses but quickly focused on other disciplines within the expansive breadth of the electrical engineering field.

At the recent DesignCon 2016 conference, Brad Brim, Product Engineering Architect at Cadence’s Sigrity group, gave an enlightening presentation that focused on bridging the gap between these two groups, entitled: Access to 3D EM Simulation — for those who care and those who couldn’t care less.

Brad began with a brief history of 3D EM simulation technology — from the solver algorithms used, to the simplifying material and model assumptions of Maxwell’s wave propagation theory that enable the speedups of static and quasi-static modes. The figure below summarizes this chronology.


Specifically for the DesignCon audience, Brad highlighted how EM simulation has evolved from the domain of RF antenna design to become a fundamental tool in the analysis of package and PCB designs. A complete “hybrid” system analysis approach combining EM and circuit simulation models was emphasized, whether for the voltage/timing margin “eye diagram“ analysis of signal interfaces (SI) or comprehensive power distribution network analysis (PI).


Yet, how does an engineering organization bridge the knowledge gap highlighted above, between EM experts and the (much larger) design teams that need the EM simulation results?

Brad presented his vision for the methodology to enable design teams to have access to the simulation technology required for analysis of a complex system model. The approach has two fundamental tenets:

  • The EM experts and the package/PCB designers need to work from a common physical layout database.

Although this may seem obvious, it is not uncommon for an EM expert to prepare a model independently, in a separate tool environment. Material stack-ups, via arrays, representative trace topology, power distribution planes, etc., are uniquely drawn and analyzed, and offered to the design community at large as design constraints (to verify in a constraint checker) and/or as recommended design library cells.

  • The approach to generating detailed EM simulation S-parameter results initially utilizes the EM expert to define the geometric “cut points” in the design. Then, with this initial setup, the design team can directly launch EM simulation, and thus, more efficiently iterate on model analysis, minimizing the resource demand on the EM expert.

These cuts define the “ports” for EM simulation and S-parameter model generation. Individual models are then stitched together as part of the system model. The figures below illustrate how a cut-and-stitch model definition is created, and an example of how EM simulation would be invoked directly from within the Cadence Allegro Sigrity environment.

Is the “cut-and-stitch” method for model generation sufficiently accurate?

Brad presented several examples demonstrating the accuracy of the overall system results and the speedup relative to attempting a single EM model analysis (which would be infeasible on large designs, regardless). The figure below shows an example of the S(1,n) set of model S-parameters for the cut-and-stitch approach, compared to an analysis of a full model.


EM simulation technology must become more accessible to a wider cross-section of the design community. The insights of EM experts are used to assist with model and simulation setup, yet the analysis results and optimization decisions are most efficiently led by the design teams. A common physical database accessible to all is a prerequisite.

The Cadence Sigrity team is enabling this trend, with a defined methodology for model partitioning and simulation, all within their tool platform. As Brad succinctly summarized the Sigrity approach toward enabling EM simulation for design teams, “It’s time to put the A back in EDA.”😀

More information on the Cadence Sigrity “cut-and-stitch” EM simulation methodology is available HERE.

-chipguy

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Submerging the Data Center

Submerging the Data Center
by Eric Esteve on 02-02-2016 at 4:00 pm
Categories: IP, NetSpeed Systems

One of NetSpeed’s customers is a Tier-1 semiconductor company that develops some of the industry’s best performing and most complex system on chips (SoC) for the data center and cloud computing markets. To keep its leadership in the data center market, the company needs to produce best-in-class SoC solutions year after year. Today, NetSpeed’s Network-on-Chip (NoC) is at the heart of these super-SoCs.

The main challenge for the data center market can be summed up in a few words: offering 60% more bandwidth every year while decreasing the latency. Adding more servers can’t be the only solution because that would severely impact latency. Even if existing designs achieve best-in-class latency, future SoC generations will require even lower latency. Moreover, with in-memory computing replacing previously used storage solutions like hard disk drives, traditional latencies have to be greatly reduced to enable real-time, data-driven decision making.

This customer used to hand-tune interconnect designs and it was severely impacting the design and verification schedule and requiring chip architecture iterations, as the methodology for deadlock discovery, analysis and resolution added an extra 6 months to the development schedule. Therefore, a solution that was guaranteed to be deadlock-free could save up to 6 months of development time and generate a huge time to market advantage.

Not all interconnects (or NoCs) are created equal. NetSpeed provided an interconnect synthesis engine, an innovative solution that optimizes the interconnect architecture based on workload models. Implementation of NetSpeed’s NoC led to a new generation SoC that delivers 25% lower latency and 29% higher maximum frequency than previous ICs. Because NetSpeed synthesizes a pre-verified interconnect design within minutes, the direct impact on design schedule is to shrink six months of analysis down to a few hours.

Data center dedicated SoCs are known to be the best-performing ICs on the market. NetSpeed’s NoCs enabled a new generation SoC that delivers 25% lower latency and 29% higher maximum frequency than previous ICs.But the SoC optimization effort to reduce both area and power consumption has to be pushed to the maximum in order to create a power conscious solution leading to an economically viable chip size.

Both power consumption and area are directly impacted by the number of wires and buffers in the SoC interconnect. NetSpeed’s interconnects can be optimized to reduce the number of wires and buffers. This created an SoC design that offers higher performance than previous generations while reducing area by 40%, wire count by 26%, and buffer count by 46%.

Using NetSpeed’ NoC solution is probably not enough to magically solve the data center power consumption issue forever. Offering 40% lower power than previous generation is already a great achievement and saving 6 months on the SoC design schedule can allow reassigning creative and experienced people like SoC architects and designers to other tasks. For example, they could rework and optimize the architecture of the data center itself to create future storage and processing units that could become so power friendly that you don’t need to submerge the data center…

This blog is extracted from NetSpeed “Data Center” Success Stories. You can read more about this story and Mobile AP, Automotive SoC, Networking, Digital Home SoC or Data Center Storage stories here

From Eric Esteve from IPNEST

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Keeping an ‘Open’ Mind with Technology

Keeping an ‘Open’ Mind with Technology
by Pranay Prakash on 02-02-2016 at 7:00 am
Categories: IoT

Software and hardware vendors are developing proprietary products and technologies to tap into the massive potential business opportunity with Internet of Things (IoT). While most of the noise is around consumer driven IoT, commercial applications for IoT are making huge financial impact in many verticals. Buildings alone account for 40% of world’s energy consumption – extrapolate this with number of disparate devices at a smart city level and this becomes gigantic.


A smart city project might include connectivity of homes, soda machines, parking lots, commercial buildings, security cameras, traffic systems etc, it is impractical to think that the infrastructure and devices across the city will be homogeneous. This really is a multi-vendor, multi-protocol and big data play and will require software and hardware platform technologies that are ‘Open’ and able to integrate disparate devices and deliver analytics and control over remote devices.

As IoT is gaining momentum there are startups and established companies entering the IoT arena with new platform technologies. While having more options for products and services can be good, it can also be confusing and can make it very difficult to select the right technology needed to build a strong IoT solution. If you know your IoT goals, selecting the right foundational platform technology is very important. You will need to keep an ‘open’ mind and look for some of the following tenets:

Open Technology
Open IoT platform technologies can help you normalize data from legacy proprietary and new edge devices, build applications and integrate with 3rd party systems as and when you need without having to replace the platform or infrastructure. APIs play a critical role here – look for published open APIs for your developers. Even Microsoft has announced support for open technologies such as supporting Linux Operating System or Cloud Foundry Platform as a Service (PaaS) on its Azure platform.

Stable Technology
If you have the choice, besides evaluating pros and cons of existing vs new platforms in your labs, evaluate established “real” IoT operational case studies. See how long these systems have been running and how customers have benefited over multiple years. IoT systems should be designed for prolonged and sustained benefits.

Robust Eco-System
With Android and iOS, we all know the power of an application ecosystem. You want to be able to have choice. Select a platform that has a developer community around the technology. If you have the developer mindshare, your customers will be able to access cool applications for their operational use.


Scalable Technology
Although scalability depends on your business needs, I recommend selecting a platform that can scale from the edge to the cloud. Learning, managing and developing applications on multiple platforms is hard and cost-prohibitive. If your business serves a large and complex IoT infrastructure, you should plan for the millions of devices that are going to get connected to the web over the next several years.

I hope the above is useful in your IoT journey. I would love to hear how you are using or considering open technologies for IoT or otherwise. If you are not, I am sure there is a reason and it will be great for readers to learn why.

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Smartphone-based Connected Health Insights from Patents

Smartphone-based Connected Health Insights from Patents
by Alex G. Lee on 02-01-2016 at 4:00 pm
Categories: Mobile

US20150124067 illustrates an improved technique for monitoring human health vitals without contact using the physiological signals extracted from video images captured by a video camera of a smartphone. One advantage of the contact-less vitals monitoring technique is the avoidance of contact measurement which can be a problem for infants and the elderly who need monitoring for a long period of time.

The contact-less vitals monitoring technique uses the photoplethysmographic (PPG) method. The PPG uses the optical signals (related to cardiac signal and respiratory signal) transmitted through or reflected by a person’s blood, e.g., arterial blood or perfused tissue, for monitoring a physiological parameter of the person. The smartphone can adjust the illuminator of the video camera with respect to intensity, spectrally, spatially, and/or temporally to improve the level of accuracy of the measurement. The smartphone processes the captured video images to extract a time-series signal. The smartphone extracts the physiological signals from the time-series signal. The smartphone can transmit the measurement results to the remote healthcare practitioners for further analysis and assistant.

US20150351698 illustrates a system for analyzing physiological and health data (e.g., activity data) retrieved from wearable monitors using a smartphone to identify emergencies or medically significant events in real-time. The system retrieves the physiological and health parameter data in real-time from the physiological and health monitors associated with a user. The physiological parameter data includes values of a physiological parameter of the user measured in real-time. The health parameter data includes values of the health parameter of the user measured in real-time.

The user smartphone analyzes the received physiological parameter data in real-time to identify a medical event associated with the user. The analysis of the received physiological parameter data includes determining that the physiological parameter data includes values that are outside of a normal range for the physiological parameter and that the medical event corresponds to a period of time in which the physiological parameter values remain outside the normal range. The user smartphone also analyzes the received health parameter data in real-time over a specified time period and generates a health level for the user based on the health data over a pre-determined period of time. The system generates medical notifications corresponding to the identified medical event and generated health level in real-time. The generated health level is transmitted by smartphone to an emergency response system when the identified medical event is an emergency medical event.

US20150335272 illustrates a system for reliably testing, monitoring and predicting blood sugar concentration (e.g., glucose) for a user. The system includes a user-wearable devices including storage for glucose testing strips, a spring-loaded lancet, a strip reader, a display, an activity sensor (e.g., accelerometer). The user-wearable devices collects and stores the blood glucose level based upon a test strip reading along with activity level of the user. The user-wearable devices transmit the data regarding the blood glucose level and activity level to the user smartphone for calculating a predicted blood glucose level for the user. The smartphone can provide the user with information illustrating how well the user has managed his/her own blood sugar concentration during a prior period of time based on the predicted blood glucose level for the user.


More articles from Alex…

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HSPICE – 35 and looking good!

HSPICE – 35 and looking good!
by Tom Dillinger on 02-01-2016 at 12:00 pm
Categories: EDA, Synopsys

A maturetool. A legacytool. A tool that’s a little long in the tooth. We have all used these terms to refer to an EDA product that has not been able to keep up with technical challenges of model complexity, performance, or new features required by current SoC and system design requirements.
Continue reading “HSPICE – 35 and looking good!”