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Sleep Monitoring and Aiding Devices Insight from Patents

Sleep Monitoring and Aiding Devices Insight from Patents
by Alex G. Lee on 02-08-2016 at 12:00 pm

US9192326 illustrates a sleep monitoring system that can be embodied within a wearable device or in a mobile device. The system includes an accelerometer to monitor a user’s movements. The system determines when the user is falling asleep into a sleep session based on the user’s movements. The system also identifies the sleep session as a power nap or a longer sleep based on a current time of day, a time since a last longer sleep, and a location of the user. The system notifies the user to change the user’s location when the user falling asleep would have a negative effect on the user.

When the user falling asleep does not have a negative effect on the user, the system determines a time to wake up the user based on a combination of the current time of day, the time since a last longer sleep, the location of the user, user preferences, and measured information regarding the sleep session.

US20150182164 illustrates a sleep monitoring system that can be embodied within a wearable ring (e.g., on a digit of a hand and/or a toe of a foot). The system includes the biometric sensors comprise a heart rate sensor, a respiration sensor, a temperature sensor, a skin conductance sensor, a skin conductance response sensor, a galvanic skin response (GSR) sensor, an electromyography (EMG) sensor, an electrodermal activity sensor, and an electrodermal response sensor.

The biometric sensors generate biometric signals such as an arousal signal indicative of arousal in a sympathetic nervous system. The system analyzes the biometric signals to classify a user’s sleep state as several sleep types. The system notifies the user regarding the sleep state that is an indication of the negative health status (e.g., inflammation, fatigue, stress). The system provides a coaching that includes advising or offering suggestions to the user for changing behavior or to improve some aspect of the wellbeing of the user.

US20150351693 illustrates a sleep monitoring system that can be embodied within a bed or a mattress. The system includes pressure sensors that are spatially arranged in a predefined planar geometry. The system extracts the biophysical variables from the biophysical signals of a user resting on a bead or mattress that are obtained by the sensors. The person’s sleep state is inferred from the biophysical variables.

A good life quality is usually built up with the good sleep quality. Unfortunately, according to the research findings, about 11.7% of Americans (i.e. about 32 million people) suffer from the problem of sleeplessness. US20150217082 illustrates a sleep aiding system for assisting in easing hardship of falling asleep. The system monitors a bio-condition of the sleeper to collect bioinformation of the sleeper. The bioinformation includes a heartbeat, a body temperature, a blood pressure, a skin conductivity, and a respiration rate. The system determines a falling-asleep hardship index based on the received data to indicate hardship of falling asleep for a user. The system provides the sleep guidance in visual form audio form to adjust the environment for building an optimum sleep environment.

US20140316192 illustrates a virtual reality system for promoting sleep. The system includes a virtual reality device and a wearable or mobile sensor device. The sensor device communicates wirelessly with the virtual reality device (e.g., eye wear and headphones). The sensor device detects various different physiological signals and determines the physiological parameters. The sensor device determines a stage of the immersive virtual environment based on the values of the physiological parameters. The virtual reality device presents the stages of the immersive virtual environment that are designed to promote sleep by providing a different arrangement of sensory stimuli.

More articles from Alex…


Complexity And Security

Complexity And Security
by Bernard Murphy on 02-08-2016 at 7:00 am

From time to time when talking about security, it is useful to look at the big picture, but not to further lament the imminent collapse of the sky. We all know that the problem is big and we’re really not on top of it. A more productive discussion would be about what we can do to reduce the scope of the problem. And that has to start with a more scientific approach driving first-principle ideas for improvement. My thanks to @ippisi who pointed me at langsec.org which is a fascinating resource for anyone interested in fundamental work in improving software security (and perhaps ultimately hardware security since hardware is not so different from software).

The Growth of Complexity
Here I’ll just concentrate on one aspect – complexity – and I take a lot of insights from the keynote at langsec.org last year, with a few of my own thoughts thrown in. Complexity can be quantified but to avoid getting mathematical, I’ll rely on an intuitive sense. As systems grow in size, complexity inevitably grows also. Even if the system growth is just replication of simpler systems, those systems have to intercommunicate, which leads to more complexity, especially in the Internet of Things (IoT). Then we add still more complexity to manage power consumption, different modes of communication and, paradoxically, security.

The level of complexity is important because it limits our ability to fully understand system behavior and therefore our ability to protect against attacks. And that points to a real concern: that the complexity of the systems we are building or planning to build is fast out-stripping our ability to fully understand them, much less protect them.

Consider first just the classical Internet (forget about the IoT). Dan Geer, the langsec 2015 keynote speaker, found in researching an article that we are having increasing problems bounding or discovering what the Internet actually is. It seems many reachable hosts have no DNS entry, complete reachability testing in network trees became impossible a long time ago (the number of paths in a tree grows exponentially with tree size) and what we consider endpoints in end-to-end views of connectivity has anyway become quite unclear in a world of virtual machines and software-defined networking. So the Internet, pre-IoT, has unknown complexity. Building out the IoT, I assume, would compound this problem.

OK you say, but at least I fully understand the system I designed. Exceptionally clever people could possibly have made this claim when software and hardware were created from scratch. But now design in both domains is dominated by reuse and that leads to dark content. Not dark in the sense of powered-down from time-to-time, but dark in the sense of never used, or you don’t know it’s there or if you do, you don’t know why, or what it does.

A non-trivial percentage of software may be dark, especially through legacy code but also through third-party code supporting features you don’t use, and also through code that no-one wants to remove because the person who wrote it left long ago and who knows what might break if you pull it out. Projects to understand and refactor this class of code get very low priority in deadline-driven design, so it stays in.

This problem applies as much to hardware as to software – lots of legacy logic you only partly understand and unknown code in boatloads of third party IP. Dark code amplifies complexity and indications (mentioned in the langsec keynote) are that it is growing fast. Forget about hidden malware – we don’t even know if innocent but untested (for your intended use) darkware harbors possible entry points for evil-doers.

Then there’s innate or architectural complexity – what you build when you create a significant function and when you put a lot of large functions together. We try to manage complexity through function hierarchies and defensive coding practices, which say that we should code for graceful handling of unexpected inputs and conditions.

But there are practical and subjectively-judged limits to how far any designer will take this practice. You defend against misbehaviors you think might be possible, and self-evidently not against behaviors you can’t imagine could happen (or you didn’t have time to imagine). And since it would be impractical to defend everywhere, you defend only at selected perimeters and assume within those perimeters that you can rely on expected behavior. But if any of those defenses are breached, all bets are off. These defenses limit complexity in a well-intended but rather ad-hoc (and therefore incomplete) manner.

The Effect of Complexity on Test
And then there is the issue of how we test these complex systems. For large systems it would be wildly impractical to test at every possible level of the functional hierarchy, so we test (or presume already well-tested) only at those levels for which we believe we understand expected behavior – the total system and some well-defined sub-functions. Our tests at the sub-function level, even with fuzzing or constrained random, probe only a small part of the possible state-space of those functions.

And at the system level we are limited to testing representative sets of use-cases, perhaps with a little randomization in highly constrained channels. We effectively abandon any hope of fully exploring the complexity of what we have built. Again this is becoming as much of a problem in hardware as it has been for years in software. Throughout systems, complexity is growing faster than our ability to understand and manage defenses against attacks on weak areas in behavior we don’t even know exist, much less understand.

How We Might Manage Complexity
So what can we do (at a fundamental level)? Formal is a de-facto answer (for both software and hardware) but is very limited since it explodes very quickly on large problems. Bounded proofs of constrained objectives are sometimes possible but only if multiple assumptions are made to limit the search space, which limits its value as a general solution to managing complexity.

An alternative is to constrain the grammar you use in design. As a sort of reduced version of Gödel/Turing’s reasoning, if you make a grammar’s expressive powers simple enough, you make it easier to use existing (e.g. formal) or comparable proof methods to fully prove properties (e.g. a statement about security) of a logic function in that language. There are preliminary efforts in this direction in reported in langsec.

Another more speculative though potentially less disruptive idea (my contribution, based on capabilities in the BugScope software we sold at Atrenta) is to focus on the observed (tested) behavior of function interfaces during normal behavior. You infer de-facto assertions from observed behavior and accumulate unions of these assertions – this integer interface was always less than 14, that interface was never active when this signal was 0, and so on. Then you embed those in the production software/hardware as triggers for out-of-bounds behavior, where the bounds are these observed/tested limits.

In use, if an assertion triggers, you don’t know that something bad is going to happen, but you do know the software/hardware is being exercised outside the bounds it was tested. This is effectively a tested-behavior fence – not foolproof by any means, but potentially higher coverage than even user-supplied assertions (which tend to be complex, difficult to create and therefore sparse in possible behaviors). In practice it would be necessary to adjust some of these bounds as continued use “proved” the relative safety of some out-of-bounds excursions, so there has to be a learning aspect to the approach.

In either approach darkware would either prove to be harmless (does not cause a proof to fail or behavior lies inside acceptable bounds) or will reveal itself through unexpected proof failures or unexpected bounds.

There are plenty of other methods suggested in langsec proceedings for managing/restricting complexity (for software). I heartily recommend you read Dan Geer’s keynote HERE and branch from there to the 2015 proceedings HERE. The keynote is full of interesting insights and speculations. For anyone with too much time on their hands, I wrote a blog last year about an way to develop a security metric for hardware based on the complexity of the hardware. You can read that HERE.

More articles by Bernard…


Automotive Deaths and Big Data

Automotive Deaths and Big Data
by Roger C. Lanctot on 02-07-2016 at 8:00 pm

Nothing focuses peoples’ attention quite as effectively as death and there’s been a lot of it on U.S. highways lately. Preliminary figures released this week by the National Highway Traffic Safety Administration (NHTSA) reveal that for the first nine months of 2015 traffic fatalities increased 9.3%.
Continue reading “Automotive Deaths and Big Data”


IP Vendor Nabs Top Talent from Semiconductor Industry

IP Vendor Nabs Top Talent from Semiconductor Industry
by Tom Simon on 02-07-2016 at 4:00 pm

The growth of mobile and IoT have helped increase the demand for One Time Programmable Non Volatile Memory (OTP NVM) as a solution for on-chip storage. To continue to meet this demand and grow with it, industry leading Sidense has recently brought on board seasoned semiconductor executive Ken Wagner as VP of Engineering. He was most recently at PMC as VP of Engineering for Communications Products. Also there in his role as Distinguished Engineer he led a number of initiatives, including low power and IP.

During his hectic first few weeks at Sidense I was able to speak with him about his background, his thoughts on the markets that Sidense addresses and the future. At PMC he was heavily involved as a consumer of chip level IP. He sees IP as a very interesting segment. It has evolved quite a bit over the years, not unlike EDA or the semiconductor segments. Initially there were many smaller players but IP, like the rest, has seen consolidation that has allowed larger players to emerge. He cites ARM as a good example of this phenomenon. As this has happened IP has become a much larger market.

Ken felt that Sidense has an excellent technology foundation and a strong customer base. This affords good opportunities for new products development. Ken was naturally a bit reluctant to get into specifics about their plans though.

In his opinion their OTP IP is world class and very secure. This is the kind of building block needed for some of the biggest and fastest growing markets, such as automotive, mobile and IoT. Automotive in particular is seeing new standards for security. OTP NVM is extremely useful in helping to fight hacking, a serious concern in the automotive market.

Another characteristic of the automotive market is that it is not always using the most advanced nodes. This is driven by reliability requirements that arise from the harsh environments found in automotive applications. In addition to older larger nodes, Sidense supports an extensive range of process nodes, including the most advanced nodes like FinFET.

We also spoke about potential alternatives to OTP NVM. Sidense provides a solution that offers very high density. Their solution does not require any additional mask layers, unlike NAND flash. So Ken believes OTP NVM will always be the best choice for small byte count storage needs.

Even so, OTP array sizes can be quite large, making it suitable for applications like boot code storage. This offers the highest security for trusted boot. Sidense OTP NVM can even be configured to emulate multiple writes, allowing for in field updates.

Ken pointed out that another critical Sidense competitive advantage is in write speeds. This saves time for configuring finished chips. He also mentioned that in addition to smaller memory arrays, Sidense has the most compact support logic and most flexible internal power supply options, eliminating the need for extra external power pins and additional power-net routing on chip.

In closing our conversation Ken said that he is excited for what lies ahead in his new position. Sidense is growing and there are many opportunities for additional growth ahead. For more information about Sidense’s OTP offering you can visit their website at www.sidense.com.


Synopsys’ New Circuit Simulation Environment Improves Productivity — for Free

Synopsys’ New Circuit Simulation Environment Improves Productivity — for Free
by Pawan Fangaria on 02-07-2016 at 12:00 pm

When technology advances, complexities increase and data size becomes unmanageable. Fresh thinking and a new environment for automation are needed to provide the required increase in productivity. Specifically in case of circuit simulation of advanced-node analog designs, where precision is paramount and a large number of simulations must be performed over multiple corners under different modes of operation and testbenches, one cannot rely on manual management through legacy scripts. Of course a designer’s expertise is most important in the case of analog design, but circuit simulation of these designs requires an intuitive, intelligent and automated environment for analysis of the huge simulation results to boost productivity.

Having worked in custom design environment in my previous job, I have seen how native environments make simulators more powerful. It’s the environment that provides a complete solution and is the differentiator against point tools. An individual simulator can be integrated into design flows and managed through scripts, but that approach limits the scope for management and control of regressions; moreover the full potential of the simulator can seldom be exploited.

A simulator integrated in a 3[SUP]rd[/SUP] party design environment gets tied-up in that environment and there is often a lag in gaining access to its new features and capabilities; this problem was evident during my talk with Geoffrey Ying, Product Marketing Director for AMS group at Synopsys. On February 3, Synopsysannounced a brand new native environment that will be included at no additional cost with its circuit simulators. It seems to be a very powerful simulation environment; I personally liked some of the features that cater to key requirements of the analog design community today.


SynopsysSimulation Analysis Environment (SAE) will be integrated with HSPICE, FineSim SPICE and CustomSim in the 2016.03 release with the latest advanced simulation features available in the GUI environment. The highest level of precision for 16/10nm FinFET, as well as performance up to the giga-scale level can be obtained in the same environment by utilizing different simulators. The environment is easily customizable, and long simulation jobs can be distributed across a network.

A netlist read directly into the environment, intelligently parsed and understood in the right context provides a unique capability for analog and mixed-signal simulation setup where the netlist can be cross-probed with a visual representation of different simulation blocks under different directives. Testbenches, analysis types, design parameters, output measurement statements, and various other simulation setups can be done with ease. TCL scripts generated from interactive sessions can be customized further for regression runs in batch mode.

The SAE can directly read-in data from the design netlists, and analog/digital partitions can be easily visualized in the language-sensitive text editor or schematic of a mixed-signal design. Annotation for interface elements can be added in the schematic as well as text view. There are interesting simulation management features to assist comprehensive sweeps, corners and Monte Carlo simulation. An intuitive color scheme has been used to distinguish between min and max or pass and fail with ease. Multiple testbenches are supported with a history of results preserved for each testbench. Active job monitoring can be done where a long running job can be halted to let other high priority jobs precede for better resource management.

The SAE provides a powerful post simulation analysis and debugging environment where results are visible along with dynamic data filtering for pass/fail/all and their visual indicators as soon as they become available after the simulation run. The current results can be easily compared with historical results available in the system. The SAE also provides tight integration with Custom WaveViewfor debugging with actual waveforms.


The Synopsys SAE provides a unique and powerful data mining and charting capability for root cause and correlation analysis. Statistical and multi-parameter charts are presented which provide direction to find the best set of desired parameters. The reports are web-based with hyperlinks in the testbenches that can be used for quick access to their corresponding results. The results can be navigated to analyze detailed measurement data and also to view the waveforms saved during simulation, that’s a unique feature.

Synopsys has disclosed in their press release that Samsung has deployed this new simulation environment in their System LSI business unit. Samsung’s System LSI BU was an early collaborator with Synopsys for conceptualizing this new environment; that’s like a customer-driven initiative.

The Synopsys SAE will be included with existing Synopsys simulators in their 2016.03 release in March of 2016 without any additional cost. This is a step in the right direction towards promotion of increased analog automation. Analog automation cannot be like digital, however intelligent, assisted tools and environments like these can increase productivity and throughput significantly for analog designs.

I guess most of the analog design community is familiar and has worked with Cadence ADE which has been around for a long time. Now Synopsys SAEis available for all analog and AMS designers using Synopsys simulators. Going forward, it is expected to interoperate with other simulators, as well.

The Synopsys press release is HERE.

Here is the link to register for the SAE webinar: Improving Analog Verification Productivity Using Synopsys Simulation and Analysis Environment (SAE)

Pawan Kumar Fangaria
Founder & President at www.fangarias.com


How 16nm and 14nm FinFETs Require New SPICE Simulators

How 16nm and 14nm FinFETs Require New SPICE Simulators
by Daniel Payne on 02-07-2016 at 7:00 am

About 35 years ago the first commercial SPICE circuit simulators emerged and they were quickly put to work helping circuit designers predict the timing and power of 6um NMOS designs. Then we had to limit our circuit simulations to just hundreds of transistors and interconnect elements to fit into the RAM and complete simulation runs over night. Today we can enjoy using our smart phones with 5.7″ displays that are using FinFET nodes at 16nm and 14nm, but what kind of SPICE circuit simulator do circuit designers need to be using? Let’s start out by looking at an idealized FinFET and note the 3D nature of the transistor, especially how tall it has become:


FinFET 3D structure, Source: Intel Corporation

Some of the new challenges with FinFET design are:

  • The number of device parasitics have increased
  • Layout rules are more complex and prohibitive
  • Device noise must be included for accurate analysis
  • Model evaluation is more compute intensive
  • SPICE simulation run times are increased

Many consumer and industrial applications are already using the 16nm and 14nm FinFET technology for chips used as application processors, graphics processors, FPGAs and Memory. The typical trade offs occur in both FinFET and planar CMOS technologies: power versus speed versus area versus reliability. To reach your market window on time it is important to have EDA tools and a methodology that are up to the challenge.

Consider designing a PLL (Phase Locked Loop) circuit, the device noise must now be included for closed loop PLL phase noise analysis or else your results are too inaccurate (~30dB difference):


PLL Analysis must include device noise

Device noise is now a first order effect for FinFET transistors, so it’s an added type of modeling required for noise sensitive designs. Adding device noise will slow down the simulation speed of a SPICE circuit simulator.

Going back to the initial example of a smart phone which is battery-powered, we know that circuit designers are minimizing power to extend the battery life by using power gating, adding read/write assist circuits, and using multiple operating voltages. All of this circuit complexity impacts on-chip variations that lead to a jump in the number of PVT (Process, Voltage, Temperature) corner simulations required:


Number of PVT corners increases at 16nm, 14nm

With FinFET transistors the physical layout has more parasitic RC elements than planar transistors that need to be extracted and simulated in SPICE, plus there are more coupling capacitors, which tend to bog down SPICE circuit simulators even more. LDE (Layout Dependent Effects) contribute to longer running circuit simulations, and the following chart depicts the parasitic complexity increases as a function of smaller geometries:


Parasitic complexity versus process geometry

On the reliability front we know that FinFET transistors can degrade over time by a few effects:

  • Hot Carrier Injection (HCI)
  • Positive Bias Temperature Instability (PBTI)
  • Negative Bias Temperature Instability (NBTI)

With thinner dielectrics being used in FinFET designs the effects of device aging will actually increase the voltage thresholds for P and N channel devices, plus the channel carrier mobility will slow down, both which make the circuit perform more slowly and even shortens the circuit lifetime. These aging effects need to be simulated in SPICE to understand the reliability impact.

Analog FastSPICE

The good news is that the SPICE circuit simulator from 35 years ago has been dramatically re-architected to address each of these issues raised so far when designing with FinFET transistors. Just two years ago Mentor Graphics acquired the company Berkeley Design Automation and their Analog FastSPICE circuit simulator to better serve the needs of designing with FinFETs. Planar transistors have been simulated with standardized models like BSIM4 from UC Berkeley, however for FinFET transistors a new model called BSIM-CMG had to be used to account for the 3D nature and new effects:


BSIM-CMG model, Source: University of California-Berkeley

This new BSIM-CMG model can run 2X slower than the previous BSIM4 models, but thanks to the new optimizations in the Analog FastSPICE (AFS) tool you can expect accurate results while using the same memory during simulation.

With AFS as your circuit simulator enjoy the modern architecture that gives you more than 120 dB dynamic range, speedier results than other SPICE simulators, uses multithreading for best sequential runs, handles 10M plus elements, and allows verification of full circuits including parasitics.

Read the complete White Paper online, or jump straight to AFS product details.

Related Blogs


The Next Wave of Semiconductor Companies!

The Next Wave of Semiconductor Companies!
by Daniel Nenni on 02-06-2016 at 7:00 am

As we all know, venture capital has all but disappeared for semiconductor companies. Do semiconductor startups still exist and where do they come from? I ask these questions quite frequently but bloggable answers are hard to come by. When I asked Mike Gianfagna of eSilicon during ISSCC he reminded me of an old new source of emerging technology companies.

eSilicon has been working with a growing community of University researchers to address their multi-project wafer service (MPW) needs with theirSTAR online platform. It seems like the innovation trail for semiconductor companies now starts with University research, not elevator pitches on Sand Hill Road.

Here are some interesting examples that I found:

Ambiq Micro was spun out from the University of Michigan
Ambiq Micro developed a patented Subthreshold Power Optimized Technology (SPOT™) platform that dramatically reduces the amount of power consumed by semiconductors. By applying SPOT, Ambiq produces the world’s lowest power real-time clock (RTC) and microcontroller (MCU), Apollo. Through the use of its pioneering ultra-low power technology, Ambiq is helping innovative companies around the world to develop differentiated solutions that reduce or eliminate the need for batteries, lower overall system power, and maximize industrial design flexibility.

Isocline was also spun out of the University of Michigan:
Isocline is giving senses and situational understanding to consumer products by dramatically improving their ability to interpret sensors, microphones, and cameras. Moore’s law is stressed and this has limited what new experiences chip companies can bring to consumer products. Isocline addresses this problem by developing a sensory processing method that uses analog techniques for signal processing and neural networks. What normally takes thousands of transistors can be done with dozens of transistors. Compared to existing chips, they get a 10-100x improvement across the board for performance, cost, and battery life.

Cubeworks was also spun out of the University of Michigan
CubeWorks was founded in 2013 to make the next-generation millimeter-scale computing available today. The company’s origins come from the Michigan Micro Mote (M3) initiative, a project from the University of Michigan seeking to push the frontiers of computing.

Seamless Devices was spun out of Columbia University:
Analog designers are faced with the challenges of designing higher-performance analog interfaces at lower supply voltages. Seamless Devices’ Switched-Mode Operational Amplifier (SMOA) provides a new class of feedback amplifiers, and addresses these issues through the application of patented switched-mode signal processing algorithms. Developed at Columbia University’s Integrated Systems laboratory, Seamless’ SMOA technology will help designers to achieve higher performance with the same power, or make the tradeoff to lower power while maintaining current performance levels, even as new process nodes continue to reduce supply voltages.

Ferric Semi was also spun out of Columbia University
Ferric is commercializing innovative DC-DC power converter chips and circuit IP based on patented thin-film power inductors for customers in both mobile and cloud computing. Ferric’s proprietary technology can be applied across a broad spectrum of power electronics ranging from full scale servers to the chip level.

Lion Semi was co-founded by Prof Le while he was at UC Berkeley
Lion is a fabless semiconductor startup designing power management ICs (PMICs) for mobile devices. Unlike today’s PMICs that require many large PCB inductors, they created a PMIC with zero PCB components and very small footprint. They are working on a patent-protected, revolutionary PMIC design that is unlike any solution available.

To me this is VERY encouraging. While the VC community is raising herds of unicorns for slaughter, semiconductor professionals are going about the business of bringing world changing technology to the masses. In parallel to the University born fabless semiconductor companies, I predict that the tens of thousands of semiconductor professionals negatively affected by the continuing industry consolidation will also be looking for MPWs in the not so distant future, absolutely.

More articles from Daniel Nenni


Let’s Reduce Wasted Energy in Server Farms

Let’s Reduce Wasted Energy in Server Farms
by Alex Lidow on 02-05-2016 at 4:00 pm

With the growth in streaming video and the promises of 50 billion IoT gadgets making our lives oh-so-much better, there is an alarming demand for online computational horsepower and bandwidth.

Why alarming? In 2014, data centers in the United States consumed approximately 100 billion kilowatt hours (kWh) of energy. According to Sudeep Pasricha, an associate professor in the Department of Electrical and Computer Engineeringat Colorado State University, “that’s almost twice the electricity needed to power the whole state of Colorado for a year.” Further,this growing and insatiable desire for digital content is actually polluting the environment: the massive data centers that house all this digital content on servers are now responsible for an astounding 2 percent of global greenhouse gas emissions, a similar share to today’s aviation industry.

Inefficient grid
To add insult to injury, the power needed to support this rapidly growing demand comes from an electrical grid that is wildly inefficient and is based on infrastructure that was created, in large part, more than a century ago. To put it simply, electricity goes through several conversion stages: first, from its origination at the power plant, then on to transmission through power stations before finally feeding the remaining energy through semiconductor chips to provide computer power to servers. And due to aging equipment, a significant amount of power is lost as it travels from the power plant to the computer chip that does all the actual computing work.

Just how significant is this waste?It turns out that the power grid supplies 150W of power to meet the demands of a digital chip that may need only 100W. Moreover, the amount of wasted energy is even greater because every watt of power lost through power conversion is transferred into heat. And it is necessary to remove that heat from the server farm by expensive and energy-intensive air conditioning. It takes about 1W of air conditioning to remove 1W of power losses, effectively doubling the inefficiency of this power conversion process. Not to mention the enormous amount of carbon-dioxide that these air conditioning units emit in an effort to convert all that wasted energy.

In aggregate, the combined waste across the United States due to data center power conversion is enough to power over half of the state of Colorado.

Also Read: Submerging the Data Center


Limits of silicon
And if the inefficiencies and waste in the power grid aren’t enough, the power conversion process has been built around post World War II silicon-based semiconductors, which have reached their theoretical power conversion performance limitations. Subsequently, these chips are responsible for creating additional power inefficiencies, with great financial and environmental costs.

However, new materials have emerged that can convert electricity more efficiently and at a lower cost. In short, superior crystal properties in these materials enable the elimination of the most wasteful final stages of conversion. It’s a dynamic similar to the evolution of air travel in the post WWII era. Initially, air travel across the country required at least one stop for refueling. When jet powered flight became commercially available, the increased fuel efficiency resulted in not only non-stop coast-to-coast travel, but also significantly reduced costs of the journey.

By eliminating the inefficiencies in this final stage in the server farm power architecture we can realize a direct saving of 7 billion kWh per year. This is doubled when air conditioning energy costs are added, bringing the total to about 14 percent of the total energy consumed by servers in the US alone. The cost savings are also significant. At the average cost of $0.12 per kWh, that’s a savings of $1.7 billion annually, which does not include the additional savings in system cost resulting from fewer power converters and air conditioners.

While the need for computing power is only likely to increase in the upcoming years, technologies are appearing that will help reduce waste and drive subsequent environmental and financial savings that benefit future generations of information gluttons the world over.

We wrote a book about this subject. You can find it at: http://epc-co.com/epc/Products/Publications/DC-DCConverterHandbook.aspx



Qualcomm goes in Data Center thanks to Google

Qualcomm goes in Data Center thanks to Google
by Eric Esteve on 02-05-2016 at 12:00 pm

The Server SoC at the heart of Data Center almost don’t care about power consumption, at the opposite of Application Processors for smartphone. If you design a server multi-core SoC, you target the highest performance, in fact a combination of high frequency and lowest possible latency, and try to pack as many CPU core and embedded cache memory in a single chip. The first limitation is the die size, the chip should exhibit a yield compatible with semiconductor economics, and the power consumption compatible with physic laws (electro-migration, voltage drop and thermal dissipation). Please note that I didn’t mention power efficiency, as I don’t think it’s really a care about for this type of SoC design.

You will appreciate how challenging is the move for Qualcomm to penetrate this data center market. In fact, Qualcomm desperately need to find new market segment out of mobile. Samsung and Apple, the top two leaders in high end smartphones, are going vertical, integrating their internally designed AP. In the lower end smartphone segment, Mediatek and Spreatrum are now reaching double digit market share. To escape from this squeeze effect, Qualcomm has to move into new application. Qualcomm is good at designing application specific processor, the company has built an impressive IP port-folio (ARM architecture license, DSP, GPU, Network-on-Chip, etc.) as well as experienced designer team and is not afraid by the most advanced technology nodes like 16FF nm or even lower.

Should Qualcomm attack an hypothetic IoT market characterized by sub $5 processor price or the very dynamic data center market? I have made some market size evaluation, grapping data from IDC or Gartner. My evaluation is that the server SoC market weight $15 billion in 2015 (99% captured by Intel), SoC shipments are in the 25 million (per year) range, leading to an ASP in the $500-600 range…

25 million units is roughly 100 time smaller than the AP market size… but ASP is 20x larger. Moreover, instead of a myriad of competitors who need to gain market share (at any price?), there is only one competitor… Ok, it’s Intel.

If this news (Google will buy server SoC to Qualcomm, if the expected performance is verified) is confirmed, and we should know it by 2/11, this could ring the bell for a very interesting fight. On my right stands Intel, literally owning this market, and designing for the highest performance at any Silicon area and power consumption expense. On my left, Qualcomm who has been cleaver enough to kick out competitors like Texas Instruments, Nvidia or STMicroelectronics from a $30-40 billion AP market within 5 years (2005-2010). Which makes this move so interesting is the fact that Qualcomm not only brings its own IP, or ARM 64-b CPU, but also comes with a completely different design culture: design for power efficiency.

What’s happen when a SoC consume so many power like it does today in data center? This incredibly high power consumption impacts cost of ownership at every stage, not only electricity bill.

  • The package should have exceptional Theta jA (power dissipation) characteristic, it’s more expansive than a standard package.
  • Power should be dissipated by the means of a heat-sink mounted on the package.
  • The rack itself has to be cooled
  • The data center has to be cooled, amount of electricity spent to run the cooling system is higher than the electricity spent to power the data center chips

Last but not least, as for any IC, the SoC performance degrades when the junction temperature goes up.

I honestly don’t know by how much it would be possible to decrease server SoC power consumption. That I know for sure is that the Qualcomm designer culture is to design for performance and power efficiency. Will they do better than Intel for server SoC? Let’s say that Qualcomm is probably one of the very few companies able to address this challenge…

From Eric Esteve from IPNEST


Also Read: Submerging the Data Center

More articles from Eric…


Supernovae and Safety

Supernovae and Safety
by Bernard Murphy on 02-05-2016 at 7:00 am

Whenever we push the bounds of reliability in any domain, we run into new potential sources of error. Perhaps not completely new, but rather concerns new to that domain. That’s the case for Single Event Upsets (SEUs) which are radiation-triggered bit-flips, and Single Event Transients (SETs) which are radiation-triggered pulses propagating in a circuit. These used to be important primarily for space-based electronics and devices operated close to nuclear reactors, but as circuit sizes shrink and expectations rise, they have also become a concern in safety-critical auto electronics.

SEUs and SETs can be triggered in multiple ways, through nuclear events and external electromagnetic events. Years ago, we worried about ionization caused by alpha-decay from isotopes in the lead in packaging (alpha particles have very short range so any effect has to originate very close to the die). That source seems to be less of a concern now, either thanks to isotopic refinement or use of other materials. Aside from transients induced by lightning, the rest of the problem comes from cosmic rays – there is evidence that a significant percentage of these start in, or are accelerated through supernovae though details are still in debate. The bulk of the flux incident on the earth is protons. These interact quickly in the atmosphere, in part converting to neutrons through electron capture or other mechanisms. Since neutrons have a low interaction cross section they can make it to ground-level quite easily where they can potentially disrupt electronics.

Neutrons have no charge so they can’t directly disrupt an electrical circuit, but they can collide elastically or inelastically with a nucleus. In an elastic collision, the target nucleus is knocked out of the lattice, ionizes in the disruption and can trigger an electrical event. In the inelastic case, the neutron can trigger fission which then has electrical consequences. One significant source starts with [SUP]10[/SUP]B (boron, used in doping), which with the added neutron splits into [SUP]7[/SUP]Li (lithium) and an alpha particle. And then there are multiple inelastic reactions with silicon producing ionizing secondaries:
[INDENT=2][SUP]28[/SUP]Si + n → [SUP]28[/SUP]Al + n
[SUP]28[/SUP]Si + n → [SUP]27[/SUP]Al + d
[SUP]28[/SUP]Si + n → [SUP]25[/SUP]Mg + α
[SUP]28[/SUP]Si + n → [SUP]28[/SUP]Al + p
[SUP]28[/SUP]Si + n → [SUP]27[/SUP]Al + p + n
[SUP]28[/SUP]Si + n → [SUP]24[/SUP]Mg + n + α

Since these events are triggered in or near a transistor, electromagnetic impact is all but certain. Not that this happens very often. Matter looks largely empty to neutrons so a thin die is a negligible barrier (shielding neutron flux from reactors requires thick walls of lead). But the event rate isn’t zero. Xilinx estimated mean-time between failures due to SEU for one of their large Virtex devices to be over 600 years. There is nothing here unique to FPGAs, so put 100 devices together in a car and you could have a failure about every 6 years. Put a million of those cars on the road and you have a serious problem, especially given that average car lifetime these days is around 15 years. A surprising impact for something that started towards us from millions or billions of light-years away.

How do you fix this? You could make devices bigger so that charge flux from a single event would be negligible. But that’s going in the wrong direction in modern device design. The alternative is redundancy with voting. Critical circuits have 3 versions; if one circuit is disrupted, the probability of either of the other circuits being hit at the same time is miniscule (multiply probabilities). So a vote on outputs of the three circuits should have a very high probability of being correct, even in the presences of SEUs. Don Dingee has written recently and more extensively on this topic in SemiWiki. But you can’t use redundancy everywhere – the design would be huge. So you just use redundancy in the safety-critical sections. And there’s the rub, as Shakespeare might have said if he knew more about functional safety. When you start being selective, you can make mistakes. You need a backstop to catch those mistakes.

The best way to do this, interestingly, is through fault simulation. Fault sim seemed to vanish from the design universe when DFT and ATPG took off, so it’s worth recapping what how it works. You simulate the good machine (no faults), inject a fault, simulate the bad machine and compare to find differences in behavior. Except in the SEU/SET case, we’re no longer looking for manufacturing problems. We looking for “faults” which are bit flips or propagating pulses. And we’re no longer concerned about sorting good versus bad die. We’re looking at in-field problems and want to determine if the redundancy logic adequately screens these out in safety-critical areas. This is a perfect application for fault simulation. But just like you don’t want to insert redundant logic everywhere, you don’t want to fault every single node. The safety verification team (separate from the design team) builds a “fault dictionary” listing all the nodes they want to test. Then separation of design and verification (plus ISO26262 process compliance/oversight) provides confidence that all safety-critical logic is indeed hardened to SEU/SET.

Cadence has a comprehensive functional safety simulation solution in Incisive. They work directly with all players in the value chain from auto-makers through tier-1 and on down to component manufacturers, and are actively involved in further developing the safety standards. They told me that chapter 11 of ISO-26262 is in development and is expected to quantify several requirements that today are only described qualitatively. You can learn more about the Cadence safety simulation solution HERE.

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