SemiWiki – Page 630 – The Open Forum for Semiconductor Professionals

August 2, 2016October 8, 2021

efabless: Think GitHub for ICs and IP

efabless: Think GitHub for ICs and IP
by Daniel Nenni on 08-02-2016 at 4:00 pm
Categories: Semiconductor Services

For those of you who don’t know, GitHub is the crowdsourcing version of the defacto industry standard GIT source code management software. Currently, more than 14 million people have deposited more than 35 million software projects (mostly open-source) on GitHub making it the largest host of source code in the world.

Now think semiconductors. Imagine what could be done with an open crowdsourcing platform that dramatically reduces the cost and administrative barriers of semiconductor design and manufacturing. Sounds disruptive, right? Given the flat nature of the semiconductor industry I think disruption is a very good thing.

Do you remember how the fabless semiconductor transformation started 30 years ago? A pure-play foundry (TSMC) dramatically reduced the cost and administrative barriers of semiconductor manufacturing. Disruption is what made semiconductors the foundation of modern day life and disruption is what we need to maintain the cycle of semiconductor innovation that got us to where we are today, absolutely.

efabless corporation is the world’s first crowdsourcing platform for semiconductors. We harness the creativity of the community and dramatically reduce the cost and administrative barriers that have inhibited semiconductor innovation. In so doing, we create significant new markets for semiconductors and enable system companies to build better products and create new applications.

Another intriguing part of efabless is the people behind the company. The first name that stands out is Lucio Lanza. Lucio is the 2014 Phil Kaufman Award winner (recognizing excellence and vision in EDA) after spending his entire career in electronics. He started with Olivetti and Intel (with Phil Kaufman), then moved to EDA with Daisy Systems and Cadence, then IP with Artisan Components (ARM). Paul McLellan did a nice interview with Lucio HERE which is a must read for semiconductor professionals old and new.

The second intriguing name is Michael Wishart, efabless Chairman and CEO. Michael retired from Goldman Sachs after thirty years covering the technology industry as an investment banker. Michael is currently on the board of Cypress Semiconductor and before that he was on the Spansion board. The first question I asked Mike was why he is coming out of retirement. I already knew the answer but I wanted to hear it in his words. The answer of course is “disruption” and his rational matched up perfectly with mine.

The second question I asked was how are they going to monetize efabless. I was happy to hear it is a success based revenue sharing business model similar to how Artisan Components disrupted the semiconductor IP industry with their “Free IP Business Model” in 1998. As a competitor to Artisan at the time I can tell you this was a VERY disruptive move that transformed the fabless semiconductor ecosystem into what it is today, a force of nature.

Bottom line:efabless provides community members with a robust design flow that they access without cost or NDA. efabless obfuscates from designers the underlying technology of foundries and thereby facilitates community access to foundry process technologies, again without the requirements of NDAs. The marketplace and community is inherently collaborative with proprietary and open IP and ICs that can be forked, customized, or improved by other community members to solve interesting problems and open new opportunities. Again, think GIT Hub for ICs and IP. You can join the efabless community HERE.

August 2, 2016August 22, 2024

SEMICON West – Harry Levinson and Mike Lercel Interview

SEMICON West – Harry Levinson and Mike Lercel Interview
by Scotten Jones on 08-02-2016 at 12:00 pm
Categories: Events, Foundries, GlobalFoundries

On Tuesday morning at SEMICON I had the opportunity to sit down with Harry Levinson, Sr. Director of Technology Research and Sr. Fellow at Global Foundries and Michael Lercel, Director of Strategic Marketing at ASML to discuss the state of lithography.

I opened the discussion with a question about how we are going to address lithography from 10nm down to 5nm.

Mike Lercel – two specific directions, control and edge placement, the second theme is how multiple patterning introduces sources of variability. Process simplicity with EUV is beneficial at both 7nm and 5nm. A lot of argon fluoride immersion multiple patterning will stay and EUV will be used for the most challenging layers.

Harry Levinson – from a chip maker’s perspective there has been a lot of concern about EUV maturity for 7nm. They are looking at 7nm as a node that can be done with optical.

I asked a question about Line Edge Roughness (LER) and how much it matters for cut masks. Harry noted that even for cuts you do care about LER, for contacts and vias you do care about regularity. Via or contact on line-end is one of the most critical applications so LER does matter. Mike noted that LER affects where the line ends.

Harry noted that the good news is if we introduce EUV at 7nm we aren’t pushing it too hard. People are working on understanding LER. Shot noise is at the top of the list and you can’t do much other than increase the dose. Photoresists also contributes to LER and you need to control it at a molecular level and even the building blocks of the polymer are important so we need smaller building blocks. Mike – some of the novel materials look interesting because metal and some of the others are different than what we have today.

I asked about smoothing to address LER. Mike said it is spatial frequency dependent, the high frequencies can be smoothed better than the low frequencies. Harry, there is definite potential. Smoothing contact holes is harder than line/space and pesky line ends.

Harry said the 7nm node could be done optically and depending on customer demand could be introduced early with optical and then EUV could come next in 2018.

Mike said ASML systems in the field are at 125 watts and about 85 wafers per hour (wph), ASML’s target is 125 wph at 250 watts. Harry noted that the throughput is based on ASML assumptions and manufacturers have different requirements in terms of fields, dose, etc. Harry went on to say they are struggling to have EUV equivalent to immersion triple patterning on cost and that 5nm will likely be defined how far you can push EUV and still have single patterning. Mike, a true shrink that requires 6 immersion layers versus 3 EUV layers is kind of a cost wash.

Harry, a 2.5nm overlay budget is really hard because you are dealing with angstroms. Mike went on to say that is why you need really good mix and match of EUV to immersion.

Harry said EUV at 7nm would really help because you could learn before you have to really push it.

Mike noted that there are 8 – 3300s out in the field running and generating a lot of cycles of learning. 445,000 wafers have been processed through the tools. Without EUV we could be looking at 100 mask layers in a logic technology slowing down cycles of learning, design verification and manufacturing cycle time. (Authors note, I commented that this really struck me at the Advanced Lithography Conference this year, that for the first time there are multiple EUV systems around the world running wafers in volume and that is what you need for learning).

Harry said we will see contacts and vias done first, then metal blocks. Mask defects are still a problem but contact/vias have a lot of space to cover the defects (dark field with small open area). He is concerned about metal masks and defects (light field with high open area). It would be very desirable if line/spaces could be EUV. At N7 metal is 3 masks but he would like to do a single EUV mask. Mike also pointed out that at N5 you could be looking at a grating and more than 2 block masks.

Harry said that for 7nm contacts/vias productivity is still the main issue, they need 250 watts robust in the field. I asked him if he had a 250-watt high uptime tool today could he do 7nm contact/vias and he said yes. For contacts you have local critical dimension uniformity (LCDU) the contact version of LER and they can hit the specs with high dose, the key is how far you can back off the dose without hitting yield. With respect to mask defects the ITRS specs were based on planar gates, today there is no rigorous metric but to get to metal layers you need lower mask blank defects. Mike agreed, with contacts dark field can cover defects, metal is light field and the can’t cover the defects.

Harry, once you have the power you need to see if there are mask and wafer heating issues. Mike, Samsung saw a mask blister at 40,000 wafers, it wasn’t that long ago that immersion hazing occurred on masks at 35,000 wafers.

I asked about pellicles and Mike said no new announcements today (Mike and Harry were both scheduled to present in a session after our interview). They have run 200 wafers at a customer tool and they continue to run it at a 40-watt level. They still need to improve the pellicle. Harry jumped in to say the pellicles don’t have the transmission we are used to plus may need a filter; we will lose at least 20% of the light.

In closing Harry said that the front end of line (FEOL) has lower density so mask blank defectivity is less of an issue. EUV could enable multiple gate lengths and Mike also noted eliminate multiple cut masks.

August 2, 2016June 14, 2019

1-T SRAMs in high-density, portable applications

1-T SRAMs in high-density, portable applications
by Farzad Zarrinfar on 08-02-2016 at 7:00 am
Categories: EDA, IP, Mobile, Siemens EDA

For SoCs designed for various applications such as mobile, automotive, wearable computing, gaming, virtual reality, PC, imaging, security, and IOT applications, it is incredibly important to keep area (cost) and power as low as possible. Considering the growing percentage of chip area used for memory, it makes sense to choose the optimum memory IPs for each application. Among the memory IPs targeted for high-density consumer applications is the single-transistor dynamic random-access memory from Mentor Graphics (Novelics) called coolSRAM-1T.

You can read all about the coolSRAM-1T in Fundamentals of coolSRAM-1T Memory.

The one-transistor (1T) bit cell offers up to 50% reduction in core area for a given bit capacity compared to the more widely-used six-transistor (6T) bit cell. When your focus is on density over speed, the 1T architecture is an ideal choice. Figure 1 illustrates the density relationship between two embedded memory IP architectures.

But what about static power for always-on SOCs? A 6T SRAM uses an active driver to maintain data, so leakage power can be a concern in advanced process nodes. The coolSRAM-1T uses passive storage structures optimized for low leakage. To minimize subthreshold and junction leakage, the Mentor Graphics’ coolSRAM-1T dynamic memory cell utilizes the thick oxide or input/output (I/O) transistor option available in all advanced process nodes. The coolSRAM-1T is a nearly seamless replacement for existing SRAM-6T for lower leakage and chip area. It is also cost-effective since it can be implemented using a bulk-CMOS process with no additional mask steps.

The peripheral circuits for the coolSRAM-1T include (1) the sense amplifier and (2) the write-back circuit that restores the charge into the cell after a destructive read. To boost the signal in a given cell capacitor area, we operate the cell array at I/O voltage, which results in a larger signal for the sense amplifier and improves performance. The interface to the system is at the VDD (core) voltage. The signals must be level-shifted from one voltage domain to another as they travel from the memory interface to the cell array, and we offer three approaches for doing that that offer different tradeoffs depending on your needs.

The coolSRAM-1T is integrated into the Mentor Graphics MemQuest compiler, the web-based tool suite that lets you specify and implement custom memories. Compiled instances in the 160nm 1.8V/3.3V, 130nm 1.5V/3.3V, and 110nm 1.2V/3.3V technology nodes have been incorporated into customer products and are in volume production and is also silicon proven in 65nm technology. With the IP license comes documentation about the test flow, which includes three major steps:

[LIST=1]

Internally stress the instance to uncover any over-stress defects that could become failures in time.

Run the SRAM-style BIST (built-in-self-test) algorithm to check for defects or failing peripheral circuits.

Verify cell retention at higher temperature operation.

The coolSRAM-1T embedded memory IP is the only silicon-proven single-transistor SRAM IP that can be implemented in bulk CMOS. For high-density consumer applications, it can lower the overall system cost and static power consumption by reducing the area and the number of external components.

Learn more about Mentor Graphics coolSRAM-1T and the trade-offs between using the coolSRAM-1T and the coolSRAM-6T in this free Mentor whitepaper Fundamentals of coolSRAM-1T Memory.

August 1, 2016

Filling out the rest of the mobile device

Filling out the rest of the mobile device
by Don Dingee on 08-01-2016 at 4:00 pm
Categories: Events, Mobile

We spend an inordinate amount of energy tracking the big chip – the application processor – in a mobile device. As we’ve seen this space is coming down to a handful of players. A more interesting competition is heating up around the APU for the rest of chips needed to make a phone. Continue reading “Filling out the rest of the mobile device”

August 1, 2016September 1, 2024

Foundry Technology Packaging Solutions

Foundry Technology Packaging Solutions
by Tom Dillinger on 08-01-2016 at 12:00 pm
Categories: Foundries, Samsung Foundry

A significant shift is underway in the fabless semiconductor business model. As the application markets have become more diverse (and more cost-sensitive), product requirements have necessitated a new focus on multi-die packaging technology.
Continue reading “Foundry Technology Packaging Solutions”

August 1, 2016

Limits to Deep Reasoning in Vision

Limits to Deep Reasoning in Vision
by Bernard Murphy on 08-01-2016 at 7:00 am
Categories: General

If you are a regular reader, you’ll know I like to explore the boundaries of technology. Readers I respect sometimes interpret this as a laughable attempt to oppose the inevitable march of progress, but that is not my purpose. In understanding the limits of a particular technology, it is possible to envision what properties a successor technology should have. And that to me seems more interesting than assuming all further progress in that direction will be no more than fine-tuning.

Take deep learning and vision. Recent progress in this direction has been quite astounding; in one example, systems have bested humans in identifying dog breeds. These systems are now used in cars for driver assistance and safety applications – detecting lane markings, collision hazards, even traffic signs. Increasingly Google and Facebook use image recognition to search and tag people, animals and objects in images. It seems we’ve almost conquered automated image recognition at a level better than humans. But have we really, and if so, is that good enough?

While progress in deep reasoning has been impressive, there have also been some fairly spectacular fails. Microsoft was forced to retire a chatbot after it developed racist and other unpleasant tendencies. Google had to remove the “gorilla” tag from its Photos app after complaints that it was identifying dark-skinned people as gorillas. And Google released open-source software which identifies surrealist collages of faces in what we would consider perfectly ordinary images (in fairness, Google was pushing the software to see what happened).

You could argue that this is just normal progression for technology. Perhaps once the bugs are worked out, these problems will be rare. But I am skeptical that solutions as they stand just need better training. Our own fallibility in image recognition should be a hint. It’s common to see faces and other images in complex irregular patterns if we stare at them for a while. This phenomenon is called pareidolia, a bias of the brain to see patterns, particularly faces in random images. I can’t imagine why deep reasoning should be immune from this problem; after all we modeled the method on human reasoning, so it would be surprising if it did not also inherit weaknesses in that approach. In fact the Google software that produced surrealist images is known to have this bias.

How good the recognition has to be may depend on the application, but clearly there is room for improvement and for some applications, the bar is going to be very high. More training might help, up to a point. So might more hidden layers, though apparently the value of adding layers drops off sharply after a relatively small number. Ultimately we have to acknowledge that the only straightforward way to fix deep reasoning problems is to try harder, which is not an encouraging place to start when you want to find breakthrough solutions.

Or perhaps we could go back to how we think. Most of us don’t instantly convert what we think we see into action. We consider multiple factors and we pass our conclusions through multiple filters. This is so apparent that we all know people who seem to lack these safeguards; we consider them socially-challenged (or worse). Now think of a cascade of neural nets where each net is trained in different ways. Deep learning methods for particle detection at the Large Hadron Collider (LHC) use similar methods, also combining different approaches – neural nets and binary decision trees – to weed out false positives. This alone might be a good start, with a first order goal to default to “I don’t know” when there is ambiguity in recognition.

Training more nets and other methods would be more expensive and the outcome may initially be more ambiguous than we might like. But maybe that’s an inescapable reality of improved recognition. Perhaps we should think of what we have today as hind-brain recognition – good for quick reaction (fight-or-flight) response but, like the hind-brain, not good at ultra-high-fidelity recognition where we might need improved tools.

I’m sure however this evolves the field will continue to be called deep learning, but that’s just a label. For one insight into limitations in existing architectures and newer methods, see HERE. You can see the Google surrealist art HERE.

AMD Unveils Full Radeon RX 400 Models And Positioning At E3

AMD Unveils Full Radeon RX 400 Models And Positioning At E3
by Patrick Moorhead on 07-31-2016 at 4:00 pm
Categories: EDA

At E3 2016 in Los Angeles, California Advanced Micro Devices disclosed the numbering and targeted use cases of their full line of Polaris-based GPUs, branded as the “Radeon RX Series” of graphics cards. Advanced Micro Devices had previously disclosed some details about the new Radeon RX series of graphics cards at Computex 2016 in Taipei just a few weeks ago, but limited most details to the specific RX 480 graphics card. Now that we know more about the full line of AMD’s Radeon RX series of graphics cards, we can officially say that the RX 480 will be the highest end Polaris GPU that Advanced Micro Devices is launching.

AMD CEO Lisa Su chatting it up at E3 on the PC Gaming Show powered by PC Gamer (Photo credit: Anshel Sag)

Advanced Micro Devices said last week that the Polaris family of Radeon RX GPUs includes three different models, the Radeon RX 460, Radeon RX 470 and the Radeon RX 480. AMD also disclosed that mobile GPUs based on the Polaris architecture are expected to be available later this year, taking advantage of the performance-per-watt improvements in the architecture and 14nm process technology to enable “console-class gaming to thin and light notebooks for the first time.”

However, Advanced Micro Devices is only publishing the $199 pricing of the RX 480, which they disclosed at Computex. What is new beyond the names of the full Polaris launch lineup is that AMD is indicating what kinds of performance profiles gamers can expect from each of these GPUs. Advanced Micro Devices also reiterated that the 4GB version of the Radeon RX 480 will be selling for $199, indicating that we might see some higher memory configurations of the RX 480 for more than $199. I believe we will probably see a $249 8GB card.

Radeon RX 480
Advanced Micro Devices says the Radeon RX 480 is expected to deliver “smooth AAA gaming experiences to gamers at 1440p resolutions”. This means that AMD expects this card to perform fairly well compared to the high-end of the previous generation, roughly falling somewhere around a GTX 970. Because we don’t actually know the real performance numbers or have a card to test on our own, we cannot definitively say where the RX 480 will perform when compared to the competition.

I expect the RX 480 to perform well in Vulkan, DX12 and VR games, which may further help AMD’s case in terms of performance. It’ll be interesting to see if the rumors of an NVIDIA GTX 1060 are true as that would certainly make things very interesting depending on pricing, performance and availability.
Advanced Micro Devices is promoting the Radeon RX 400 series Polaris GPU family as “optimized for low-level APIs”, “console-class development” and “high performance VR”. The API point refers to the work done on Vulkan and the console point refers to what associate analyst Anshel Sag and I wrote on shader “intrinsic functions”. One key point on VR is that the RX 480 meets the minimum bar for both Facebook’s Oculus VR and the HTC Vive.

Radeon RX 470 and 460
This leads us to the other two GPUs in AMD’s Radeon RX 400 series line of GPUs, the Radeon RX 470 and Radeon RX 460. AMD is disclosing marketing positioning and model numbering but isn’t disclosing pricing or performance. They’re not doing this to be coy or manipulative, but rather to keep NVIDIA in the dark as long as possible. It’s also intended to drive speculation as evidenced by this column and get every hour possible to optimize drivers.

So here is the positioning…the Radeon RX 470 is being targeted towards “smooth HD gaming” which I believe is AMD’s code for being able to play most games at 1080P at 60 FPS. The Radeon RX 460 is offered as a “cool and efficient GPU for eSports” which probably means that it is mostly aimed towards MMO and RTS gamers where the graphics are less intensive. The mention of cool and efficient very likely means low power and possibly passive cooling in some scenarios.

Wrapping up
Advanced Micro Devices is slowly trickling out information on the RX 400 Series designed to create some ecosystem and end user excitement and to keep NVIDIA guessing. It makes life harder for analysts trying to piece everything together to find meaning, but this is life covering gaming. Everyone in gaming hardware, software and services does this.

While we still don’t know theexact performance of AMD’s new Radeon RX series of GPUs, AMD has released some telling clues about how each of their GPUs is expected to perform. The only thing that is really left up to the imagination at this point is the pricing of the Radeon RX 470 and RX 460 GPUs. The rumored NVIDIA GTX 1060 could create some chaos, too, if it’s at a real card, readily available and priced lower than AMD’s expectations.

Also, based on Advanced Micro Devices’ positioning of the entire RX 400 series as the “democratization of VR”, it would be really interesting to see how many of these three GPUs end up being Oculus Ready. To this point, only the RX 480, is but no one is saying the 470 or 460 isn’t. This is just me speculating. Furthermore, it will be interesting to see how much they will really drive down the price of building a VR system based on the pricing and VR certifications or the quality, something that we still don’t quite know. All we do know is that June 29th will be the big reveal and until then, we can only guess. But guessing makes the gaming world go around.

NVIDIA Rounds Out Pascal-Based GeForce Lineup With GTX 1060 And New Software Features

NVIDIA Rounds Out Pascal-Based GeForce Lineup With GTX 1060 And New Software Features
by Patrick Moorhead on 07-31-2016 at 12:00 pm
Categories: EDA

NVIDIA has been working hard to progress forward their new Pascal family of GPUs ever since their announcement at Dreamhack in May 2016 in my hometown, Austin, TX. The announcement included two of NVIDIA’s newest GPUs, the GTX 1080 and GTX 1070, both of which are somewhat available now. I worked with my colleague, Anshel Sag, to review the GTX 1080 and found it to be a fantastic GPU both in terms of performance and enthusiast value at that time. However, there were many software features announced along with the new Pascal family of GeForce GTX GPUs that hadn’t quite been ready yet but were major capabilities that elevated the GeForce GTX family. I thought those software capabilities deserved some extra attention and is important to me as any company who can get solution stickiness versus hardware progress becomes more important to the ecosystem. This is true for any tech product and solution. I also want to comment on the GTX 1060, NVIDIA’s latest card, priced from $249-299.

GeForce GTX 10 Series software
Some of these new Pascal-enabled features are non-performance-focused like NVIDIA Ansel (not to be confused with Anshel) which allows for a new way of taking and viewing in-game screenshots. Ansel will finally be released by NVIDIA with support for Mirror’s Edge and The Witcher 3 in mid-July.

NVIDIA CEO Jen-Hsun Huang introduces Ansel at the GTX 1080 launch event in Austin, TX (Photo credit: Patrick Moorhead)

In addition to software like Ansel, NVIDIA is overhauling their Gameworks program to include VRWorks to accelerate and improve the experiences inside of VR utilizing the strengths of Pascal and NVIDIA drivers. While there are many technologies that are a part of Gameworks and VRWorks, the most important ones to improving the VR experience on NVIDIA hardware are Simultaneous Multi-projection, ray traced audio and PhysX. These technologies are designed to improve the overall experience in VR either through improved performance or added realism.

VR Fun House
NVIDIA has actually created a full featured game that also serves as a technology demo called VR Fun House that they showed at their Pascal launch and subsequent events like E3. NVIDIA also announced that the VR Fun House will be coming to Steam this July, which means that anyone can play around with this carnival-style experience. This demo utilizes many of NVIDIA’s technologies including PhysX to add realism to VR and improve the overall experience with fluid dynamics, fabric physics and turbulence.

GTX 1080 Launch event attendee playing with NVIDIA Fun House (Photo credit: Patrick Moorhead)

Speaking of turbulence, I was completely blown away by the Everest VR experience that NVIDIA had worked with Solfar Studios to create. In part of that experience, Solfar Studios utilizes PhysX at the peak of Mt. Everest to make the snow swirl around you and wind blow by you in a way that can only be described as breath taking. There is definitely something game-changing there, I wasn’t convinced of it until I tried the final build of the Everest VR experience.

VRWorks
One of NVIDIA’s potentially most powerful VRWorks features is their simultaneous multi-projection feature that is enabling increased performance in VR with very little compute overhead. However, in order for this feature to work, it must be implemented by the game developer in their game. Traditionally this would be very difficult to do considering that trying to convince individual developers to implement a feature independently is very hard. That’s why NVIDIA instead approached the game engine companies directly in order to get simultaneous multi-projection implemented at the engine-level. They have announced that simultaneous multi-projection will be coming to both Unreal Engine and Unity, the two most popular game engines in the world today.

NVIDIA explains SMP benefits to tech analysts and press at an Austin, TX event after the GTX 1080 launch (Photo credit: Patrick Moorhead)

This means that developers don’t have to do as much work to implement simultaneous multi-projection because it will already be at the engine level. This also means that many more games will support this feature than I had originally anticipated, because traditionally certain NVIDIA-only features are implemented on a case by case basis. NVIDIA has already announced that they already have 30 games that will support simultaneous multi-projection including games like Pool Nation VR, Everest VR, Unreal Tournament, Raw Data, Adr1ft and Obduction.

NVIDIA has claimed to increase their VR performance by 50% or more with simultaneous multi-projection, which could vastly improve the performance of NVIDIA GPUs in VR regardless of the model.

NVIDIA GeForce GTX 1060
This leads us into NVIDIA’s latest announcement, the GeForce GTX 1060. Third-party, independent benchmarks are not available yet and NVIDIA claims that the GTX 1060 delivers GTX 980 performance at $249 or less than half the price of the 980 at launch, and will be available July 19th. This is virtually unheard of when you consider that the GTX 1060 is only one generation newer than the GTX 980 and less than half the price and just as fast. The GTX 1060 is slated to replace the GTX 960 which initially launched at $199, but also comes with half the performance in most cases and has more RAM than the 960, 970 or 980. This is obviously thanks to the Pascal architecture which also enables the GTX 1070 and 1080 to be as fast as they are.

The GTX 1060 features a new GP-106 ASIC (applications specific integrated circuit) from NVIDIA which is different from the GP-104 in the GTX 1080 and GTX 1070. This isn’t a cut-down die. This means that NVIDIA has purposely built this ASIC for the middle of the market and that it should yield fairly well. This also means that it should be even more optimized for low power gaming which explains the extremely low, stated 120W TDP and single 6-pin power connector compared to the 165W GTX 980. The graphics card itself will ship with 6GB of 8Gbps memory, which from my and Anshel’s experience should be enough for most gaming experiences and helps NVIDIA and their board partners keep down costs compared to 1070 and 1080. Additionally, NVIDIA told me that the GTX 1060, unlike the 1070 and 1080 will mostly ship in custom board partner designs and that the NVIDIA Founders’ Edition will be only available on NVIDIA.com at $299 for those that want it. If they can deliver the GTX 1060 in meaningful quantities, then Advanced Micro Devices just launched RX 480 has a very real competitor in a few weeks and that ultimately means great things for the consumer.

Wrapping up
As a whole, NVIDIA has done a very good job of catching up on their position inside of VR and have committed themselves immensely to improving VR. A lot of this has to do with the platform that NVIDIA is creating inside of VRWorks that enables NVIDIA’s GPUs to excel in truly immersive VR experiences like Everest VR. While it remains to be seen how many of the features outside of simultaneous multi-projection and Ansel get adopted by game developers, NVIDIA has done a very good job of introducing their new hardware and software products.

While there may still be some supply issues with the GTX 1070 and 1080, NVIDIA has reassured us that the GTX 1080 is the fastest ramp of a flagship GPU they have ever had and that demand is just that immense. It remains to be seen how well they can keep up with demand for the GTX 1060, but I suspect that most supply issues will be resolved by the end of the quarter regardless. I’m stunned, yes, stunned, at just how quickly NVIDIA got the GTX 1060 ready and I believe they accelerated the timetable when they fully realized the price/positioning of Advanced Micro Devices RX 480. Who wins? The GTX 1060 isn’t available yet nor are third party, independent benchmarks available on it, but for sure, the consumer wins as we have a fistfight in the mid-range.

NVIDIA has presented a very strong line-up of new GPUs that range from $699 to $249 and supported it with a broad array of new software, features and capabilities as well.

E-Class: Saving Lives with Fine Print

E-Class: Saving Lives with Fine Print
by Roger C. Lanctot on 07-31-2016 at 7:00 am
Categories: Automotive

Television spots for cars are becoming a little like pharmaceutical ads filled with fine print and warnings about side effects and clarifications. Safety advocates are taking Mercedes to task for its latest TV ads for the 2017 E Class, claiming that the car company is misleading consumers into thinking the car can drive itself. For me, fine print is the trade-off on the road to saving lives.

Autonews: “Mercedes Challenged over ‘Drive Pilot’ TV Ads: –http://tinyurl.com/hqen85m

I have to say that when I first noticed official online information regarding the capabilities of the new E-Class I, too, was surprised at the volume of fine print. It looks like the future will be filled with it.
The fine print in question in the E-Class notes that the car cannot drive itself but has driving assistance features noting, further, that there are frequent reminders for the driver to keep hands on the wheel. The TV ad briefly depicts the driver removing his or her hands from the wheel while appearing to be on a highway before switching to a self-parking scenario.

But fine print also appears on Websites in descriptions of the vehicle’s Car-to-X communication capability and the description of its Drive Pilot Active Lane Change function – a clear response to the lane-changing proposition offered by Tesla Motor’s Autopilot. The key difference, of course, is Tesla doesn’t advertise on TV.

We may as well face facts. From today forward increasingly sophisticated cars will be sold with increasingly sophisticated safety systems … and a magnifying glass. The latest J.D. Power APEAL scores bear this out, with makers of safety-system-laden cars leading the list:

“Safety Features Score Big, Boosting New-Vehicle Appeal, J.D. Power Study Finds” – http://tinyurl.com/h5upkg2

My own personal research has shown that new car dealer sales people are generally more attuned to and more excited about explaining safety features than infotainment features. The J.D. Power study bears out Strategy Analytics’ own findings that safety is a higher car purchasing priority than infotainment.

In an ideal world, all safety features will work intuitively and, perhaps, be available and functioning at all times. But the reality is that humans need to learn how and when to activate and de-activate these systems. The pressure on HMI scientists is growing rapidly – along with the deployment of driver monitoring systems.

The fine print is unnerving, but I think Mercedes is getting it right. It’s hard to pursue “The best, or nothing” without getting into some areas where supplemental explanation is necessary. The surfeit of fine print is a small price to pay for lives saved in the future.

Car-to-X fine print:

Drive Pilot Active Lane Change:

“[3] Active Lane Change Assist is no substitute for active driving involvement. It does not predict the curvature and lane layout of the road ahead or the movement of vehicles ahead. It is the driver’s responsibility at all times to be attentive to traffic and road conditions, and to provide the driving inputs necessary to retain control of the vehicle. System may not detect some objects, obstacles or vehicles in the area into which the vehicle would move. See Operator’s Manual for system’s operating speeds and additional information and warnings.”

Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.VuGdXfkrKUk

July 30, 2016

Why is AMD Stock Jumping?

Why is AMD Stock Jumping?
by Daniel Nenni on 07-30-2016 at 7:00 am
Categories: EDA, Foundries

One of my favorite pastimes is listening to the quarterly investor calls of the leading semiconductor companies. I can then match up the talking points with the calls I do with Wall Street, the conferences I attend, and the other data points I have collected while working inside the fabless semiconductor ecosystem for more than 30 years. Rarely do all the points match up but sometimes they are so off it makes for an interesting conversation.

As usual the prepared statements were a bit obscure and convoluted so it was very hard to draw any specific conclusions but there are several points worthy of discussion:

First and foremost, it is getting harder to differentiate the reasoning behind GAAP and non-GAAP results. For example, AMD sold a majority interest (85%) in their assembly and test operations to another firm to raise cash. As a result they recorded a significant profit on this sale ($127M after provisions for taxes).

This (one-time) profit was included in GAAP results. The CEO proudly said, “We achieved profitability this quarter, for the first time since 2014.” Yet, without this one-time operations spin-out, the net operating results were a significant loss.

It is also interesting to note that there are not many key AMD assets left for sale or spin-out. It was reported that the iconic Sunnyvale campus is for sale so AMD can move to a smaller facility. Unfortunately, AMD does not actually own the property so it cannot be used to bolster future GAAP.

Second, AMD is paying an average of almost 7% on long-term bond interest, a total of ~$2B, which will start to mature in 2018. There is clearly insufficient operating income to pay off these bonds so they’re going to have to start rolling them over, assuming their credit rating holds up.

Third, the PC market is still rather weak with “upper single digit declines to be expected this year”, according to the webcast call.

The last Bulldozer-based APU (CPU + GPU) product release occurred earlier this year, but there was no specific mention of this product on the webcast call. (As AMD has already pre-announced the replacement core architecture “Zen” it’s likely that this last APU refresh will not generate much new revenue or market share in the consumer PC or laptop area.)

They did indicate that the initial Zen-based server chip is with first customers for evaluation, and that “sales should begin in the first half of 2017”.

Fourth, AMD is benefiting from both the XBox One and the PS/4 for the coming Christmas season, although one of the analysts said, “OK, that’s a nice ramp in revenue, but the price takedown negotiated with Microsoft and Sony over time means this is likely a low margin return.”

AMD countered with, “We are also ramping for the mid-life refresh of the consoles, as well — we’re excited about Microsoft’s announcement of the XBox One S, a new console with improved High-Dynamic Range rendering support.” Unfortunately, Microsoft also has announced another refresh in 2017 which will likely cut into XBox One sales this year.

Bottom line: AMD is definitely counting on a very well-received Christmas buying season for game consoles which may not happen.

Fifth, AMD announced a refresh of their discrete GPU card plug-in product family. The good news is they priced it very aggressively, and it appears to be selling well. The bad news is two-fold — (1) this is just a FinFET-based replacement to an existing product line with better power dissipation but no significant performance boost that one would expect with a new GPU architecture and (2) Nvidia just announced their stripped down version of their new architecture and a competitive performance and price point. Some games play better on one or the other. Hard to imagine a mid-range, aggressively-priced GPU refresh generating sustaining revenue growth.

Sixth, there is a new joint venture with a Chinese firm to provide a specific x86-based server. Last quarter, when this JV was announced, AMD recorded “operating revenue” to address the R&D applied to this project. On the conference call this quarter, if I understood correctly, they recorded the payment from the Chinese firm as “IP licensing” and they said they had hit the first project milestone and expected the scheduled payments to continue.

Seventh, no mention of AMD’s ARM-based server product initiative, either the existing “Seattle” 28nm design (announced late last year) or its supposed refresh (using the ARM A72, in a 14nm process, due early 2017, as I recall). Remember, AMD bought ARM based server company SeaMicro in 2012 for $334M only to shut it down in 2015.

Eighth, there are high hopes for the Chinese JV, but that’s a couple of years away from generating any significant sales. It’s just R&D reimbursement currently.

Bottom line, expect a strong game console sales bump this year (but with pressure on margins). A GPU refresh will generate a bump in revenue (again, not at the high-end with its commensurately higher margins). PC revenues will decline. Server revenue is still very weak. And, there is a rather large debt redemption pending.

It’s all going to come down to whether the Zen-based x86 refresh captures new server (and subsequently, consumer PC) market share away from Intel. Time will tell, although the fact that the initial 14nm GPU part was somewhat “underwhelming” in power/performance does not bode particularly well for the Zen-based server part in 2017. I should also note that the original architect and team leader of Zen (Jim Keller) now works for Tesla as do several of his team members.