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February 27, 2018

Hardware Configuration Management – A Key Enabler for Startups & Big Companies Alike

Hardware Configuration Management – A Key Enabler for Startups & Big Companies Alike
by Mitch Heins on 02-27-2018 at 12:00 pm
Categories: Cliosoft, IoT

Software configuration management (SCM) has been around for a long time with commercial SCM offerings such as ClearCase and Perforce and public domain mainstays such as CVS and Subversion. Similarly, over the last two decades we’ve seen a big uptake in the adoption of hardware configuration management (HCM) methodologies driven by the exponential growth in systems-on-a-chip (SoCs) complexity, larger amounts of binary design data, an increased need for better control over data security, and the use of larger geographically-dispersed design teams.

More recently, the complexity growth is being exacerbated by newer heterogeneous SoC architectures required by the internet-of-things (IoT) devices. These devices fuse data from multiple different sensors and some even employ artificial intelligence techniques that combine both hardware and embedded software to process data before sending actionable information back to the cloud.

Managing SoC design data is particularly challenging when one considers that the design data is a composite of many different CAD abstractions and views. Design teams regularly use CAD tools from multiple electronic design automation (EDA) vendors, each which have their own data representations with different and many times incompatible databases. Layer on this the fact that designs also use multiple IP libraries, some built internally while others are from outside vendors.

Add to this the fact that design teams are comprised of engineers with varied backgrounds who are working on different steps of the design process, on different networks and different hardware platforms while geographically dispersed across the globe. These engineers have different responsibilities and access rights to project data that must be strictly enforced.

For any SoC design, it is necessary to effectively manage the sharing of completed design data while isolating data that is still in progress (e.g. shared libraries vs scratch libraries). Hardware teams have traditionally relied on human-based data gate-keeping to ensure engineers don’t inadvertently overwrite each other’s work when copying changes from scratch areas to master libraries. It’s a practice that is fraught with error and almost unmanageable for teams that cross multiple time zones.

Teams have tried to mitigate the time zone problem using multiple master libraries, which they try to keep in sync on a regular basis. The use of hierarchical design complicates this practice as changes to lower level cells may not be seen due to latency between updates to the different master libraries and the lack of a clean bill of materials detailing cell versions to be used by the project. A much bigger problem occurs when changes are not detected and the project tapes out. This sort of error can necessitate a very expensive re-spin. File management is also cumbersome in this arrangement with multiple copies being kept on each site for both use and archival, which increases the cost of the associated storage devices.

The biggest issue aside from the logistical management of files and databases is the lack of a common process for managing the numerous revisions on all views of the design. This is where a hardware configuration management tool comes in. Many companies have taken different approaches to resolving the issues unique to the hardware designer. While some have opted to build layers on top of existing SCMs such as subversion, others have taken the route of creating the HCM from the ground up, providing a better platform which can be easily customized to the different needs of hardware design teams.

SOS7, a HCM from ClioSoft, is a good example. ClioSoft’s SOS7 streamlines the design process and significantly improves a team’s productivity. It acts as a gatekeeper and protects the users from accidentally losing or overwriting valuable data, eliminating the need for manual bookkeeping. SOS7 employs a distributed Client-Server architecture that allows access to data irrespective of a user’s location. Data is stored once in a common project repository and the system makes use of remote cache servers to reduce network bandwidth and minimize the effects of network latency.

Most importantly, SOS7 ensures that design changes are seen immediately by all other members of the team, regardless of the hardware platform used, as SOS7 works cross platform and is available on both the Linux and Windows. SOS7 also provides for sandbox development areas to isolate changing data. Objects checked out for edit have write-locks to prevent accidental overwrites by others with the ability to revert to or view previous versions.

Especially important for safety critical applications requiring ISO 26262 certification is that SOS7 maintains audit trails of all changes made to the design. SOS7 also employs gate keeping policies for data access control and integrates data management with requirements and issue tracking systems such as Jira, Bugzilla and Trac.

While SCM systems deal with source code in the form of ASCII text files, HCM systems must deal with data in different EDA formats. EDA tools create many different types of side files used to manage their own data. Knowing which of these files to archive can be cumbersome, but SOS7 takes care of that automatically, making it easier to add or exchange tools within the design flow as needed. This is enabled by the EDA vendors providing application programming interface (API) support that allows SOS7 to manage their data for them. DM APIs enable the design flow to seamlessly support revision control with automatic check-out and check-in capabilities without requiring the designer to know all the nuances of which EDA files need to be stored and which can be ignored.

It is easy to do a diff with text files, but it is a different problem when it comes to binary files such as schematics or layout views. SOS7 can easily do the text diff capabilities like SCM, but it also goes the extra mile by providing a mechanism to highlight differences between versions of a schematic or layout. In addition, ClioSoft also added design management GUIs directly into the EDA tool library browsers and design editors to give engineers the capability to browse libraries and design hierarchies, examine the status of cells and perform revision control operations without leaving the design environment or learning a new interface.

For most SoC design teams, given the large amount of design data generated, and the increased number of globally dispersed designers, disk space storage remains a major concern. A HCM such as SOS7 works hard to ensure that the size of the repository remains as small as possible. It achieves this objective by intelligently using the notion of symbolic links to optimize disk space usage for static libraries and design files. All the design files in the designer’s workspace remain as read-only symbolic links which minimizes the disk usage considerably. It is only when the designer wants to edit the file that a writable view of the design file is made available in the workspace.

The take away from all of this is that with the advent of more complex SoCs being designed for IoT applications, hardware configuration management will no longer just be for the big enterprises. Even small teams will need to embrace HCM, not only for design complexity, but for the capability to be able to do safety critical designs that require an audit trail and good version control. And remember if you are a startup, you likely will be hoping to be acquired for your IP. Being able to show that your design process and data are clean and in control can make all the difference to an acquiring company as to whether your IP is considered valuable or a pile bones that only a few people can make work.

This all bodes well for ClioSoft and their DM solutions and I expect we will be hearing more from them as the IoT revolution continues to explode.

February 27, 2018

Connecting Coherence

Connecting Coherence
by Bernard Murphy on 02-27-2018 at 7:00 am
Categories: AI, Arteris, IP
5 Comments

If a CPU or CPU cluster in an SoC is the brain of an SoC, then the interconnect is the rest of the central nervous system, connecting all the other processing and IO functions to that brain. This interconnect must enable these functions to communicate with the brain, with multiple types of memory, and with each other as quickly and predictably as each function requires. But it must also be efficient and ensure error-free operation.

Pulling off this trick has led to plethora of bus protocol standards, most widely represented by the AMBA family, now complemented by CCIX, which I’ll get to later. There’s a nice summary of the various AMBA protocols here, ranging from APB and ASB, through multiple flavors of AHB and multiple flavors of AXI, all the way up to ACE (also in a couple of flavors) and finally CHI. Why so many? Because you simply can’t serve in one protocol the needs for functions running at tens of MHz to functions running at GHz, and quality of service (QoS) ranging from best-effort (e.g. web response) to guaranteed (e.g. phone-call).

Network-on-chip (NoC) architectures, like the FlexNoC solution from Arteris, have become pervasive in mixed-protocol SoC designs because of the flexibility, performance, QoS and layout- and power-efficient advantages they offer in in contrast to more traditional switch-matrix solutions. You don’t need to construct tiered hierarchies of interconnect to bridge between different protocols; the NoC architectures seamlessly manages bridging and communication and can be tuned to deliver the PPA and QoS you need.

These days, there’s another wrinkle: Cache-coherent protocols have become popular thanks to the appearance of CPU clusters and other devices which need to communicate with those systems. When cores read and write memory, they do so first to their caches as a fast short-cut to reading and writing main memory. But if a core updates memory address X in its private cache just before a function F reads X, from its private cache or directly from main memory, then F is going to read the wrong value. Cache-coherency protocols manage these potential mismatches through a variety of techniques to ensure that memory views stay in sync when needed. The ACE and CHI protocols were introduced to cover this need; ACE first then CHI later to handle the more complex configurations appearing in more recent SoCs.

Now of course many design enterprises have a mix of IPs with either ACE interfaces or CHI interfaces. Arteris introduced their Ncore version 3 cache coherent interconnect at the October 2017 Linley conference to manage both ACE and CHI protocols in one interconnect, so you can manage a complete cache-coherent domain with just one interconnect solution. This is technology is very configurable, not just in the expected parameters but also in topology. Ncore 3 supports tree, ring and mesh topologies and even a 3D options, all allowing for different ways to manage bandwidth, latency and fault-tolerance.

Typically, your whole design won’t require cache-coherence; much of what you repurpose from legacy subsystems (or even many new subsystems) won’t depend on this capability. You can connect all of those non-coherent subsystems and hardware accelerators using the standard FlexNoC solution, but again with a wrinkle: A hardware accelerator/sub-subsystem in this non-coherent domain can share address space with the coherent domain, allowing memory references from that accelerator/subsystem to be coherent. You accomplish this by connecting these non-coherent subsytems to the Ncore 3 fabric through interfaces containing proxy caches, which loops them into the coherence management logic. You can even connect multiple non-coherent accelerators to a single proxy cache, thereby creating a cluster that can interact with the rest of the system as a coherent peer to the cache-coherent CPU clusters..

Kurt Shuler (VP Marketing at Arteris) told me that this need to integrate non-coherent subsystems and accelerators with the coherent domain is becoming increasingly important in machine-learning use-cases. As the number of hardware accelerators required to process neural net and image processing algorithms increases, it become harder to manage data communications without using cache coherence for critical parts of the system. Incidentally, it’s also possible to connect, cache coherently, to other die/devices though the CCIX interface (in a 2.5D/3D assembly solution for example). Ncore 3 supports this kind of connection with a CCIX interface connecting coherent domains between multiple chips.

There is one more important set of capabilities in Ncore 3 that are highly relevant to automotive or other safety-critical applications. This solution provides (within the fabric) ECC generators and checkers for end-to-end data protection, intelligent unit duplication and checking, similar to dual-core lockstep (DCLS), and a fault controller with BIST that is automatically configured and connected based on the designer’s data protection and hardware duplication settings. The capabilities can be combined to provide sufficient diagnostic coverage to meet automotive ISO 26262 functional safety certification requirements, as well as the more general IEC 61508 specification.

There’s a lot of technology here which should be immediately interesting to anyone building heterogeneous coherent/non-coherent SoCs and anyone wanting to build added safety into those systems. You can learn more HERE.

February 26, 2018

Developing Affordable IoT Systems

Developing Affordable IoT Systems
by Daniel Payne on 02-26-2018 at 12:00 pm
Categories: EDA, IoT, Siemens EDA
3 Comments

The IoT market opportunities in segments like wearables, vehicles, home, cities and industrial are all growing thanks to the combination of semiconductors, sensors, software and systems technology. New hardware designs for IoT edge devices appear on a daily basis, and the companies behind these new products can often be start-ups or just a handful of people in a larger company doing something totally different. Of course to run a successful business you have to manage cash flow, so ideally when starting a new IoT project the expenses need to be managed closely during the design phase. Maybe you need to get an early IoT prototype completed as proof of concept in order to secure funding for production.

IC Insightsproduced a report in June 2017 that showed that the IoT market size in 2016 was $74.6 billion, project to reach $124.1 billion by 2020 in the five categories mentioned above. The IoT edge market doesn’t include gateways, servers, computers, smartphones or tablets.

The five IoT market segments fuel semiconductor revenue in the following proportions where smart cities is the largest segment at 59% or $10.82 billion, followed by Industrial IoT at $4.02 billion and connected vehicles at $2.14 billion:

Custom SoCs are a popular IoT implementation approach for edge devices in order to get the most battery life, performance, lightest weight or smallest sized product. Alternate approaches like placing discrete components on a PCB may not meet requirements. Using a custom SoC does provide several benefits over discrete parts, like:

Lower BOM costs
Smallest size
Lowest power, longer battery life
Higher performance
Better reliability
No more obsolete components
Greater IP protection, harder for competitors to copy
Higher barriers to entry for your competitors

Before you get all enamored with the idea of developing a custom SoC it is wise to consider your costs, market size and segmentation, time to market, your competitors and the proper process node. Fabricating with a 180nm node is much cheaper than choosing to use 28nm, plus with 180nm you still use 3.3V supplies which provide a high dynamic range and better noise margins, something quite useful for RF antennas.

You’ll hear terms like Non-recurring Engineering (NRE) which include the price of EDA design software, semiconductor IP blocks from 3rd parties and the first silicon run to get your samples. Mentor – a Siemens business, provides a 30 day, no cost evaluation of their Tanner EDA tools for design and simulation of your custom SoC.

Schematic capture of AMS design using S-Edit
Processor IP – Arm Cortex-M0 or Arm Cortex-M3
Analog simulation using T-Spice
Digital simulation using ModelSim

Once your proof of concept is ready the next step is to begin implementation using software tools and semiconductor IP. Here’s the flow from Mentor:

Pushing down into the EDA tooling box there are four distinct engineering tasks:

IC design
Embedded Software
System Exploration
PCB Design

Analog Mixed-Signal (AMS) design and MEMs design are done with the Tanner EDA tools, and this is also where you model all of the IoT sensors. Here’s more detail on what the AMS IC design flow looks like:

If you’re IoT device needs to measure something like pressure, rotation, acceleration, speed or humidity then MEMS can be modeled in 2D and 3D then analyzed for physical effects.

For embedded software development Mentor Embedded has a real-time operating system (RTOS) and other tools for IoT edge devices. The Nucleus RTOS is well-equipped for battery powered IoT devices and has been used in some 3 billion devices so far. During embedded software development you would use Sourcery CodeBench:

With Sourcery CodeBench your team can use micro-controllers or microprocessors, then understand system execution, measure performance and even debug your apps.

For system-level design and documentation Mentor has the SystemVision Cloud tool that can model both electronics and mechatronics systems, then simulate them so that you can explore the best design approach.

To finally place your SoC and sensors onto a PCB it’s time to use software called PADS Standard, which has both schematic capture and board layout features at an affordable price.

The most popular processor architecture in the world comes from Arm and they have put together a program called DesignStart Evalthat allows you to design and prototype at no cost, then when you’re ready for production you upgrade to DesignStart Pro.

Having IC samples produced at a low cost can be accomplished with multi-project wafers (MPW), where you are sharing the IC mask costs with other companies onto the same silicon wafer. Foundries and companies like MOSIS, eSilicon and EUROPRACTICE can assist you with the MPW logistics. It costs about $16K to get 45 IC samples on a 180nm process, according to EUROPRACTICE, while the second order of 45 samples has an even lower price of $2K.

Your particular SoC for IoT applications may have unique requirements that drive up the cost like adding more IP blocks, including design consulting, needing a smaller geometry process, needing more EDA tools, PCB fabrication, or more analysis of MEMS.

Full production is the final step after your proof of concept has been accepted and raised enough capitol, so you choose a foundry partner and get quotes for mask costs and production. At the 180nm node you can expect mask costs to be around $150K, while more advanced nodes like 90nm you can expect mask costs of $500K.

Summary
The IoT market is very promising and with the right approach you can minimize engineering costs for both a proof of concept and into production using vendors like Mentor and Arm.

There’s a 14 page White Paper from Mentor on this topic, available to download.

February 26, 2018November 22, 2019

The hierarchical architecture of an embedded FPGA

The hierarchical architecture of an embedded FPGA
by Tom Dillinger on 02-26-2018 at 7:00 am
Categories: eFPGA, Flex Logix, IP

The most powerful approach to managing the complexity of current SoC hardware is the identification of hierarchical instances with which to assemble the design. The development of the hierarchical design representation requires judicious assessment of the component definitions. The goals for clock distribution, power management, and circuit/routing utilization require partitioning that is neither too fine nor too coarse – e.g., the management of multiple power domains within a large partition is difficult, while too fine a partitioning results in more pin constraints to manage and fewer opportunities for timing-driven physical design optimizations.

It struck me that the tradeoffs to the hierarchical representation directly apply to the architecture of an FPGA, as well. I recently chatted with Cheng Wang, SVP of Engineering at Flex Logix Technologies, about how they approached the hierarchical decomposition of the design complexity of their embedded FPGA cores – it was an extremely enlightening discussion.

First, I needed to study up on the typical hierarchical architecture of an FPGA. The programmable logic is implemented with n-input look-up tables (LUT’s). A logic block consists of multiple LUT’s, with additional storage bits. Dedicated local routing connects the LUT’s within the block. The traditional FPGA uses an island style architecture, with logic blocks separated by wiring channels. (This architecture is also denoted as a “mesh” style design.)

Figure 1. General FPGA island architecture. (From: Rose and Betz, “How Much Logic Should Go in an FPGA Logic Block?”, IEEE D&T of Computers, January 1998.)

The input and output signals of logic blocks are connected to segmented wires in the channels. The logic block-to-channel wire assignment is denoted as the “connection box”. The pins of the logic block are connected to a percentage of the wires in the channel (Fc), typically between 50% and 100% of the channel track width.

Figure 2. Expanded view of the connection box and switch box of an FPGA mesh architecture. (From: D. Markovic, “FPGA Architecture”, UCLA EE216B.)

The figure above depicts “un-segmented” channel wires and pass transistors for logic block connections. Alternatively, wire segments are commonly used – the figure below illustrates a block input pin connected to three segments, with the active segment using a buffer + MUX shown in red.)

Figure 3. Segmented wires in the channel connected to a logic block input. (From: V. Betz, “FPGA Architecture”, University of Toronto).

The channel wires are connected to programmable switches, located in the “Switch Box”. The Switch Box design defines how channel wires may connect to wires on other sides – the “flexibility” of the switch box is a parameter that indicates how many other wires are potential connections.

Note in the figures above that clock wires are not shown – the common approach is to include specific global and local wiring tracks for clocks to the logic block storage elements. The dedicated clocks include distributed buffering and clock management units.

FPGA architecture design involves balancing multiple tradeoffs related to the implementation hierarchy:

Logic block functionality needs to address performance, utilization, and routability. A fine-grained block design will require more programmable interconnect resources, more switches, and correspondingly, less performance. A very rich (coarse-grained) logic block design will be inefficient for small logic functions. The goal is to find an optimum logic block functionality, which aligns with the capabilities of the logic synthesis and physical design tools. FPGA implementations have commonly ranged from 4-10 LUT’s connected locally in the logic block. As FPGA synthesis has improved, the common LUT design has also evolved, from 4- to 5- to 6-input (with dual 5-input) functionality, as is the case for the current Flex Logix EFLX architecture.

FPGA design has also evolved to include special-purpose blocks. The hierarchical implementation needs to be able to readily support the unique programmable logic design of arithmetic and DSP functions.

The FPGA routing architecture needs to provide sufficient resources to satisfy both utilization and performance targets.

With that background, I asked Cheng, “How did Flex Logix approach these implementation hierarchy decisions?”

He answered, “Rather than the island architecture, we adopted a hierarchical switch network. The number of switch connections required for routes with high locality is reduced, improving performance.”

Figure 4. Hierarchical switch network for FPGA connectivity. (From: US Patent 9,503,092.)

“Of specific importance is the radix and depth of the hierarchical network tree, which were chosen to optimize the overall routability – the top level of the switch network utilizes the mesh routing of the island architecture.”, Cheng continued.

“What other hierarchical tradeoffs were faced?”, I asked.

Cheng replied, “We recognized two key design goals for embedded FPGA IP. For many applications, customers need to implement power gating on some of their eFPGA functionality. And, for performance, customers require optimal, low-skew clock distribution, with support for integrating multiple clock domains. To meet these requirements, we introduced a hierarchical component denoted as a tile.”

The Flex Logix hierarchical tile functionality includes ~2,500 6-input, 2-output LUT’s (16nm), with two optional flops per LUT.

Cheng highlighted, “Within a tile, the programmable logic can be power gated for a low-power application. The tile design includes an optimized H-tree clock, supporting either one or two clock domains. We implemented a novel method for balanced H-tree construction to distribute a clock input across multiple tiles.”

Figure 5. Clock distribution within and between tiles, for balanced H-tree distribution. A clock may enter a tile at any edge, with multiplexing to distribute through a consistent number of buffers throughout multiple tiles. (From: US Patent 9,882,568.)

“With the introduction of the hierarchical switch network and the tile hierarchy for clock and power management, we needed to develop our own netlist placement and routing technology. These algorithms provide improved performance, with a reduced number of switches for logic localized to the lower levels of the hierarchical network.”, Cheng said.

The design of eFPGA IP requires supporting a range of end-customer logic capacities with aggressive utilization and performance targets, while supporting varied clock and power domain designs. The introduction of the hierarchical “tile” achieves these goals.

The next time we get together for coffee, Cheng is going to share how the tile boundary design enables efficient signal communication between adjacent tiles – it should be an interesting discussion.

For more information on these eFPGA hierarchical implementation design options, please follow this link.

-chipguy

LithoVision 2018 The Evolving Semiconductor Technology Landscape and What it Means for Lithography

LithoVision 2018 The Evolving Semiconductor Technology Landscape and What it Means for Lithography
by Scotten Jones on 02-25-2018 at 5:00 pm
Categories: Events, Lithography, Semiconductor Services, TechInsights
10 Comments

I was invited to present at Nikon’s LithoVision event held the day before the SPIE Advanced Lithography Conference in San Jose. The following is a write up of the talk I gave. In this talk I discuss the three main segments in the semiconductor industry, NAND, DRAM and Logic and how technology transitions will affect lithography. Please note the slide numbering used in the article is matched to the slide numbers in the presentation.
Continue reading “LithoVision 2018 The Evolving Semiconductor Technology Landscape and What it Means for Lithography”

February 25, 2018

First Line of Defense for Cybersecurity: AI

First Line of Defense for Cybersecurity: AI
by Ahmed Banafa on 02-25-2018 at 7:00 am
Categories: AI, IoT, Security

The year 2017 wasn’t a great year for cyber-security; we saw a large number of high-profile cyber attacks; including Uber, Deloitte, Equifax and the now infamous WannaCry ransomware attack, and 2018 started with a bang too with the hackingof Winter Olympics. The frightening truth about increasingly cyber-attacks is that most businesses and the cybersecurity industry itself are not prepared. Despite the constant flow of security updates and patches, the number of attacks continues to rise.

Beyond the lack of preparedness on the business level, the cybersecurity workforce itself is also having an incredibly hard time keeping up with demand. By 2021, there are estimated to be an astounding 3.5 million unfilled cybersecurity positions worldwide, the current staff is overworked with an average of 52 hours a week, not an ideal situation to keep up with non-stop threats.

Given the state of cybersecurity today, the implementation of AI systems into the mix can serve as a real turning point. New AI algorithms use Machine Learning (ML) to adapt over time, and make it easier to respond to cybersecurity risks. However, new generations of malware and cyber-attacks can be difficult to detect with conventional cybersecurity protocols. They evolve over time, so more dynamic approaches are necessary.

Another great benefit of AI systems in cybersecurity is that they will free up an enormous amount of time for tech employees. Another way AI systems can help is by categorizing attacks based on threat level. While there’s still a fair amount of work to be done here, but when machine learning principles are incorporated into your systems, they can actually adapt over time, giving you a dynamic edge over cyber criminals.

Unfortunately, there will always be limits of #AI, and human-machine teams will be the key to solving increasingly complex #cybersecurity challenges. But as our models become effective at detecting threats, bad actors will look for ways to confuse the models. It’s a field called adversarial machine learning, or adversarial AI. Bad actors will study how the underlying models work and work to either confuse the models — what experts call poisoning the models, or machine learning poisoning (MLP) – or focus on a wide range of evasion techniques, essentially looking for ways they can circumvent the models.

Four Fundamental Security Practices
With all the hype surrounding AI we tend to overlook a very important fact. The best defense against a potential AI cyber-attack is rooted in maintaining a fundamental security posture that incorporates continuous monitoring, user education, diligent patch management and basic configuration controls to address vulnerabilities. All explained below:

Identifying the Patterns
AI is all about patterns. Hackers, for example, look for patterns in server and firewall configurations, use of outdated operating systems, user actions and response tactics and more. These patterns give them information about network vulnerabilities they can exploit.

Network administrators also look for patterns. In addition to scanning for patterns in the way hackers attempt intrusions, they are trying to identify potential anomalies like spikes in network traffic, irregular types of network traffic, unauthorized user logins and other red flags.

By collecting data and monitoring the state of their network under normal operating conditions, administrators can set up their systems to automatically detect when something unusual takes place — a suspicious network login, for example, or access through a known bad IP. This fundamental security approach has worked extraordinarily well in preventing more traditional types of attacks, such as malware or phishing. It can also be used very effectively in deterring AI-enabled threats.

Educating the Users
An organization could have the best monitoring systems in the world, but the work they do can all be undermined by a single employee clicking on the wrong email. Social engineering continues to be a large security challenge for businesses because workers easily can be tricked into clicking on suspicious attachments, emails and links. Employees are considered by many as the weakest links in the security chain, as evidenced by a recent survey that found that careless and untrained insiders represented the top source of security threats.

Educating users on what not to do is just as important as putting security safeguards in place. Experts agree that routine user testing reinforces training. Agencies must also develop plans that require all employees to understand their individual roles in the battle for better security. And don’t forget a response and recovery plan, so everyone knows what to do and expect when a breach occurs. Test these plans for effectiveness. Don’t wait for an exploit to find a hole in the process.

Patching the Holes
Hackers know when a patch is released, and in addition to trying to find a way around that patch, they will not hesitate to test if an agency has implemented the fix. Not applying patches opens the door to potential attacks — and if the hacker is using AI, those attacks can come much faster and be even more insidious.

Checking Off the Controls
The Center for Internet Security (CIS) has issued a set of controls designed to provide agencies with a checklist for better security implementations. While there are 20 actions in total, implementing at least the top five — device inventories, software tracking, security configurations, vulnerability assessments and control of administrative privileges — can eliminate roughly 85 percent of an organization’s vulnerabilities. All of these practices — monitoring, user education, patch management and adherence to CIS controls — can help agencies fortify themselves against even the most sophisticated AI attacks.

Challenges Facing AI in Cybersecurity

AI-Powered Attacks
AI/Machine Learning (ML) software has the ability to “learn” from the consequences of past events in order to help predict and identify cybersecurity threats. According to a report by Webroot, AI is used by approximately 87% of US cybersecurity professionals. However, AI may prove to be a double-edged sword as 91% of security professionals are concerned that hackers will use AI to launch even more sophisticated cyber-attacks.

For example, AI can be used to automate the collection of certain information — perhaps relating to a specific organization — which may be sourced from support forums, code repositories, social media platforms and more. Additionally, AI may be able to assist hackers when it comes to cracking passwords by narrowing down the number of probable passwords based on geography, demographics and other such factors.

More Sandbox-Evading Malware
In recent years, sandboxing technology has become an increasingly popular method for detecting and preventing malware infections. However, cyber-criminals are finding more ways to evade this technology. For example, new strains of malware are able to recognize when they are inside a sandbox, and wait until they are outside the sandbox before executing the malicious code.

Ransomware and IoT
We should be very careful not to underestimate the potential damage IoT ransomware could cause. For example, hackers may choose to target critical systems such as power grids. Should the victim fail to the pay the ransom within a short period of time, the attackers may choose to shut down the grid. Alternatively, they may choose to target factory lines, smart cars and home appliances such as smart fridges, smart ovens and more.

This fear was realized with a massive distributed denial of service attack that crippled the servers of services like Twitter, NetFlix , NYTimes, and PayPal across the U.S. on October 21st , 2016. It’s the result of an immense assault that involved millions of Internet addresses and malicious software, according to Dyn, the prime victim of that attack. “One source of the traffic for the attacks was devices infected by the Mirai botnet”. The attack comes amid heightened cybersecurity fears and a rising number of Internet security breaches. Preliminary indications suggest that countless Internet of Things (IoT) devices that power everyday technology like closed-circuit cameras and smart-home devices were hijacked by the malware, and used against the servers.

A Rise of State-Sponsored Attacks
The rise of nation state cyber-attacks is perhaps one of the most concerning areas of cyber-security. Such attacks are usually politically motivated, and go beyond financial gain. Instead, they are typically designed to acquire intelligence that can be used to obstruct the objectives of a given political entity. They may also be used to target electronic voting systems in order to manipulate public opinion in some way.

As you would expect, state-sponsored attacks are targeted, sophisticated, well-funded and have the potential to be incredibly disruptive. Of course, given the level of expertise and finance that is behind these attacks, they may prove very difficult to protect against. Governments must ensure that their internal networks are isolated from the internet, and ensure that extensive security checks are carried out on all staff members. Likewise, staff will need to be sufficiently trained to spot potential attacks.

Shortage of Skilled Staff
By practically every measure, cybersecurity threats are growing more numerous and sophisticated each passing day, a state of affairs that doesn’t bode well for an IT industry struggling with a security skills shortage. With less security talent to go around, there’s a growing concern that businesses will lack the expertise to thwart network attacks and prevent data breaches in the years ahead.

IT infrastructure
A modern enterprise has just too many IT systems, spread across geographies. Manual tracking of the health of these systems, even when they operate in a highly integrated manner, poses massive challenges. For most businesses, the only practical method of embracing advanced (and expensive) cybersecurity technologies is to prioritize their IT systems and cover those that they deem critical for business continuity. Currently, cybersecurity is reactive. That is to say that in most cases, it helps alert IT staff about data breaches, identity theft, suspicious applications, and suspicious activities. So, cybersecurity is currently more of an enabler of disaster management and mitigation. This leaves a crucial question unanswered — what about not letting cybercrime happen at all?

The Future of Cybersecurity and AI
In the security world AI has a very clear-cut potential for good. The industry is notoriously unbalanced, with the bad actors getting to pick from thousands of vulnerabilities to launch their attacks, along with deploying an ever-increasing arsenal of tools to evade detection once they have breached a system. While they only have to be successful once, the security experts tasked with defending a system have to stop every attack, every time.

With the advanced resources, intelligence and motivation to complete an attack found in high level attacks, and the sheer number of attacks happening every day, victory eventually becomes impossible for the defenders.

The analytical speed and power of our dream security AI would be able to tip these scales at last, leveling the playing field for the security practitioners who currently have to constantly defend at scale against attackers who can pick a weak spot at their leisure. Instead, even the well-planned and concealed attacks could be quickly found and defeated.

Of course, such a perfect security AI is some way off. Not only would this AI need to be a bona fide simulated mind that can pass the Turing Test, it would also need to be a fully trained cyber security professional, capable of replicating the decisions made by the most experienced security engineer, but on a vast scale.

Before we reach the brilliant AI seen in Sci-Fi, we need to go through some fairly testing stages – although these still have huge value in themselves. Some truly astounding breakthroughs are happening all the time. When it matures as a technology it will be one of the most astounding developments in history, changing the human condition in ways similar to and bigger than, electricity, flight, and the Internet, because we are entering the AI-era.

Herb Reiter on the Challenges of 2.5D ASIC SiPs

Herb Reiter on the Challenges of 2.5D ASIC SiPs
by Daniel Nenni on 02-23-2018 at 12:00 pm
Categories: Events, Open-Silicon, Semiconductor Services

Years ago my good friend Herb Reiter promoted the importance of 2.5D packaging to anybody and everybody who would listen including myself. Today Herb’s vision is in production and the topic of many papers, webinars, and conferences. According to Herb, and I agree completely, advanced IC packaging is an important technology for leading edge chip companies who are focused on high performance and low power. TSMC agrees of course supported by their CoWoS and INFOs packaging technology which has been adopted by leading semiconductor companies (Apple, Nvidia, Xilinx, etc…).

The latest trend for 2.5D packaging is the leading ASIC companies enabling the masses and as we write about it the word is spreading quickly to emerging AI chip companies (Nervana, DeePhi, Mythic, Groq) and the systems companies that are now doing their own chips (Google, Amazon, Facebook). On March 6[SUP]th[/SUP] you have the opportunity to hear it from Herb himself via a webinar sponsored by leading ASIC company Open-Silicon:

Solutions and Strategies to Mitigate the Physical Design, Assembly and Packaging Challenges of 2.5D ASIC SiPs

This Open-Silicon webinar, moderated by Herb Reiter of eda 2 asic Consulting, Inc., will address the unique physical design, assembly and packaging challenges of 2.5D ASIC SiPs, and outline the proven solutions and strategies that are available to mitigate these issues in order to successfully ramp ASIC SiP designs into volume production. Using a 2.5D HBM2 ASIC SiP as a case study, the panelists will cover all aspects of physical design of the interposer, ASIC, signal integrity analysis and STA, rail analysis and power integrity analysis. They will also address the package design, assembly and testing both at the wafer level and the SiP level.

The panelists will emphasize the importance of understanding the entire 2.5D ASIC SiP manufacturing supply chain ecosystem and all of its stakeholders, such as the HBM2 memory, ASIC, interposer, package substrate, assembly house, foundry and more. Attendees will learn about system planning, 2.5D ASIC SiP requirements and implementation strategies, package assembly flows, verification, test, and signoff. By understanding the implementation and manufacturing challenges associated with 2.5D ASIC SiPs and the solutions available, designers and architects will be better equipped to achieve high volume manufacturing with lower risk, higher performance and faster time-to-market.

This webinar is ideal for chip designers and SoC architects of the next generation of high bandwidth applications in HPC, networking, deep learning, virtual reality, gaming, cloud computing and data centers.

Herb has more than 30 years of semiconductor experience and he has been a tireless promoter of 2.5D packaging for many years. Herb writes for and works with industry organizations on 2.5D work groups and events at conferences around the world. I have worked with Herb on various conferences and recommend him professionally at every opportunity. Herb’s company EDA 2 ASIC Consulting started with single die designs in 2002 and now helps with the transition to multiple dies in a single package. This is one webinar that you don’t want to miss, absolutely.

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 130 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com

February 23, 2018December 27, 2023

An AI assist for 5G enhanced Mobile Broadband for mobile platforms

An AI assist for 5G enhanced Mobile Broadband for mobile platforms
by Bernard Murphy on 02-23-2018 at 7:00 am
Categories: AI, Ceva, IP, Mobile

If you’re not up-to-speed on 5G, there are three use-cases: eMBB(enhanced mobile broadband) for mobile platforms (Gbps rates, immersive gaming, VR, AR – spectrum usage also extends up to mmWave, but that’s a different topic), mMTCfor massive machine type communication (ultra-low cost, ultra-low power, very dense networks) and URLLC or ultra-reliable low latency communication (for tele-surgery, traffic safety and aspects of industrial automation). CEVA is announcing their PentaG platform in support of eMBB at Mobile World Congress (MWC) next week.

Leveraging their skills in DSP IP, CEVA has built considerable experience and product road-time in wireless standards support, from 2G on up, and are now at 9B+ devices shipped to date across their product lines. Which means they already have a lot of credibility with the handset and base-station OEMs who are preparing for 5G. I blogged last year (One Cellular Technology to Rule Them All) on their work in this area in support of base-stations. Now they’re announcing what they’re doing in support of UEs (user-equipment aka mobile devices to the rest of us).

Enhanced Mobile Broadband (eMBB) is a tough standard to support; versus LTE it requires much higher capacity and bandwidth, much lower latency, multi-mode/RAT support for smooth evolution / coexistence with existing standards, and support for massive MIMO – multi antennas at both base-station and UE. But looks like it will be worth the effort. CCS Insight expects 1B subscribers by 2023 and 2.5B by 2025. The network operators, handset makers and semis are already actively engaging, most in support of the 5G-NR priority while Verizon apparently is still doing its own thing (with support from some cities and countries) in the mmWave part of the standard.

Emmanuel Gresset (Director Biz Dev in the CEVA Wireless Unit) told me that an important aspect in providing support for 5G in these relatively early days when the standard is still evolving is to balance between performance and flexibility. They put a lot of effort into looking at tradeoffs, and in ability for customers to reuse legacy software with enhancements only where needed for eMBB. He cited as an example their choice to use the already widely-deployed XC4500 in the Vector MAC unit processor (VMU). This has 64 MACs versus their XC12 with more MACs but the XC12 solution might have implied more software rework for existing customers. Instead they added extensions to the 4500 architecture to support 5G with minimal disruption to legacy code (and they incidentally pick-up the MAC shortfall in the VMU).

One part of the PentaG solution I found especially interesting is an AI processor based on neural nets which they use for link adaptation. Adaptation is a phase where the UE and the base-station communicate to optimize the quality of the link; the base-station sends information, the UE receives and looks at all options to optimize that signal, then sends back to the base-station to guide reconfiguring the link.

In earlier standards, the UE method to decide how to optimize was algorithmic. As standards evolved this had to be extended to algorithms plus lookup tables tuned to needs. As standards evolved further (LTE-Advanced), those tables had to grow significantly to meet link quality expectations. For CEVA it was very unclear that this approach could scale into 5G without loss in quality, hurting both transmission rates and power. PentaG instead uses a neural net approach which can be trained (by the OEM) to optimize adaptation. CEVA demonstrate this in improved throughput and significantly reduced power over their earlier-generation (LTE-A) solution. They also believe this approach will be much more flexible in adjusting to evolution in the 5G standard.

The VMU is designed to handle the massive MIMO requirement of 5G where you have a greatly increased number of antennas on the base-station and on the UE, resulting in 5X the channel bandwidth to be processed that you have in LTE. 5G MIMO also means that the UE has to deal with 10X the beamforming options it had to handle in LTE. The VMU assists here, through parallelism, a matrix engine and yet more MAC processing, again providing higher performance and lower power than earlier generation solutions.

A cluster of CEVA-X2 DSPs optimizes modem control for latency and performance across multi-RAT/5G and multiple simultaneous events. It also provides an optimized connect solution/queue manager to manage traffic housekeeping between units directly without needing to get bogged down in interrupt-driven transfers – yet again important in managing throughput and latency to 5G expectations.

Finally, the platform – and it is a platform, multiple IPs and software – offers a set of hardware accelerators for the encode and decode functions required for 5G: polar and LDPC. They also offer software libraries optimized for 5G (also for LTE-A / WCDMA / TD-SCDMA) and a HW/SW development kit with reference board. The software also includes the AI training suite that an OEM would use to train the neural nets. Emmanuel stressed that PentaG is not a full modem – you still have to add RF and cache for example. But it certainly seems to be the heart and soul of a 5G eMBB modem.

At MWC next week, CEVA will be showing an impressive demo based on a UE with 4 antennas and a base-station with 8 antennas. The UE will be in a car driving in the city, among high rises with quickly varying reception, at times with no line of sight to the base-station. They’ll show how actual reception/transmission rates compare to theoretical optimum values. Sounds like they’re pretty confident. You can learn more about PentaG HERE. If you want to learn more about 5G in general, there’s a useful reference HERE.

February 22, 2018

Mentor Tessent MissionMode Provides Runtime DFT for Self-Correcting Automotive ICs

Mentor Tessent MissionMode Provides Runtime DFT for Self-Correcting Automotive ICs
by Mitch Heins on 02-22-2018 at 12:00 pm
Categories: Automotive, EDA, Siemens EDA

The automotive industry continues push the limits on how “smart” we can make our vehicles and from that, it follows as to how smart we can make the electronics in the vehicles. When I think of smart cars (and smart automotive ICs) I typically think of things like advanced driver-assistance systems (ADAS) that use AI and neural networks for image recognition and automated driving controls. However, there is another level intelligence going on inside the ICs that is just as critical but maybe not so well known.

What I’m alluding to is the use of design-for-test (DFT) technologies in ICs that do self-monitoring, error detection and self-correction. While perhaps not as glamorous as AI or neural networks, these capabilities are essential technology to all ICs in safety-critical applications. Traditionally, DFT techniques have been used to improve the cost and coverage of post-manufacturing tests meant to ensure that chips don’t ship to customers with internal manufacturing defects. More recently however, DFT has grown to encompass a larger scope known as mission-mode testing.

Mission-mode testing entails self-diagnostic testing by chips during power-on, power-off and certain runtime scenarios. These tests are meant to check for errors that may have creep in over time while the chip is being used (e.g. errors caused by aging or environmental considerations or some unexpected or unplanned state, either accidental or nefarious). In-system test (IST) challenges are much like those seen at manufacturing test where we are dealing with large complex circuits with deeply embedded logic that can be hard to access and isolate. Additionally, IST also has the requirement of being able to run these tests in real time while accommodating required system response times and power budgets.

Mentor, a Siemens Business, has been working on this issue for their automotive customers and has recently added a new technology called Tessent MissionMode to their test-products portfolio. Tessent MissionMode has both design tool and IP components. The design tool portion is the Tessent Shell tool that enables designers to insert a MissionMode IST controller-IP into their chip designs. The controller block is a central control hub that connects and manages test blocks spread throughout the chip such as built-in-self-test (BIST) circuitry for memories (MBIST), logic (LBIST) and other on-chip test industry-interface compliant structures. These test blocks monitor and check the chip’s functions, returning status to the controller on an ongoing basis. If trouble is spotted the controller sends a signal to the chip’s main CPU for action.

Because systems-on-chip (SoCs) are so complex, Mentor has taken a hierarchical approach to their testing architecture that lets engineers break their designs into hierarchical zones within the chip that can be alternately enabled or disabled using segment-insertion bit (SIB) IP switch blocks. Each test block can be a different type of test. Test blocks can also be hierarchical themselves. The MissionMode controller communicates with different test blocks using the industry standard IJTAG protocol, telling each test block what tests to perform and when to perform them. Negative results can be communicated back to the main CPU which can then take the appropriate action to record, report or fix the problem. The hierarchical nature of the test network allows designers to ensure low latency between the test controller and various test blocks, which is important as time budgets for in-system tests are typically small.

This self-diagnostic and self-correction or mitigation functionality has many applications. Errors can be reported to an automobile’s main controller, which in turn can warn drivers of a problem in real-time and even take corrective action to self-repair the problem or return to a safe state. Additionally, data can be sent to service centers and manufacturers for follow-up action, root-cause analysis and design corrections to be captured in future versions of the chip. Finding the source of defects and fixing them is imperative for the automotive industry as it strives to achieve zero-defect ICs for autonomous vehicles.

The Tessent MissionMode IP and other Mentor DFT blocks provide users with an ISO 26262 qualification report to simplify chip ASIL certification and have been tuned to work with the rest of Mentor’s DFT design tool solutions. In case you are wondering if this is all just hype, or if anyone is using this technology, you have no further to look than to a recent announcement by Mentor and Renesas where Renesas touted their use of Mentor Tessent products to reduce their costs and improve the quality of their automotive-IC manufacturing and in-systems tests (see link below).

So, not only are automobiles becoming smart enough to detect objects and avoid them, but the ICs inside those vehicles are also becoming smart enough to intelligently monitor themselves and act should things take a turn for the worse. Remembering the adage, a chain is only as strong as its weakest link, Mentor’s Tessent MissionMode offering is all about ensuring that the ICs in your automobiles won’t be that weak link.

February 22, 2018August 19, 2020

A Development Lifecycle Approach to Security Verification

A Development Lifecycle Approach to Security Verification
by Bernard Murphy on 02-22-2018 at 7:00 am
Categories: EDA, IoT, Mobile, Security, Tortuga Logic

We have become accustomed to the idea that safety expectations can’t be narrowed down to one thing you do in design. They pervade all aspects of design from overall process through analysis, redundancies in design, fault analytics and mitigation for faults and on-board monitors for reliability among other requirements and techniques.

Why shouldn’t similar concepts apply to security also? Here we don’t have an ISO 26262; we do have security IP and software, however design tools and methods in this space are somewhat piecemeal, leaving me at least feeling that our coverage of design best practices is rather patchy. Conversely the concept of best practices in design for softwaresecurity is already quite well established within certain enterprise levels like Microsoft.

Tortuga Logic aims to correct this. A venture that started in joint research between UCSD and UCSB, their approach builds on a top-down approach to security development. This starts by developing a threat model for the system, defining potential attack entry points, assumptions about resources attackers may have (money, time, etc.), and their ability to find exploits via those entry points given those resources. This threat model can be developed either by Tortuga’s hardware security engineers or by the chip design / architecture / security team. Examples of factors considered in the threat model include memory isolation, key management and secure boot configurations, from a high-level view all the way down to individual circuit components. This should be a living document, updated regularly during the design lifecycle.

The threat model is then a key input, along with the design RTL, to the Tortuga analysis / augmentation process. Using patented techniques based on a concept they call information flow, their products analyze for potential harmful data leakages in the chip design. This analysis does not require advance knowledge of suspected architecture vulnerabilities.

Jason Oberg, the CEO of Tortuga, pointed particularly to the Meltdown/Spectre issue and said that these problems are symptomatic of a broader lack of design-for-security methodologies which he believes Tortuga can address with this solution. He mentioned a number of markets where this will be important:

Aerospace and defense – Apparently this domain was a significant component in their research activity, especially around two topics: information assurance, where it is critical to ensure that you can properly contain secrets and microelectronics trust, where there is always a question around the trust you can place in 3[SUP]rd[/SUP] party cores, a very pressing concern when you’re building electronics to go in a missile for example.
Mobile applications – where security concerns are probably much more familiar to many of us: ensuring that secure boot cannot be compromised, correctly managing access control so that that a general-purpose CPU, for example, should not be able to read boot image authentication keys, and protecting customer content (passwords, mobile payment data etc)
Datacenters – where there is a proven concern around effective isolation of different customer processes potentially running on the same hardware in different VMs or in other shared resources in the datacenter. There have already been multiple reports of techniques to run side-channel attacks in these cases through cache probes and timing analyses.

From what I can deduce, to detect security weaknesses Tortuga’s analysis effectively instruments your design to help detect potential security problems in your downstream analysis, whether that be through simulation, emulation or formal methods (again, my guess). This seems to me to be a very powerful complement to security-aware design flows. You should probably check them out. You can learn more HERE.