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DAC 2018 Potpourri

DAC 2018 Potpourri
by Alex Tan on 07-03-2018 at 12:00 pm
Categories: Arm, EDA, Events, RISC-V

The venue
Despite of being held at the new three-story Moscone West building, this year 55th DAC in San Francisco bore many similarities as compared with last year’s. Similar booth decors and floorplan positioning of the big two, Synopsys and Cadence, which were across of each other and right next to the first floor entrance –although this time Synopsys had similar screen size for partner presentations as Cadence’s. There were also the same purple-dress magician and the (Penn &) Teller-look-alike comedian at two of the vendor booths; the end-of-each-day poster sessions competing with mouth-watering hors d’oeuvres; and some vendor giveaways luring DAC attendees in hope they also carry along the takeaways from partners’ 10-minute flash presentations. Likewise, many returning vendors and replays of product offerings with incremental updates.

Unique and new things at this year DAC
While from talking with many attendees the sentiment seems to be rather subdued on the exhibit floor, the sheer number of technical papers and behind-closed-door sessions still reflect a leap of enthusiasm in propagating AI, ML and cloud into the EDA space. Key EDA players shared their continued tools benchmarking and rolling out their fruitful collaborative efforts (such as Synopsys Fusion integration with Ansys’ RedHawk, Mentor Calibre-RTD with major P&R tools, Aldecwith its co-simulations, among others).

At this DAC, two seasoned Wall-street EDA/semiconductor analysts (Richard Valera from Needham and Jay Vleeschhouwer from Griffin Securities) were given the opportunity to share their EDA/semiconductor prognosis during Sunday’s DAC kick-off reception and at the Tuesday’s DAC Pavilion session, respectively. They are in agreement that EDA growth is there, although around mid single digit amidst further consolidation of players. Jay also noted that there are more cloud players participation in developing their own silicons (not only doing software developments).

There was Design Infrastructure Alley designated for cloud providers along with Design-on-Cloud pavilion to showcase their EDA on cloud collaborations. Out of the big three, Cadence offers the most comprehensive cloud-enabled solutions including different engagement models while Mentor embraced cloud by offering emulation capabilities on AWS. Despite good traction in addressing cloud technical related aspects such as security and scalability, I believe the cloud adoption is still at the exploration stage. Other than ideally providing capacity at peak demand, the business model portion is still evolving as it is quite a challenge to undo or align major customers existing on-premise capacities with a cloud expansion. On the other hand, it is good news and lowers barrier-of-entry for smaller design houses which may be more ready to embrace metric-based-usage model.

IP is getting more attention
Jay’s feedback on the IP resumption growth resonates well with a number of talks given during DAC. IP has its own ecosystem, encompassing a swath of enablers: from smallest footprint IP providers such as PLL from Silicon Creation to verification IP’s from Synopsys.

In the core IP segment, RISC-V is making a comeback and seems to showcase adopters and aligning a number of talks. Krste Asanovic, Chairman of RISC-V foundation and SiFive co-founder made the Skytalk speech 2 years ago in Austin DAC and it’s Dave Patterson turn this year to make a pitch. “Why open source compilers and operating systems but not ISAs?”, Dave touted. “..The thirst for open architecture that everybody could use and they look all over for the instruction sets and stumbled into ours and liked it and started using it without telling us about it…” Patterson says about his encounters with RISC-V early adopters a few years back. Once realizing of such thirst for an open architecture, it had prompted him and few others to try to make it happen by building the ecosystem through the RISC-V Foundation.

As Synopsys Aart de Geus stated at Silicon Valley SNUGthis year that action is happening at the interface, (Instruction Set Architecture) ISA is the most important interface in a computer system as it connects software to hardware. The motivation behind forming the RISC-V Foundation is also ensuring its openness. According to Rick O’Connor, its executive director, “…so the technology is not controlled by a single company or entity.” He mentioned that using ISA does not require membership or license. Only when it is used as part of non-open-source device or commercial products it requires a RISC-V trademark/license.

While it is a good addition to the core IP selection (as MIPS is now owned by Wave Computing) and Dave showed its anticipated volume ramp, it is still a bit early to make a significant impact on the existing IP-core ecosystem, which is currently being dominated by both X86 and ARM based architectures. Which one will be the leader? Perhaps this involves a bit of reading tea leaves, since it is impossible to predict which one will be dominating IoT and automotive applications.

But ARM has also recently aligned its organization to serve these two-market segments. I asked ARM’s John Ronco, VP & GM of Embedded & Auto Line of Business regarding the appeal of RISC-V instruction set ownership and customization in addressing security related needs, for example. He is not worried as adopters only gain control on the ISA, they still need to design the CPU.

Furthermore, he said “My view on that, vast majority of cases you don’t want to customize the instruction sets. There are two reasons…firstly, actually if you do that you’ll break the software ecosystem. One of the huge benefit of ARM is that you’ve got these vast network of tools/software companies that work on ARM platform…” Secondly, he believes adopters will be confined to incremental customization that offers no performance benefit as they have to ensure no deviations from its fundamental architecture.

ML and AI
At the conference, there were more progress shared by the EDA providers in embedding ML into their solutions. Synopsys shared incremental QoR gains and significant cycle time saving upon deploying ML (and three of their four Fusion interfaces: design, signoff, ECO), while Cadence announced augmenting ML on their characterization tool enabling smart interpolation of points and critical corners to also significantly reduce overall timing library generation. Likewise, Silvaco ML augmentation in behavioral Verilog-A spice modeling generation and its characterization tools has enabled less input collaterals and has reduced the required overall runtime.

As our electronics industry is venturing into the IoT and automotive while sustaining efforts for the upcoming mobile migration towards 5G network, there are many smaller solution providers at the exhibit showing either their niche point-tools or flexible design services. It seems that smaller product form factors, focused functionalities, IP availability and now cloud enablement may have enticed more participants into this foray. Let’s hope it will be more vibrant in Vegas next year!

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Dragonfly-NB2: You Can Have It All in Your IoT Device

Dragonfly-NB2: You Can Have It All in Your IoT Device
by Bernard Murphy on 07-03-2018 at 7:00 am
Categories: Ceva, IoT, IP

I wrote last month about CEVA’s Dragonfly-NB1 platform, a single-chip IoT solution supporting narrow-band cellular communication; this can meet aggressive total solution price-targets for high-volume deployment, long-range access and the low-power needed for 10+ year battery lifetimes. That solution, based on Release 13 of the standard (also known as NB-IoT or LTE Cat-NB1) saw quick uptake across multiple use-cases. Meantime, opportunities to improve on the standard led to Release 14 (also known as eNB-IoT or LTE Cat-NB2) which now is quickly becoming the mainstream technology for narrow-band. CEVA announced their solution for Release 14 recently at the Shanghai Mobile World Congress.

One feature of Release 14 will sound pretty familiar to low-power experts. Release 13 data rates were pegged relatively low to meet a low-power goal – at peak ~60Kbps – which you would think would be fine for the small data transfers expected in these applications. However, we often see that net low energy is better served by running faster and stopping sooner. This is particularly true for narrow-band cellular where the power amplifier is the biggest power hog. So Release 14 bumps peak rates by as much as a factor of 3; faster transfers and the battery lasts longer!

Another key extension in Release 14 is location support. Here, let’s start with why you would even want location-awareness in an IoT device. For some applications the need is obvious: asset tracking and child-tracking watches (big in China apparently) are examples. But did you know that location-awareness is also valuable in parking meters and street lights, applications not known for mobility? The reason is subtle. While each such device will stay put for its useful life, the system provider and possibly network owners still have to record, at least initially, where the device is; for maintenance, perhaps for billing, for available parking location info and more. You could rely on human input for that data, or you can just take the human out of the loop to get reliable location data across potentially thousands of devices, especially given the small marginal cost to add this feature.

Location-awareness in Release 14 is based on GNSS (pronounced genesis), which is a constellation of positioning standards: the US GPS standard, China’s BeiDou, Russia’s GLONASS and Europe’s Galileo. I had originally wondered about the narrowband positioning reference signal (NPRS) capability in Release 14 as an alternate way to provide location, but according to Emmanuel Gresset (Director Biz Dev in the CEVA Wireless Unit), NPRS locations are quite coarse and are getting only spotty support among operators. NPRS may still provide value in some cases, but GNSS will be a clear leader for most applications.

The Dragonfly-NB2 platform fully supports the Release 14 standard, adding GNSS hardware and software support (as an option) in the modem and the digital front-end. The system supports multi-constellation GNSS with software switching between constellations. CEVA have added instructions to the modem to more efficiently (speed and power) support GNSS so that supporting additional constellations just requires updating the software, which CEVA intends to keep open (the first release, from a 3[SUP]rd[/SUP] party, supports GPS and BeiDou). And naturally it includes interfaces to connect USIM or eSIM for authentication, etc.

Dragonfly-NB2 continues to offer the advantages of NB1, providing all the components you need, including RF transceiver and power amplifier; just add embedded flash and sensors/sensor-interface and you have a single chip solution. You can run application software on the CEVA-X1 platform at competitive MCU performance in addition to supporting communication functions. CEVA have also added deep-sleep capability to further reduce standby power for that 10-year battery life goal. Emmanuel says you can expect to see full silicon-proven reference boards (with RF) to support application software design in Q3, based on both 55nm and 40nm processes.

Since CEVA are already well known for voice-based capabilities, they also offer voice-activation through their ClearVox software as an option. I’ve written about this capability in other blogs – voice activity detection, beam-forming support, noise suppression, always-on voice-trigger, command and sound detection. Imagine a medical alert system activated by voice rather than pushing a button, or a home protection system detecting the sound of broken glass.

This is a pretty impressive package – cellular communication, location aware, voice activation, ultra-low power. Is it overkill? Not according to recent survey information from Ericsson which Emmanuel shared with me (Ericsson Mobility Report 2018). Adoption of Release 13 + Release 14 is expected to grow at 30% CAGR through 2023, and Emmanuel expects Release 14 to quickly dominate this growth for all the reasons outlined earlier.

A lot of this is being driven by new systems entrepreneurs, like smart bike and scooter providers, parking space trackers, recycling systems and other rapidly-emerging solutions. Each is looking for differentiation in capability, through power, location-awareness, even voice-activation. And they’re also looking for differentiation in cost, where more are now going around the standard supply chain, wanting to squeeze price through single-chip solutions by working directly with IP and ASIC vendors.

So I’m guessing this probably isn’t overkill. Across the boundless range of possible IoT innovation, ability to pick and choose the capabilities you want, especially with hot features like voice activation (no need for panels or buttons), this looks like a great platform on which to build. You can learn more about Dragonfly-NB2 HERE.

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IITC – Imec Presents Copper, Cobalt and Ruthenium Interconnect Results

IITC – Imec Presents Copper, Cobalt and Ruthenium Interconnect Results
by Scotten Jones on 07-02-2018 at 12:00 pm
Categories: Events, Foundries, Semiconductor Services, TechInsights
16 Comments

The IEEE Interconnect Technology Conference (IITC): Advanced Metallization Conference was held June 4th through 7th in Santa Clara. Imec presented multiple papers on comparing copper, cobalt and ruthenium interconnect. One paper in particular caught my eye: Marleen H. van der Veen, # N. Heylen, O. Varela Pedreira, S. Decoster, V. Vega Gonzalez, N. Jourdan, H. Struyf, K. Croes, C. J. Wilson, and Zs. Tőkei, “Damascene benchmark of Ru, Co and Cu in scaled dimensions” and I had the chance to not only review the paper but also to interview one of the papers authors, Zsolt Tokeis.

Background
The resistance of an interconnect line depends on the line length, cross sectional area and the resistivity of the material, see figure 1.

Figure 1. Line Resistance and Material Properties.

On the left side of figure 1 is the formula to determine the resistance of an interconnect line. On the right side of the figure is the bulk resistivity and electron mean free path for selected materials. From the table it can be seen that copper has the lowest bulk resistivity of any of the listed materials, however as the cross-sectional area of an interconnect lines scales down resistivity increases due to scattering. The longer the electron mean free path is in a material the more the resistivity increases as the area is reduced. Copper has a long electron mean free path and is strongly affected by cross sectional area.

The other issue with copper is a barrier layer is required to prevent the copper from contaminating the rest of the structure. Barrier layers are made of materials such as Tantalum Nitride with very high resistivity and the barriers don’t scale down in thickness as the cross sectional area scales down, see figure 2.

Figure 2. Copper Scaling.

Currently copper barriers are around 2nm to 4nm in thickness with 2nm a lower limit. From the figure you can see that scaling from a 14nm node to a 10nm node reduces the copper cross sectional area to 0.33x for a 4nm barrier and 0.48x for a 2nm barrier.

The problems with increasing resistivity as linewidths shrink and barrier resistance open the door for other materials to displace copper at small linewidths if the resistivity doesn’t increase as much with cross sectional area and thinner or no barrier can implementations are possible.

Cobalt and Ruthenium are the two leading materials to replace copper at small dimensions.

Imec Line Resistance Results
Imec created 15nm trench openings on a 44nm pitch and then shrunk the trench width by depositing a conformal SiO[SUB]2[/SUB] layer using Atomic Layer Deposition (ALD). The resistance of lines created by filling the trenches with various were then measured. Figure 3 is the measured resistance of the lines.

Figure 3. Line Resistance Versus Conductor Area
(figure 3 from the imec paper).

Figure 3 from the papers looks at copper with a 2nm barrier (the minimum achievable) versus cobalt and ruthenium with no barriers and 0.3nm adhesion layers. Cobalt and Ruthenium migrate less than copper and can be used without barriers (more on this later).

Plot (a) in the figure is the line resistance versus the cross-sectional area of the conductor material with the cross-sectional area determined electrically and excluding the barrier. From the figure you can see that the resistance goes up for all materials as the cross-sectional area is reduced with copper always having the lowest resistance. Plot (b) in the figure is the resistance of the overall line including barriers and shows that at around 300nm[SUP]2[/SUP] conductor cross-sectional area cobalt and ruthenium are superior to copper.

For a typical aspect ratio this is equivalent to an approximately 12nm linewidth. For advanced nodes there is a trend for critical interconnect layers to have wide lines and narrow spaces between the lines to minimize resistance. A 12nm line would be typical from something like a 16nm pitch, smaller than is likely to be required any time soon.

Via Resistance
For the lower level interconnects lines are relatively short and vias are common. Via resistance can therefore become a very important factor in interconnect resistance and barriers in vias contribute a lot of resistance. Figure 4 illustrates the via resistance versus critical dimension (CD).


Figure 4. Via Resistance Versus CD
(figure 5 in the imec paper).

Figure 4 compares ruthenium with no barrier, cobalt with no barrier, cobalt with a 1nm titanium nitride barrier and copper with a 1nm ruthenium barrier and 1.5nm tantalum nitride barrier. At all CDs ruthenium and cobalt outperform copper. It has been found that barrier-less cobalt is only usable with dense inter level dielectric layers so some barrier may be required depending on the ILD. Ruthenium does not require a barrier at all.

The lower resistance of cobalt and ruthenium vias shifts the pitch at which teh material out perform copper. It is somewhat design dependent but at a 40nm pitch copper is the best, by the time you scale down to 32nm pitch cobalt and ruthenium perform better.

Currently cobalt has been implemented by some companies for contacts at 7nm and Intel is using cobalt interconnect for soem levels for their 10nm (roughly equivalent to foundry 7nm) technology. Ruthenium has the best via and interconnect resistance at small dimension but is very difficult to process.

Electromigration
Even with the relatively small currents that exist in state-of-the art ICs, the small cross-sectional area of the conductors leads to high current density. Momentum transfer from electrons to the conductor atoms can cause the conductor atoms to migrate and eventually create breaks in the conductor. This is referred to as electromigration and is a serious issue particularly in higher performance designs. The electromigration resistance of a material can be characterized by the activation energy of the material for electromigration to occur where the activation energy is an exponential factor. The electromigration activation energy is proportional to the materials melting point and cobalt and particularly ruthenium shows greatly improved electromigration resistance compared to copper.

Discussion
Taking line resistance, via resistance and electromigration into account imec draws the line at around a 40nm pitch for cobalt or ruthenium to outperform copper.

Imec is working on a barrier-less cobalt solution with dense low-k iILD materials, electromigration performance is good but without a barrier cobalt does intermix with copper where the two materials come into contact at high interconnect levels.

Ruthenium doesn’t need a barrier but CMP of ruthenium is still problematic.

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55DAC Trip Report with Drama

55DAC Trip Report with Drama
by Daniel Nenni on 07-02-2018 at 7:00 am
Categories: Events

This was my 35th DAC and it did not disappoint, especially when it came to the DAC Drama Department. This year DAC proved once again that it is THE place for semiconductor professionals and academics to learn and network. The big news is that Synopsys did not reserve a booth for 56DAC in Las Vegas next year which resulted in quite a bit of drama.

In my opinion the actual location of DAC is not as big of a deal as it seems. The number one critical feature of any conference is content. Without great content it does not matter where it is located and by content I am talking about the actual conference, not what’s happening on the exhibit floor.

The second critical conference feature is promotion. You have to get the word out to the masses. As a mature industry new faces are always important, especially in the academic community as they are our future.

Third of course is location. I have been to DACs all over North America including my first one in Albuquerque NM, two in Las Vegas and two in New Orleans of all places. San Francisco, San Diego, and Anaheim are popular destinations because let’s face it, California is the best location, absolutely. For the life of me I do not know why it has never been in San Jose but that is another story.

Back to the drama of Synopsys not exhibiting at 56DAC. The first question I have is: “Does it really matter?” To me the answer is no, Synopsys not exhibiting will not change my plans at all. My beautiful wife and I are both attending 56DAC, we both enjoy Las Vegas and are really looking forward to it. In fact, my wife’s first DAC was 1985 in Las Vegas. The picture above is from our 30th wedding anniversary in Las Vegas where we renewed our vows. Kind of a spur of the moment thing. We actually went there to see Elton John but I digress…

By the way, this would not be the first time a leading EDA company skipped exhibiting at DAC. Cadence did it a number of years ago when it was in San Francisco. Instead they rented space at the Four Seasons hotel across the street. That was pretty much the end of Cadence CEO Mike Fister. EDA and IP customers will always have a choice and how a company behaves can sway that choice one way or another, believe me.

To be clear, just because Synopsys may not exhibit I can assure you they will still be part of the DAC sessions and panels. The only real difference will be a lot less purple running around and I am okay with that.

Based on what I was told by people that know, 56DAC will in fact be in Las Vegas no matter which vendors decide not to show up. 57DAC however will probably be co-located with SEMICON WEST in San Francisco. I also attend SEMICON and feel co-location would be a 1+1=3 proposition. Semiconductor design and semiconductor manufacturing has never been closer and it will continue to cross even more paths as we introduce new process technologies, my opinion.

This year more than 20,000 people are expected to attend SEMICON WEST as compared to around 6,000 people at DAC:

“From materials, equipment, design, manufacturing, system integration, and demand channels to new verticals and adjacencies such as Flexible Hybrid Electronics, MEMS & Sensors, you’ll gain access to the best in the business and get a glimpse at what’s next. Immersive, new experiences demonstrating hot-buttons like Smart Transportation, Smart Manufacturing, MedTech, Big Data, IoT, and the cognitive technologies that are transforming the world make this year’s Expo like no other before.”

Sounds like a great fit to me!

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Trump is the greatest gift that Twitter could have asked for!

Trump is the greatest gift that Twitter could have asked for!
by Vivek Wadhwa on 07-01-2018 at 7:00 am
Categories: General

In the 1930s, psychologist B.F. Skinner put rats in boxes and taught them to push levers to receive a food pellet. The pushed the levers only when hungry, though. To get the rats to press the lever repeatedly, even when they did not need food, he gave them a pellet only some of the time, a concept now known as intermittent variable rewards. Casinos have used this same technique for decades to keep us pouring money into slot machines. And now the technology industry is using it to keep us checking our smartphones for emails, for new followers on Twitter, or for more “likes” on photographs we posted on Facebook.

It’s also the technique Donald Trump has mastered with his tweets. Whether on the left or the right, we are now so addicted to this erratic stream of controversy that we must, must, must check our social media far more often to witness the latest twist. In other words, we are now a national Skinner Box experiment, a country of rats waiting for the food pellet to fall.

Ironically, the greatest beneficiaries of this growing addiction to the crazy political news cycle are none other than the technology companies that make it possible. Donald Trump is their greatest gift, and they are his. Social media have become the equivalent of rat pellets, and the technologies that were supposed to bring humanity together and satisfy our social cravings are instead tearing societies apart.

This is something that Alex Salkever and I explain in our new book, Your Happiness Was Hacked: Why Tech Is Winning the Battle to Control Your Brain—and How to Fight Back.We are never sure whether someone has retweeted, “liked”, or commented on our posts, so we return to our devices all the time and, in doing so, end up being sucked into the rabbit hole. This induces release of dopamine, a neurotransmitter related to feelings of satisfaction. The resultant feeling of satisfaction is very short term, though, and is often followed by longer-lasting feelings of frustration and regret at having wasted time and allowed another to hijack our brains and our attention.

One motivator dependent upon intermittent variable rewards is the fear of missing out (FOMO). FOMO is a tangible feeling that we are being left out of a conversation or event that is important to our social status, work, or position in society. FOMO commonly happens at work. And now, our president has pushed FOMO aggressively into the social realm. We feel a need to know what’s happening because so much is happening and it’s all so crazy!

The media that we consume as a result of these manipulations tend to be biased toward events that have a very negative effect on us. It may be important that we know what is happening in the world around us, especially if we are to change it. But absorbing too much news of negative events trains us to perceive them to be more likely than they actually are to affect us directly. Talk of the invasion of America by gangs of the transnational criminal organization MS-13 induces people to fear gang activity even in places where MS-13 has no presence. That effect occurs amongst both Trump supporters and Trump opponents, because the part of our mind that processes deep fears still factors in information that our logical minds would declare false.

Of course, the ubiquity of certain negative stories of even marginal makes those stories appear highly relevant to everyday life, leading to greater consumption of the technology platforms that publish them. Until the last elections, Twitter was essentially dying. Yet, following the election, in its 2017 annual report, Twitter stated that, though user numbers had grown by just 4%, engagement had grown by a very substantial 12%. More engagement means more ads and a feedback loop that is stronger and therefore harder to exit or to consciously opt out of.

Twitter is Trump’s platform of choice, of course. But the behaviors that Trump’s use of it encourages in all of us feed into the advertising-revenue streams of all major online search engines and social media. Thus many apps now employ the convention of using a red dot on an icon or on a menu to indicate that an update, message, or other form of communication is awaiting our attention. And the growth of this compulsive behavior conversely robs us of control and poisons our world view.

We don’t want to check Twitter more often. It makes us dissatisfied, even grumpy. And we don’t want to think only about the bad things in life. But we feel powerless to control the information that overwhelms us via our friends and everything else we consume to learn about the world.

So this presidential term is, if nothing else, a gift to the tech companies that benefit from the behaviors that actors in the political realm are constantly reinforcing in the population. And if you have felt your life to be less under your own control since the nation entered this new Skinner Box phase, that may be because it is.

For more, please read my new book,Your Happiness Was Hacked: Why Tech Is Winning the Battle to Control Your Brain—and How to Fight Back.

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The TI Experience and Morris Chang

The TI Experience and Morris Chang
by Daniel Nenni on 06-29-2018 at 7:00 am
Categories: Wally Rhines
4 Comments

This is the fourth in the series of “20 Questions with Wally Rhines”

I joined Texas Instruments (TI) in 1972. Most Stanford PhD’s in my field at that time remained in the Bay Area to work for Fairchild, National Semiconductor, HP or other local companies. But TI was the largest semiconductor company and there were plenty of TI PhD’s recruiting at Stanford.

About a month after I arrived at TI, Morris Chang was promoted to Group Vice President of the Semiconductor Group. Morris was born in Mainland China, near Shanghai, and had the unique distinction of being accepted to Harvard University in the U.S. Sensing that a technical degree was the best path forward, Morris transferred from Harvard to MIT after the first year and ultimately received a Mechanical Engineering degree and took a job at Sylvania, an early participant in the emerging semiconductor industry.

With several years of experience. Morris was attracted to TI in 1958 and was given responsibility for developing and manufacturing transistors for IBM’s first major mainframe computer with transistor logic, the IBM 7090. There were four transistors that were produced by both IBM and TI, three of which were yielding at acceptable levels. But one of them remained at low single digit yields. Morris worked late nights analyzing data and finally figured out the problem. Yields soared and Morris became a hero, ultimately becoming the manager of all of TI’s germanium transistor business.

Morris’ goal, however, was to become VP of R&D. His superiors told him that such a goal would be impossible unless he had a PhD since most of the researchers had that credential. So Morris took advantage of a TI funded opportunity to go to Stanford in 1961 and studied under John Moll, Bill Spicer and Gerald Pearson, receiving his PhD in record time in early 1964. When he returned to TI, business had grown dramatically so, instead of joining the research labs, they needed Morris to run the integrated circuit business. Despite Jack Kilby’s invention of the integrated circuit in 1958, TI had lost ground due to Bob Noyce’s development of the planar process in 1960 which eclipsed TI’s lead. With some good decisions and hard work, TI emerged as the leader in bipolar TTL integrated circuits (after losing to Fairchild in the first bipolar generation RTL and Motorola in the second generation with DTL). This success, combined with TI’s two year lead in developing the silicon transistor took TI to its goal of $1 billion of revenue. And Morris headed the world’s largest semiconductor business.

While TI dominated the bipolar semiconductor era of integrated circuits, and had the largest market share in the semiconductor industry in the 1960’s, the MOS era that evolved in the late 1960’s with Intel and Mostek was a different story. While TI did the best job of the “Big Three” (TI, Fairchild and Motorola) of making the transition from bipolar to MOS technology initially, Motorola recruited a substantial number of TI’s senior semiconductor managers in the mid 1970’s including Jim Fiebiger whose team from TI changed the competitive environment. MOS memory and later microprocessors became strengths for both of TI’s key competitors, Intel and Motorola. That made the late 1970’s and 1980’s a difficult period for TI.

Intel’s 1103 1K DRAM became a widely adopted standard. TI had three programs to match it before a production worthy part was developed but it was too late. Hope appeared when the 4K NMOS DRAM emerged since Intel had a three transistor cell and TI leapfrogged to a single transistor cell but the victory was short lived. Mostek, who had introduced an undistinguished 4096 MNOS structure for their 4K but, upon hiring Paul Schroeder from Bell Labs (who said on his resume that he was the greatest DRAM designer in the world), usurped the lead with the Mostek 4027. TI struggled with its TMS 4030 design and remained allied with the camp of companies doing 18 and 22 pin parts because of the advantage that they required no multiplexing of address and data and would therefore be faster, unlike the 16 pin Mostek part. Mostek’s 4027 disproved that thesis. The only solution was to copy the Mostek 4027, which was perfectly legal at the time, and I was chosen to head that team.

On the day I arrived in Houston to begin the development, Dick Gossen, head of memory design, advised me to begin filling out my resume. Dick explained to me that the corporate senior management was underestimating the difficulty created by the analog nature of a DRAM. TI, and everyone else, had freely second sourced logic parts by copying. In fact, that was the normal procedure that was encouraged in the industry to make a design viable, i.e. solicit another company to copy your part and help to make it a standard. DRAM’s, however, have analog sense amplifiers that have variable behavior depending upon the process used for manufacturing.

I began a detailed analysis of the device structure of the Mostek 4027 and discovered that, when the Mostek founders left TI to start Mostek, they took the TI process with them. So the normal difficulties of matching a design and a process were not relevant; the process was the same.

We followed the 4K with a similar copy of the 16K DRAM that kept TI as a contender in the MOS memory business but the challenges of the evolving microprocessor business put TI further behind (spectrum.ieee.org/tech-history/heroic-failures/the-inside-story-of-texas-instruments-biggest-blunder-the-tms9900-microprocessor).

Rarely do companies succeed in being the leader in two major transitions of an industry. TI had done that with the silicon transistor and the bipolar integrated circuit. But the next two generations were MOS memory and MOS microprocessors, leaving TI behind. Today, TI is the only company to continue as one of the ten largest semiconductor companies from the 1950’s to the present because the tide was reversed in the next generation of embedded DSP’s.

The 20 Questions with Wally Rhines Series

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The Technology China Trade Growing Snowball

The Technology China Trade Growing Snowball
by Robert Maire on 06-28-2018 at 12:00 pm
Categories: Semiconductor Advisors, Semiconductor Services
7 Comments

As we have been warning for months the China trade issue continues to grow and accelerate. As we are approaching the June 30th cliff (when export sanctions will be announced) it seems as if the administration has given the industry a kick so we fly even further. The US will also restrict Chinese investment in US tech companies. The administration went on to say that other foreign countries beyond China will also be held to the same restrictions.

Ir seems fairly clear that China’s “Made in China 2025” program is a red flag to the current US administration. Given this further escalation , it makes it even harder to back down from the edge that we are racing towards. We had previously said that a resolution prior to the June 30th announcement was low, we now put the odds at less than zero.

Even if we backed off or found a way to settle with China, we think permanent damage has been done to the tech industry that will either take very long to recover from or never recover at all. The repercussions are much broader after you realize all the interconnectedness of the Chinese and US economies.

We may also be helping other countries compete against us on the global stage given our. It’s very difficult if not impossible to calculate the full risk of semiconductor trade with China as there are many derivatives that are unclear. Much of this will also remain unclear as even after the June 30th list comes out we are sure there will be questions.

A very rough guess of 25% of the overall US semiconductor industry may be a starting point. At least 15% or so of the semi equipment industry is likely at risk. The risk obviously varies widely. The stocks will be driven primarily by this China trade issue as there are limited other drivers at this point. The stocks have done well and are well priced which can set us up for downside.

Throwing a wet blanket on M&A?
We can well imagine that we might see a slight slow down in semiconductor M&A or at least an easing of valuations assuming China will be taken out of the bidding process. China has a very big $100B checkbook for the semiconductor industry and if we stop them from bidding we could see reduced M&A activity and at the very least lower valuations as a bidder with money burning a hole in their pocket has been thrown out of the game.

Companies who may have embraced one another with fear of being acquired may be OK being single and boards may not see dollar signs of big Chinese checks.

Helping foreign competitors in China
By refusing to sell to China we will cede the Chinese market to our competitors plain and simple. While not selling them oil and pork bellies is easily replaced by other countries in a commodity market chips and chip equipment is not quite a commodity in many cases.

In semiconductor equipment both Lam and AMAT compete against the likes of Tokyo Electron (who AMAT tried to buy) as well as Hitachi. They both also compete against ASM International (not ASML). KLA , NANO and Rudolph have NOVA (of Israel) as a competitor as well as Hitachi and others. Veeco has Aixtron in Germany. You also have indigenous Chinese suppliers like AMEC.

You can be sure that salesmen at Tokyo Electron , Hitachi, Nova, AMEC and Aixtron and others have already placed calls to their Chinese customers to offer help against those untrustworthy Americans. We have seen the trailer for this movie before in the Veeco/AMEC dust up in China. We think Veeco permanently lost customers who would rather buy from a local supplier, AMEC, rather than a US supplier who could be cut off at any minute even if the technology was worse and price higher. Its more important to have a steady supply to stay in business as ZTE found out.

Even if we kiss and make up with China, as Veeco and AMEC did, the damage has already been done and is “undoable”.

“Billing” address versus “ship to” address?Moody’s gets it wrong…
We found a laughable news report that Moody’s (obviously experts in the semiconductor equipment industry) that said that China will have a limited impact on the semiconductor equipment industry as “indigenous” business with China amounts to only 6% of AMAT, LRCX & KLAC.

We don’t think even the current administration with its limited understanding of tech thinks for a second that technology loss to China only matters with companies that are “indigenous” to China (ie; billing address is in China).

The issue is that companies like Intel, Samsung and others are building fabs in China and teaching them. This is much like Japanese engineers who on their weekend breaks flew to Korea to help set up Korea in the semiconductor business.

What Moody’s got wrong is that it is the “ship to” address that matters and that is a lot, lot larger than 6%….more like 15% or more. China is the fastest growing market for semiconductor equipment period. With memory slowing its even more important than ever.

Who cares who pays for it or gets the bill or where the company is headquartered, what matters is what equipment shows up inside China, thats what the administration wants to stop and they are not so stupid as to use a “bill to” address.

This means that life for companies like Intel and Samsung will get very complicated. Will they abide by restrictions which could put their China operations out of business? Will equipment be “trans-shipped” from Korea and Oregon? Will equipment makers service “gray market” equipment? Will they be breaking the law? Will they just buy from non US equipment companies for their China operations and teach the Chinese how to make do?

It going to get very ugly, very confusing and very messy.

US semi equipment manufacturing in China at risk?
One thing not widely mentioned are equipment companies that manufacture in China and ship back to the US. Two companies that come to mind are AEIS which moved its semiconductor power supply manufacturing from Colorado to China a long time ago and UCTT which makes a significant amount of its product in China and has been one of the leaders in outsourcing to China.

What will the tariffs do to those products? what could the impact on gross margins be? These products go into AMAT and Lam tools which could in turn be at risk.

Ignoring the 800 pound gorilla in the room….China trade
We find it interesting that quite a few so called analysts have not mentioned China trade as an issue or mentioned it only in passing. We have published numerous articles starting with our April first issue warning of a potential equipment embargo and reporting on the increasing issues and associated risks. We similarly started ringing alarm bells about the dependence on memory growing to an unsustainable level of business. Other analysts only recognized the memory market issues after Samsung stopped its orders.

We pointed out in our last newsletter that both memory and China have been the two brightest spots in the industry and now both have dimmed at the same time for different reasons. It seems that many have not fully calculated the potential impact of China and will only do so after the fact on July 1st.

Investors need to pay attention as headline risk can cause stocks to go down in the near term even if trade issues are worked out over the longer term

The Stocks….
We had mentioned in the past weeks to our clients that being short the semi group would probably be appropriate going into June 15th and June 30th and so far that seems to be the case.

We would mention again to investors that a simple way to be short the group is SOXS (not SOXX). SOXS is a 3X bear index of the SOXX index. The SOXX was down 3.13% today while SOXS was up 8.7% today. At the very least, for those long term holders who don’t want to trade out of positions and go short you can “hedge” your bets a bit with SOXS (we have no affiliation and get no compensation…).

We made some money in AMAT’s quarter suggesting it had downside to a”4″ handle, and it was down 10%. We thought $45 might be a good place to buy in again but we are re-thinking that in light of the worsening Chinese trade issues.

When investors see a 25% shipments down quarter from Lam we could see a $150ish price. KLAC has been immune until recently but has still been holding up relatively well. ASML has broken below $200 which we view as an important psychological barrier.

Unfortunately we see no positive news coming out before the June 30th “D” day for exports to China and don’t think Semicon will help the stocks either. Even good numbers from Micron haven’t helped much and Intel’s CEO issues don’t help either….

All is not quiet on the semiconductor front and the war is going poorly before it even starts…

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Design for Power: An Insider View

Design for Power: An Insider View
by Bernard Murphy on 06-28-2018 at 7:00 am
Categories: EDA, Events, Siemens EDA

The second keynote at Mentor’s U2U this year was given by Hooman Moshar, VP of Engineering at Broadcom, on the always (these days) important topic of design for power. This is one of my favorite areas. I have, I think, a decent theoretical background in the topic, but I definitely need a periodic refresh on the ground reality from the people who are actually designing these devices. Hooman provided a lot of insight in this keynote.


He set the stage by defining categories for power. Category 1 is high end, high performance, high margin where power is managed as needed at any cost. Category 2 is mid-range, good performance but under margin pressure, where power is critical to system cost. Category 3 is low end, lower performance and low margin where power is critical to system operation (e.g. battery/system lifetime). In his talk, Hooman focused mostly on Category 2 devices. He covered a lot of background on power and the challenges, which I won’t try to cover in depth here; just a few areas that particularly struck me.

First, some general system observations. He said that for Broadcom, thermal design at the system level is obviously not under their control and customers are often not very sophisticated in managing thermal, so Broadcom winds up shouldering much of the burden of making solutions work in spite of the customers. Given this, integration is not a panacea in part because of power. Multiple smaller packages can be cheaper both in manufacturing and in total thermal management cost.

In power estimation at initial planning/architecture, it was interesting to hear that this is still very much dominated by Spice modeling, spreadsheets and scaling. He said they have evaluated various proposed solutions over the years but have never found enough accuracy to justify switching from their existing flows. Which I don’t find very surprising. If you can carry across use-cases and measure power stats from an earlier generation device and scale parasitics, you ought to get better estimates from a spreadsheet that you could when estimating parasitics, uses-cases and power scaling in a tool. At RTL they use PowerPro (from Mentor, not a surprise) and have determined that this, like competing tools, typically can get to within 20% of gate-level signoff power estimates.

For power management, they use a lot of the standard techniques: mixed Vt libraries, clock gating both at the leaf-level and in the tree (since clock tree power is significant), frequency scaling and power gating. He also mentioned keeping junction temperatures down to 110[SUP]o[/SUP]C (he doesn’t say how, perhaps through adaptive voltage scaling?), which lowers leakage power and also improves timing, EM and long-term reliability. They also like AVS as a way to reduce power in the FF corner. Hooman touched on FinFET technologies; I have the impression they are more cautious than the mobile guys, where area/cost tradeoff is not always a win, though reduced (leakage) power can still provide an advantage in integration.

He talked about some additional techniques for power reduction, such as use of min-power designware, e.g. in a datapath with many multipliers or in a block instantiated many times in an SoC. Another technique he likes is XOR self-gating – stopping the clock on a flop in absence of a toggle on the data input (need to be careful with this one at clock domain crossings).

Looking at challenges they still face, he said that active power management is still a bigger concern for them than leakage. The challenge (at RTL) is in estimation, particularly in estimating the power in the synthesized clock tree since the detailed tree obviously doesn’t exist yet at this stage. He acknowledged that all tools have methods to manage this error and to tune estimates in general (eg by leveraging parasitic estimates from legacy designs).

Hooman talked about challenges in getting useful toggle coverage early for reasonably accurate dynamic power estimation. RTL power estimates lack absolute accuracy (they’re better for relative estimates), while gate-level sims are more accurate but take too long and are available too late in the schedule. He said they should be using emulation more but still see challenges with that flow. One is differences between the way combinatorial logic and memories are modeled in the emulator and in design logic – this he feels requires some improvisation in estimation. Another is that you still need to connect all that other scaling/estimate stuff (parasitics etc) with emulation-based power estimation. I would guess this part is primarily a product limitation which will be fixed in time (?).

Overall, good insights, especially on the state of the art in mid-range power management. No big surprises and, perhaps as usual, design reality may not be quite as far along as the marketing pitches. I’m sure it will eventually catch up :cool:.

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Imec technology forum 2018 – the future of scaling

Imec technology forum 2018 – the future of scaling
by Scotten Jones on 06-27-2018 at 12:00 pm
Categories: Events, Semiconductor Services, TechInsights

At the Imec technology forum in Belgium, Dan Mocuta and Juliana Radu presented “Evolution and Disruption: A Perspective on Logic Scaling and Beyond”, I also had a chance to sit down with Dan and discuss the presentation.

Device scaling
Scaling of devices will only get you so far, you need to look at new devices and new materials. For new materials SiGe for channels is the most likely next material. Authors note, there was a lot of discussion of SiGe PMOS channels for 5nm at IEDM in December of last year.

You can use circuit level design to augment device level scaling that is slowing down but they are one-time kind of scaling boosters and you have to come up with something new for each new generation. Figure 1 illustrates some device level scaling boosters that are being considered or implemented.

Figure 1. Design Technology Co Optimization (DTCO) Scaling Boosters.

Authors note, some of the scaling boosters in figure 1 are in use now, for example super vias in TSMC 10nm, dual STI in multiple FinFET technologies, single diffusion break in multiple technologies and self-aligned gate in Intel’s 10nm process.

From a device scaling perspective, the goal is to stay on FinFETs as long as possible for cost and control reasons but contacted poly pitch (CPP) scaling is slowing and moving to horizontal nanowires/nanosheets (HNW/HNS) provides additional CPP scaling. Imec has demonstrated HNW/HNS but it is not their scope to carry it further. Companies interested in commercializing the technology must carry the work forward.

System optimization
To continue scaling you must look at the system and optimize the system and technology. There are three approaches:

[LIST=1]

  • Co integration – co integrate devices, for examples IBM 14nm has FinFETs over embedded trench DRAM fabricated in the substrate. Or there is the proposed CFET devices where nFET and pFET devices are stacked on top of each other.
  • Sequential 3D – fabricate a device up to Middle Of Line (MOL) and then bond a wafer on top, thin the bonded wafer and fabricate another layer of devices in the bonded wafer, for example SRAM over logic.
  • 3D IC – fabricate complete devices and then stack them using Through Silicon Vias (TSV) and or Interposers.Figure 2 summarizes the three approaches.

    Figure 2. System Technology Co Optimization (STCO) Driven (Disruptive) Future Scaling.

    Figure 3 provide more information on the CFET concept. Stacking an nFET over a pFET into 2 decks can result in a 40% structural gain in SRAM scaling. Authors note, there are groups working on extending this concept to multiple decks, I have even seen a 7 deck proposal that relaxes lithography rules to 14nm but achieve 1xnm node scaling.


    Figure 3. Disruptive Next Generation Device: CFET.

    Figure 4 illustrates how a multi core microprocessor can be scaled using 3D integration. The advantage of this technique is that each block of the microprocessor can be implemented in the optimum technology. Breaking up the cores, memory and internal/external interconnect allows a memory optimized process to be used for memory, a core performance optimized technology to be used for the cores and a relaxed technology for the I/O. This type of partitioning and optimization can address performance and cost but there are cooling challenges with this approach.


    Figure 4. 3D-SOC: Functional Partitioning for High Performance.


    Conclusion
    As traditional device scaling slows down there are multiple options for new devices and 3D integration schemes to continue scaling.

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When Why and How Should You Use Embedded FPGA Technology

When Why and How Should You Use Embedded FPGA Technology
by Alok Sanghavi on 06-27-2018 at 7:00 am
Categories: Achronix, eFPGA, FPGA

If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn’t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors — then progressing to gates, ALUs, microprocessors, and memories. FPGAs are simply one more useful component in the tool box, available for decades as standalone products, and now available for integration into your IC design using Achronix’s Speedcore eFPGA, supported by Achronix’s ACE design tools. These products allow you to easily incorporate the performance and flexibility of programmable logic into your next ASIC or FPGA design.

The questions then become: Why would you want to do that? Why use an FPGA at all? Why put a programmable fabric in your ASIC or SoC?

Why FPGAs?
System-level designers employ FPGAs for many reasons, but the two main ones are performance and flexibility. Many tasks executed in software running on a processor benefit from significant performance improvements when implemented in hardware. When designing ASICs and SoCs, however, there’s a fork in the hardware path. If you’re absolutely certain that there will never be any changes in the associated algorithms, then freezing the functionality into ASIC gates makes sense.

These days, not much seems that stable. Standards change. Market needs change. If you’ve frozen the wrong algorithm in ASIC gates, you’ll need to respin your chip.

To mitigate the risks associated with ASIC gates, system designers have relied on FPGAs for decades to execute algorithms at hardware-level processing speeds with the flexibility to change the algorithm in milliseconds (or less). Pairing an application processor or microcontroller with an FPGA on a circuit board is now common design practice. The FPGA accelerates tasks that need it.

Moving the Programmable Fabric into the ASIC
However when the application processor and the FPGA are in separate chips, communications between the two represent a major bottleneck. No matter how fast the communications between the two devices, the FPGA is always logically “far away” from the processor, as Achronix’ Kent Orthner describes in the video:

For example, PCIe has become a common protocol for connecting processors with FPGAs on a circuit board. While PCIe is a high-speed serial protocol, featuring fast data transfer, there’s additional latency to serialize the data, transmit it, and then deserialize it. In practice, the hardware latency is on the order of 1 microsecond, but with Linux overhead, that latency can be an order of magnitude larger or more. Consequently, the accelerated algorithm must be meaty enough in terms of processing time and processed data size to overcome this latency.

Embedding an FPGA into your ASIC or SoC solves this bottleneck. You can instantiate as much connectivity between the on-chip processor(s) and the FPGA(s) as required by your application. For example, many SoC designs couple ARM processor cores to other on-chip hardware using AXI buses. You can easily use a 128-bit AXI bus to connect a complex of processors to an eFPGA. But why stop there? If your application requires more bandwidth, you can use two, four, or more 128-bit AXI buses to drive multiple accelerators instantiated in the eFPGA(s).

There’s another, more subtle reason why eFPGAs outperform discrete processor/FPGA implementations. Because the FPGA is “far away” from the processor, it must usually have its own DDR SDRAM to buffer large data blocks. This need to buffer means that the processor or a DMA controller must move the data to be processed from the application processor’s DDR memory to the FPGA’s DDR memory. Then, the processed data must be transferred from the FPGA’s DDR memory to the processor’s DDR memory. Depending on the amount of data to be transferred, the delay incurred by these data transfers falls somewhere between a long, long time and forever (from a hardware-level speed perspective).

Giving the on-chip eFPGA direct access to the processor’s DDR memory means that data does not need to be buffered. The transfer becomes nothing more than passing a memory pointer to the eFPGA so that it can immediately start processing. When the eFPGA completes its work, it passes a memory pointer back to the processor for any additional handling.

Where might these eFPGA qualities be useful? Here are three application examples to whet your imagination:

  • Wireless/5G – No industry is in more flux at the moment that the telecom industry. The 5G specifications are constantly being updated while telecom providers are doing what they can to extract the most out of installed 4G infrastructure equipment. In addition, telecom equipment must meet stringent size, weight, and power requirements. All of these factors argue in favor of SoCs with eFPGAs to provide instant flexibility while reducing equipment size, power, and weight.

  • Fintech/High-Frequency Trading – As discussed above, eFPGAs reduce latency. In the high-frequency trading world, cutting latency by a microsecond can be worth millions of dollars. That alone is more than enough justification for developing SoCs with on-chip eFPGAs to handle the frequently changed trading algorithms.

  • Artificial Intelligence/Machine Learning (AI/ML) Inference and CNNs – Convolutional Neural Network (CNN) inference algorithms rely heavily on multiply/accumulate operations and programmable logic. Speedcore eFPGAs can significantly accelerate such algorithms using the massive parallelism made possible by including a large number of programmable DSP blocks in your eFPGA specification.

These are just three examples demonstrating how eFPGAs can enhance an ASIC’s or SoC’s performance and capabilities. If you would like to explore other ways your ASIC or SoC design might benefit from a performance-enhancing, on-chip FPGA, visit www.achronix.com/product/speedcore/.