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2025 Outlook with Matt Burns of Samtec

2025 Outlook with Matt Burns of Samtec
by Daniel Nenni on 01-09-2025 at 10:00 am
Categories: Samtec, Semiconductor Services

Matt Burns Samtec

My good friend Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 25 years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Matt holds a B.S. in Electrical Engineering from Penn State University.

Tell us a little bit about yourself and your company.

Samtec is a privately held, global manufacturer of a broad line of high-performance copper, optical, and RF interconnect solutions. Our technical experts around the globe optimize the signal path from the bare die to an interface 100 meters away, and all interconnect points in between. I lead an experienced team of professionals who evangelize the capabilities of Samtec’s Silicon-to-Silicon solutions.

What was the most exciting high point of 2024 for your company?

Throughout the year, Samtec was able to demonstrate the high-speed capabilities of several next-gen interconnect platform solutions. Even at 224 Gbps PAM4 speeds, copper isn’t dead.  Samtec’s Flyover® Next-Gen Systems route data from the ASIC to the front panel (or backplane) via our Eye Speed® Cable Technology. At SC24, we exhibited the latest versions of our Si-Fly® HD co-packaged and near chip systems driven by Synopsys IP with a pre-FEC BER of e-9 over a 40 dB channel. On the optical side, our demonstrated 56 Gbps PAM4 performance of our Halo™ next-gen mid-board optical transceivers.

What was the biggest challenge your company faced in 2024? 

I talked with several colleagues throughout the year. All of us agreed that innovation is speeding up. We anticipate that will continue going forward. The near insatiable demand for GPUs, XPUs, and AI accelerators by the hyperscalers remains the key driving force here. Semiconductor suppliers, IP providers, EDA vendors and interconnect companies like Samtec must meet their design requirements on-time and under budget. That sounds common sensical, but the combined technology required to scale AI at the pace the industry demands is unprecedented.

How is your company’s work addressing this biggest challenge? 

Samtec is innovating faster as well. We are ramping up our engineering hiring. It’s just a necessity. Unique design challenges demand unique interconnect solutions. Our technical experts are improving the SI performance across the new signal channels. We are creating next-gen mated contact systems to enable 224 Gbps PAM4 performance in dense, small footprints. We constantly tweak our twinax cable technology by testing new dielectric materials, improving cable manufacturing, or developing new cable testing techniques. Our SI engineers are always researching the latest laminates to recommend for high-speed or high-frequency design. We work with our partners to squeeze more performance out of simulation tools. The list goes on.

What do you think the biggest growth area for 2025 will be, and why?

In short, we can’t manufacture micro coax and twinax copper cables fast enough. The adoption of Samtec’s Flyover® technology across networking, computing, storage, and AI acceleration platforms throughout data center, supercomputing systems, and semiconductor testing and manufacturing applications continues to be the driver here. We are also seeing increased demand for our growing portfolio mid-board optical transceivers across several applications.

How is your company’s work addressing this growth? 

As mentioned, we continue to invest in innovation. On the copper cable side, we need to find to materials with the lowest dK available. That has led us to researching, developing and finally manufacturing twinax cable based on uniformly foamed dielectrics. Cable diameters need to be smaller, so finding thinner cable wraps is a necessity. We are expanding cable manufacturing globally. Additionally, we have standard cable assemblies, but our customers usually require something unique. We need to balance supporting emerging R+D opportunities while handling high-volume needs of programs already in production. On the optical side, its more of the same story: ramp innovation and ramp production.

What conferences did you attend in 2024 and how was the traffic?

Samtec sponsors, exhibits, and presents at more than 50 tradeshows and conferences annually around the glove.  Some of the shows I attended included OFC, the OCP Global Summit, MemCon, various PCI-SIG DevCons, ECOC, embedded world, SuperComputing (SC24), and the AI Hardware and Edge AI Summit. From Samtec’s perspective and personally, attendance at tradeshows is still on an upward trend. That’s been the case that last few years coming out of the pandemic.  However, I think the accelerating pace of innovation in AI, semiconductors, EDA, optical connectivity, and other high-growth areas are defining this trend.  I expect this to continue into 2025

Will you attend conferences in 2025? Same or more?

Yes, without a doubt. Conference and events are still a great way to meet luminaries, thought leaders, influencers, design engineers and the like. We are still finalizing our 2025 event strategy and scheduling.  Overall, we will probably attend more vents in 2025. We will likely be on par in the Americas and EMEA, while we strategically invest a bit more across Asia.

How do customers engage with your company?

That’s a great question. As I just mentioned, we still meet plenty of new customers as conferences. Engineers can engage with us directly via our global sales team or our global network of approved distributors. Technically, our FAEs, AEs, and SI engineers are only a phone call or e-mail away. Our website – www.samtec.com – is a treasure trove of product information. We are also accessible via our social media channels.

Additional questions or final comments? 

It’s always nice to engage with you and you team, Dan. We always appreciate the opportunity.  I am sure the year ahead will pose many opportunities and challenges. Samtec looks forward to working with our customers and partners to solve their next-gen interconnect challenges.

About Samtec

Founded in 1976, Samtec is much more than just another connector company. We put people first, along with a commitment to exceptional service, quality products and innovative technologies that take the industry further faster. This is enabled by our unique, fully integrated business model, which allows for true collaboration and innovation without the limits of traditional business models.

Also Read:

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

Samtec Demystifies Signal Integrity for Everyone

Samtec Simplifies Complex Interconnect Design with Solution Blocks

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2025 Outlook with Christelle Faucon of Agile Analog

2025 Outlook with Christelle Faucon of Agile Analog
by Daniel Nenni on 01-09-2025 at 6:00 am
Categories: Agile Analog, IP

Agile Analog Christelle Faucon headshot

Tell us a little bit about yourself and your company. 

I was born in France, but I have been living in the Netherlands for two decades. I have worked in the global semiconductor industry for over 25 years. After my Master’s Degree in Electronics Engineering, I started my career as a Design Engineer. Since then I have held senior product and commercial positions, including 10 years at TSMC and 10 years as President of GUC (Global Unichip) Europe. Currently I am the VP of Sales at Agile Analog, the customizable analog IP company.

Agile Analog is revolutionizing the analog IP sector with our expanding portfolio of highly configurable, multi-process analog IP products. The company has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications, for any foundry and on any process. We provide a wide-range of customizable analog IP solutions and subsystems, covering data conversion, power management, IC monitoring, security and always-on IP. Applications include; HPC (High Performance Computing), IoT, AI and security.

What was the most exciting high point of 2024 for your company? 

2024 was an extremely busy time at Agile Analog. Our main focus was on implementing and delivering customer projects. Throughout the year we saw a significant increase in demand for our novel analog IP and we ramped up the number of customer deliveries. There are tier 1 companies that we work with that unfortunately we can’t talk about due to confidentiality, but in March 2024 we were able to announce the completion of our first always-on IP subsystem for XMOS.

We have also strengthened relationships with the major foundries. Partnering with these foundries enables us to access advanced technology PDKs, so we can support customers across the globe who need solutions on advanced nodes. Agile Analog has been a member of the TSMC OIP IP Alliance Program and Intel Foundry IP Alliance Program since 2023. In July 2024 we announced that we had joined the GlobalFoundries GlobalSolutions Ecosystem and delivered our IP to customers on FinFet and FDX processes.

Other company highlights in 2024 included being on the EE Times Silicon 100 list for semiconductor startups worth watching and being selected as a WIRED Trailblazer.

What was the biggest challenge your company faced in 2024? 

2024 was another challenging year across the semiconductor sector, with the ongoing geopolitical turmoil and economic downturn leading to more uncertainty. The impact of this was felt across the entire industry, with many companies frustrated and restricted by reduced budgets. The automotive sector in Europe was particularly badly hit, although Agile Analog’s exposure to this market is small.

How is your company’s work addressing this biggest challenge? 

Agile Analog has continued to drive forward to accelerate the adoption of our unique analog IP. Despite the challenges, we are proud that Agile Analog has grown as a business, achieving our highest number of IP sales and bookings. We work closely with our foundry and industry partners across the globe, and we have seen a surge in demand, especially for our data conversion IP, power management IP and security IP. Our aim is that when chip designers are looking for customizable analog IP then Agile Analog is the company that comes to mind. Our reach is truly global, with increased levels of interest from customers in North America and Asia. In October we announced a collaboration to support the work of the Southern Taiwan IC Design Industry Promotion Center.

What conferences did you attend in 2024 and how was the traffic?

Over the last 12 months the Agile Analog team has taken part in more global semiconductor foundry events than ever before – including the TSMC Technology Symposiums, TSMC OIP Ecosystem Forums, GlobalFoundries Technology Summits, Samsung Foundry Forums and Intel Connect. The audience and flow of traffic at these events have been encouraging. We have enjoyed showcasing our extending range of analog IP solutions, as well as talking with customers and partners about market trends and challenges. These discussions are invaluable as they form part of the decision-making process as we develop our product roadmap.

The Global Semiconductor Alliance (GSA) events have also been very interesting, including those focused on the Women’s Leadership Initiative (WLI). In March I attended the first GSA WLI EMEA event – Women in Semiconductors Conference – at the GSA International Semiconductor Conference in London. Then in October there was the first GSA WLI EMEA lunch and learn event in Munich. It’s great to see such a strong community that supports the career development of women working in the semiconductor industry.

What do you think the industry’s biggest growth areas will be in 2025?

Despite the fact that there are obviously ongoing global challenges, there are still reasons for cautious optimism in the semiconductor industry. AI and data centers have been key areas of interest in 2024, and we expect that these will continue to be the main growth areas in 2025. Indeed, the potential of generative AI has been a recurring talking point and its future impact on the world looks set to be game-changing.

Will you attend conferences in 2025?

In 2025, we will further strengthen our foundry relationships by participating in more of the foundry events. We may also review sector related events such as those focused on AI/Big data.  We really enjoy meeting existing and potential customers and partners face-to-face, so events are important for us.

What will be the main product focus areas for your company in 2025? 

At Agile Analog, our key product related priorities in 2025 will be working on advanced nodes and our security IP. Until now we have not been able to focus enough attention on developing our technology on advanced nodes. In 2025, we are keen to change this. We have exciting plans to collaborate with major foundries, such as TSMC and Samsung Foundry. There is also growing demand for our security IP solutions, especially for anti-tamper applications, so this range of our products will be at the forefront in 2025. As always at Agile Analog, meeting the needs of our customers comes first. We will continue to listen to and support our customers, and share our extensive expertise and experience in order to ensure that we can deliver the very best solutions possible.

Also Read:

Overcoming obstacles with mixed-signal and analog design integration

CEO Interview: Barry Paterson of Agile Analog

International Women’s Day with Christelle Faucon VP Sales Agile Analog

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Stanford showcases the first 60 GHz GaN IMPATT Oscillator at IEDM 2024

Stanford showcases the first 60 GHz GaN IMPATT Oscillator at IEDM 2024
by Daniel Nenni on 01-08-2025 at 10:00 am
Categories: Events

fig1

Key takeaways

  • IMPATT (Impact Ionization Avalanche Transit Time) sources operating at millimeter-wave and sub-THz frequencies using GaN technology have the potential to become some of the most powerful high-frequency (RF) generators.
  • At this year’s IEDM, a major breakthrough was reported: a GaN IMPATT RF oscillator achieving 60 GHz oscillation with an output power of 12.7 dBm.
  • The Stanford team, spearheaded the design and fabrication efforts, introducing key process innovations in edge termination, substrate thinning, and device packaging.
  • The QuinStar team contributed by designing the circuit and conducting RF characterization using their industry-standard setup to rigorously evaluate the device’s performance.
Performance comparison for IMPATT technology with various base materials

Gallium nitride (GaN) proves its prominence in high-power high-frequency RF applications due to its superior properties, such as high critical field, high mobility, and high saturation velocity. These merits make GaN a prime candidate for making IMPATT diodes, which promise to offer the best power-frequency performance among solid-state semiconductor RF devices. Theoretical analysis predicts GaN IMPATT diodes can offer a power-frequency product 450 times higher than their silicon counterparts. However, the experimental demonstration of GaN IMPATT diodes has been long hindered by the absence of achieving uniform avalanche. In 2020, an 800 MHz oscillation was observed for the first time in a GaN pn diode, capable of avalanche breakdown. The latest results presented by Stanford University at 2024 IEDM significantly advanced GaN IMPATT technology, reaching 60 GHz oscillation.

IMPATT diodes are such unique devices that they operate in the breakdown regime. For GaN, edge termination structures are vital to prevent field crowding and premature device breakdown. In this work, a 5-degree bevel mesa etch was utilized to ensure a uniform avalanche, verified by the uniform electroluminescence in the device during the unclamped inductive switching test.

5-degree bevel for edge termination and uniform avalanche electroluminescence

It’s worth emphasizing that developing high-performance IMPATT diodes requires much more than just meeting the avalanche requirement. It’s equally important to reduce the parasitic resistance to achieve efficient high-frequency operation and enhance heat dissipation to improve power density and device reliability. To address the above two challenges, the Stanford team, in collaboration with QuinStar Technologies Inc., developed a bulk GaN substrate thinning process and packaged the diode with the integration of a type IIa diamond heat sink.

The thinning process was carefully optimized to thin down bulk GaN substrate from 400 to 20 µm while keeping the avalanche capability in the diodes intact. The total on-resistance was reduced by 54 %, the leakage current remained minimal, and the breakdown voltage was maintained the same after the thinning process.

A specially designed ceramic pill with the integration of a diamond heat sink as the base was utilized to package the diode. This package offered minimal parasitic elements up to W-band operation. The adoption of a diamond heat sink supported the diode to sustain a high input power density of 2.65 MW/cm2 without burn-out.

GaN IMPATT diode with a substrate thickness of 20 µm and a fully-packaged device

The packaged diode was embedded in a waveguide resonant cavity and tested using an industry testbed at QuinStar Inc. The oscillator circuit featured a sliding backshort for impedance tuning. At a biasing current of 17.1 kA/cm2, the diode was capable of delivering a 60.8 GHz oscillation with 12.7 dBm power. This result marks the first GaN IMPATT oscillator reaching V-band operation, showcasing its great potential for mm-wave applications.

RF oscillation characteristics of the GaN IMPATT oscillator and performance benchmark

Looking ahead, there remains significant potential for improvement. Currently, the GaN substrate is the primary contributor to thermal resistance. To overcome this limitation, achieving a flip-chip configuration and enhancing the thermal boundary conductance between the GaN and diamond interface are critical for increasing the thermal capacity of GaN IMPATT diodes. Device-to-circuit co-optimization is another key to boosting the system efficiency and output power. Our next steps will center on electro-thermal co-design to fully unlock GaN’s potential for next-generation IMPATT technology.

The Presenter

Stanford University and QuinStar Technologies Inc. Under the leadership of Prof. Srabanti Chowdhury, the Wide-Bandgap Lab at Stanford has been at the forefront of GaN vertical device innovation. Their recent work on diamond and GaN integration for advanced thermal management has garnered significant attention for pushing performance boundaries.

The IMPATT devices, a core focus of Zhengliang Bian’s research, a Ph.D. student under Prof. Chowdhury, were a central part of this work who presented it at the IEDM this year. Avery Marshall led the circuit design and measurements, working closely with Lissete Zhang and Tracey Lee. Key innovations in edge termination, wafer thinning, heat sinking, and uniquely designed packaging enabled the successful demonstration of this technology, paving the way for a promising roadmap in this field.

Also Read:

Intel Presents the Final Frontier of Transistor Architecture at IEDM

TSMC Unveils the World’s Most Advanced Logic Technology at IEDM

An Invited Talk at IEDM: Intel’s Mr. Transistor Presents The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead

IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier Mii

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Stochastic Effects Blur the Resolution Limit of EUV Lithography

Stochastic Effects Blur the Resolution Limit of EUV Lithography
by Fred Chen on 01-08-2025 at 6:00 am
Categories: Lithography

Stochastic Effects Blur the Resolution Limit of EUV Lithography

Conventionally, the resolution limit of a lithography system with wavelength l and numerical aperture NA is given by half-pitch = 0.25 wavelength/NA. With the use of EUV lithography, however, electron blur needs to be added [1]. The impact of this blur is to reduce the contrast [2]. Blur reduces the modulation amplitude by a factor of exp(-0.5*(2*pi*blur/pitch)2). Consequently, the normalized image log-slope (NILS) can drop below the target value of 2.0 (10% CD change for 10% dose change).

Another, more serious issue with EUV lithography, has been its stochastic behavior. Ideally, even with blur, we expect a straight-line image to be projected from a straight line on the mask, with smooth edges. In reality, we expect varying blur from electron scattering due to resist inhomogeneity. Besides locally varying blur, the number of absorbed photons per square nm varies according to Poisson statistics (std. dev. = sqrt(mean)). We also expect locally varying electron yield per absorbed EUV photon [3-6]. Thus, the actual image formed will have randomness, or stochasticity.

Figure 1 shows the simulations of scattered electrons are shown for 30 nm, 40 nm, and 50 nm pitches.

Figure 1. Scattered electron density plotted for 30 nm, 40 nm, and 50 nm pitch horizontal lines. Absorbed dose=60 mJ/cm2, resist thickness = pitch, 5/um absorption, 3-5 electrons/absorbed photon, mean blur = 5 nm, blur std. dev. = 1 nm. The pixel size is 1 nm.

The smaller the pitch, the less well-defined the edge. By setting an appropriate threshold to roughly get a half-pitch linewidth, the edge roughness becomes obvious. Also, the tendency to defects is highlighted by the presence of above threshold pixels outside the edge (“bright defect pixels”), and below threshold pixels within the edges (“dark defect pixels”). More defective pixels means more information lost from the image, particularly edge position, and if severe enough, actual resist defects result.

The sum of bright and dark defect pixel % increases with decreasing pitch as expected (Figure 2).

Figure 2. Left: sum of bright defect pixel % of unexposed area and dark defect pixel % of exposed area, as a function of pitch. The effect of reducing the dose is shown for 50 nm pitch. Right: definitions of bright and dark defects.

Since the dark defect pixels dominate, a dose increase should help reduce the defect pixel %. As expected from Poisson statistics, the dose should be inversely proportional to the cube of the pitch. The # of photons absorbed scales with the thickness (proportional to pitch) and the exposed area (proportional to pitch2).

The rapid rise of required dose with decreasing pitch is a burden on EUV system throughput. Also, the resist would need to be changed to accommodate a much different (≥2X!) dose. If the throughput hit is too severe, or the resist dose is too high to accommodate, it can pose a practical resolution limit even though k1>0.25. In the case shown in Figure 3, a dose upper limit of 2x the dose used at 50 nm pitch would put 40 nm pitch as the practical resolution limit.

Figure 3. Projected dose varies as the inverse cube of pitch to preserve the same degree of photon noise. In this example, a dose upper limit of 2x the dose used at 50 nm pitch would put 40 nm pitch as the practical resolution limit.

To sum up, the resolution limit of EUV lithography is not determined by only the factors limiting DUV lithography. Electron blur and stochastic effects need to be considered as well. Due to stochastics, dose is expected to increase significantly as pitch decreases. With smaller pitch, fewer photons are absorbed, and there is more impact from blur. Higher dose impacts throughput, resist choice. Consequently, the practical resolution limit of EUV lithography will depend on dose as well as the resist. It is no surprise to see multipatterning is used for ~30 nm pitch and below [7].

References

[1] G. He et al., “Stochastic EUV Resist Model,” ISEDA 2023, p.477.

[2] B. J. Lin, “Optical Lithography with and without NGL for Single-Digit Nanometer Nodes,” Proc. SPIE 9426, 942602 (2015).

[3] G. Denbeaux et al., “The role of secondary electrons in EUV resist,” EUVL Workshop 2014.

[4] D. F. Ogletree, “X-rays, Electrons and Lithography: Fundamental Processes in Molecular Radiation Chemistry,” EUVL Berkeley 2017.

[5] A. V. Pret et al., ”Modeling and simulation of low-energy electron scattering in organic and inorganic EUV photoresists,” Proc. SPIE 10146, 1014609 (2017).

[6] P. Theofanis et al., “Modeling photon, electron, and chemical interactions in a model hafnium oxide nanocluster EUV photoresist,” Proc. SPIE 11323, 113230I (2020).

[7] Y-J. Mii, “Semiconductor Industry Outlook and New Technology Frontiers,” IEDM 2024 Keynote.

The full video presentation of this article is available here:

Also Read:

Stochastic Pupil Fill in EUV Lithography

Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV

Why NA is Not Relevant to Resolution in EUV Lithography

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Semiconductor Industry Update Webinar – Registration Now Open

Semiconductor Industry Update Webinar – Registration Now Open
by Daniel Nenni on 01-07-2025 at 10:00 am
Categories: Events, Future Horizons, Semiconductor Services

Semiconductor Futures 2025

At first glance, the headline annualized semiconductor market growth numbers remain strong, with HBM Memory leading the way and AI GPUs continuing to sell in a frenzy. However, a deeper dive into the details reveals a much bleaker picture. Inventory levels remain stubbornly high, and mainstream capacity utilization rates are painfully low. With interest rates still elevated and global GDP growth—aside from the USA—remaining weak, the outlook for the industry is challenging. Now, more than ever, is the time for calm judgment, sound reasoning, and dependable market data.

  • Has the 2023 Market Bust Finally Turned the Corner?
  • What Is the Market Outlook for 2025?
  • When Will IC Unit Growth Return to the Industry?
  • What Are the Likely Ramifications of China’s Massive CapEx Overspend.
  • Will the Current AI Market Boom Continue Throughout 2025, or Is It Set to Fall?

Find out the answer to these and other key questions at Future Horizons’ IFS2025 Annual industry Update webinar, Tuesday 14 January 2025, at 3pm UK GMT, registration now open.

Discount for 3 or more attendees from the same company.
Can’t attend in person?  Video recording option also available.

Full Details at:

https://www.futurehorizons.com/page/136/Industry-Update-Webinar

Register at:

https://us05web.zoom.us/webinar/register/6017343465502/WN_bBxd-cH2TEyFotVJIl0YxA

What Will You Hear

This one-hour broadcast will focus on the chip industry outlook, including:

  • What Happened To The Chip Market In 2024?
  • What Is The Updated Market Outlook For 2025?
  • What’s Happening In CapEx, Investment, And Onshoring Trends?
  • How Will President Trump’s Policies Impact The Global Chip Industry?
  • How To Build Resilient Business Strategies, Plus
  • Opportunity to ask specific questions in advance, during and after the webinar.
Who Should Attend

All companies, small and large, from startups to established market leaders.

  • Key decision-makers in the design, manufacture, or supply of semiconductors.
  • Government organizations in industry, trade, and investment.
  • Those involved in M&A, investment, or finance within the electronics industry.
  • Senior industry executives planning future marketing strategy.
Your Trusted Industry Advisor

Founded in 1989, Future Horizons has been in the business of forecasting and analyzing the semiconductor market for 35 years and has been a trusted advisor to governments, investors, startups, and most of the top global semiconductor firms. Our forecast track record and hands-on industry experience, dating back to the first commercial IC, longer than any other analyst and most industry execs, make this a must-attend event for key decision makers in semiconductors, electronics, and all related industries. We always present accurate and insightful analysis at these events, consistently helping our clients save time and money with our insightful and accurate analysis of the industry.

Fee

For a small investment of just UK £150 plus £30 UK VAT, you will gain accurate industry insight to make good strategic decisions in these uncertain times.

  • Discount available for 3 or more attendees from the same company/organization.
  • Can’t attend? No need to miss out, order the webinar video recording and slides instead.
  • If already registered or not directly suitable for you, please pass it to a colleague or associate.
  • The event can also be repeated on-line or in-person in-house for your added convenience and flexibility.

Malcolm Penn
Chairman and CEO

Follow us on Twitter, like us on Facebook and join our Linked In Group and receive regular industry news, information and comments.

Registered Company: 4380991 / mail@futurehorizons.com

Also Read:

WEBINAR: 2025 Semiconductor Year in Preview

Intel Presents the Final Frontier of Transistor Architecture at IEDM

TSMC Unveils the World’s Most Advanced Logic Technology at IEDM

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ML and Multiphysics Corral 3D and HBM

ML and Multiphysics Corral 3D and HBM
by Bernard Murphy on 01-07-2025 at 6:00 am
Categories: 3D IC, AI, Ansys, Inc., Chiplet, EDA

multidie and HBM stacks min

3D design with high-bandwidth memory stacks (HBM) has become essential for leading edge semiconductor systems in multiple applications. Hyperscalers depend on large AI accelerator cores supported by 100GB or more of in-package HBM to handle trillion parameter AI models. Autonomous Drive (AD) vehicles may handle smaller individual tasks but more of them through multiple levels of sensing and fusion support, computer vision, graphics, safety, security, and communication objectives. Similar requirements are appearing in aerospace and other applications. All require 3D integration with HBM to maximize performance, minimize latency, and minimize power consumption. Manufacturing technologies to build such systems are already in place but optimizing such a design introduces new physics challenges in performance and reliability.

The Physics of Large System Design

There’s only so much circuitry you can fit on a single silicon die, even in the most advanced processes. Bigger designs must split across multiple chiplets (die) but can now connect very effectively inside a single package, greatly reducing the performance and power hit compared to an equivalent circuit between packaged components on a PCB. The advantage is especially clear for large memory access implemented as stacked HBM chiplets within the same package, for which access latencies are greatly improved over off-chip DRAM.

Managing the physics of large semiconductor designs was already prominent before multi-chiplet designs appeared. Beyond the usual design objectives (functionality, performance, power and area/cost) a product design team must optimize for: over-heating with potential to damage/compromise the system; inadequate power distribution for functional demand undermining performance and reliability; electronic crosstalk impacting signal integrity; die/chiplet warping through heating resulting in broken bond connections. Tools to analyze these factors for a single die are already familiar and a well-understood strength for Ansys: power integrity (EM/IR) analysis, thermal analysis, signal integrity and mechanical analysis coupled with thermal.

Scaling multiphysics analysis up to multi-chiplet designs introduces new challenges. Thermal becomes a bigger issue especially in stacked structures where thin chiplet substrates provide little thermal isolation between layers. This analysis problem isn’t just bigger than for an already complex single die multiphysics analysis; in a 3D/HBM structure all these factors are coupled and must be co-optimized.

Multiphysics, Coupling and ML

Lang Lin (Principal Product Manager at Ansys) gave an excellent webinar talk recently on this topic, illustrating with emphasis on an HBM stack, sitting on top of a logic die and next to CPUs or GPUs on the interposer. One point he made is that traditional PVT (process-voltage-temperature) corner analysis for a single die won’t necessarily work for analysis of a complete structure of stacked chiplets. In an HBM stack, chiplets may have different assembly corners due to coupling effects. One might best be assigned a temperature of 90 degrees, at 0.8 volts and a fast-fast process. Another (in the same stack) should be assigned a temperature of 100 degrees, 0.9 volts and a typical-typical process. And so on, down the stack. Raising an obvious question – how do you figure this out?

A key point Lang made is that physics factors in this tightly packed environment are strongly coupled and all centered around thermal considerations.

Coupling implies that you can’t just optimize for one factor at a time. Temperature affects the power delivery network, timing, signal integrity which in turn can affect temperature. In a heterogenous integration with HBM, CPUs, GPUs, etc., etc., optimizing across all these factors would become a nightmare. Converging to an optimal physics solution requires (no surprise) intelligent and automated guidance. Ansys accomplishes this through their OptiSLang system which will search intelligently through vast parametric spaces to find robust solutions automatically. I’m convinced this is the way of the future in system level optimization tasks of all kinds.

Ground Proofs

Lang illustrated with a couple of live examples, the first working with TSMC on HBM optimization for warpage/stress in assembling a stack, which can result in yield loss. Here thermal cycling is based on manufacturing requirements rather than on use-cases, however I would think that temperature ranges they show in manufacturing are at least as stressful as in mission mode. TSMC and Ansys used the flow to estimate warpage/stress at each assembly step, to come up with an optimal manufacturing assembly sequence.

In another case study, Ansys worked with a different company to optimize the signal integrity of high-speed HBM interconnect (connecting to compute chiplets) on a 2.5D interposer. Here they were able to propose an optimal routing pattern for the multi-bit interconnect to minimize (transmission line) overshoot.

Pretty impressive. You can register to watch the webinar HERE.

Also Read:

A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design

Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters

Ansys and eShard Sign Agreement to Deliver Comprehensive Hardware Security Solution for Semiconductor Products

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CES 2025 and all things Cycling

CES 2025 and all things Cycling
by Daniel Payne on 01-06-2025 at 10:00 am
Categories: Events
8 Comments

UrbanGlide 3

CES 2025 was held from January 7-10, once again in Las Vegas, so I attended virtually to gather together all of the tech and trends related to cycling, which is becoming more electrified each year. E-bikes return as the biggest category and from my cycling rides I can see how popular these bikes are becoming in Oregon for commuters and people that enjoy being outdoors more without having to sweat as much. The latest e-bikes have electric motors and batteries neatly hidden and integrated into the frame or rear hub, along with a display on the handlebars to let you know how much charge remains and other metrics.

E-Bikes

This is still the fastest-growing and most profitable sector in the cycling world, with higher ASPs than pedal-powered bikes

Livall conversion kit

With this accessory your regular bike can be converted into an e- bike, as it connects to the seat tube and moves your rear wheel by friction. It even earned a 2025 Innovation Award from CES. I question the efficiency of power transfer and the robustness of the design, but marvel at the retrofit market.

LIVALL PikaBoost 2

Urtopia – Titanium e-bike

This e-bike has a strong frame made from titanium, great for commuting or gravel riding and compatible with traditional shifting, weighing only 23.8 pounds.

Urtopia Titanium Zero

Urtopia

Yes, with some AI technology called ChatGPT this bike provides navigation, safety alerts and gives motivation to stay fit. Comes in three models.

Fusion GT

Vanpowers

Four e-bike models were shown this year at CES, and the UrbanCross-Ultra provides a 60 nile range.

UrbanCross-Ultra

For off-road cycling there’s the GrandTeton-Ultra with a 65 mile range.

GrandTeton-Ultra

If you prefer a fat tire e-bike, then there’s the Cycanon with a 60 mile range.

Cycanon

Urban commuting with shocks and a rack are found in the UrbanGlide-Standard e-bike.

UrbanGlide-Standard

Muon

This German-based vendor has e-bikes in several styles, all named after elementary particles: Elon, Axion, Lepton, Bradyon. Some of their models use a belt drive, instead of a chain for easier maintenance.

Elon

ENGWE

This brand has multiple e-bike categories: commuter, fat-tire off road, folding, step-through, e-scooter. The M20 2.0 looks more like a motorcycle, has an 80 mile range, and comes with complete suspension.

M20 2.0

Blaupunkt

I remember this brand mostly for their car audio gear, and they’ve expanded into Class 2 e-bikes which have a 40 mile range, while being foldable.

Fiene eBike

SOL

A 2025 CES Innovation Award honoree, SOL showed off their Pocket Rocket S, capable of 55 mph speeds and a 70 mile range. The design is rather artistic, looking like you’re sitting on a cylinder rocket.

Pocket Rocket S

HIMIWAY

This Shanghai-based company offers a full-range of e-bikes:  mountain, kids, city, cargo, folding, step through, full suspension, motorbike.

City eBike

Heybike

They showed several new models of e-bikes this year: Polaris, Helio, Alpha (commuter), X (folding).

Helio Series

AIMA

With 400 dealers around the globe, this brand offers  e-bikes with a 20-inch fat tires – Big Sur, and a step-thru bike with 750W motor – Santa Monica.

Santa Monica

OKAI

Another company from China with a presence in Europe and North America is showing off a line of five e-bikes and eight e-scooters this year.

OKAI

Bosch

From Germany we have e-bike motors and apps.

Bosch Technology

C-Star Industrial Limited

From Shenzhen, China this 24 year old company showed off their e-scooters.

CS-P14

Komda

Based in Hong Kong, this vendor has a range of e-bikes: cargo, mountain bike, folding, city. They also offer traditional bikes: kids, folding, city.

Electric Cargo Bike

Moqous

From South Korea comes a new company that provides both a folding e-bike, and pedal bike designed for people that want to conserve space and have short commutes.

Pop-Cycle-E

Oh Wow

Offering both e-bikes and e-trikes, this California company has many models to choose from.

Conductor Trike

 

Altovetti

It sounds Italian, but this is a Chinese brand with a step-through e-bike, available in a variety of colors, designed for commuting.

Altovetti

Rundeer

Designed for off-road and commute use, this company offers three models.

Rundeer Starry Sky

Spard

All of these e-bikes require a battery and that’s where Spard comes in, supplying the many different battery form factors: external, in-tube, dual system, bottle cage, integrated, semi-integrated, rear carrier.

e-bike battery

Pedal Bicycles

Biky

This brand has kids bikes that look like a lot of fun to get started in cycling.

Biky Air 12

Trainers

On rainy or cold days a cyclist can opt to ride indoors using some type of trainer setup.

Speediance

At first this looked just like another Peleton competitor, but it actually integrates with all the popular platforms: Zwift, Strava, Apple Health, Samsung, Garmin.

VeloNix

Yesoul

A spin bike with integrated display in a few models from this Chinese vendor where you follow sessions to stay fit.

Yesoul G1M Max

Garmin

This American brand has a range of indoor trainers from low-cost on-wheel, up to their smart trainers that work with popular apps like Zwift.

Tacx Flux 2

VirtuRide

This spin bike comes with a VR headset, so you get to view real terrain while your bike tilts side-to-side, and even heads up and down hill.

VirtuRide

Real Design Tech

Smart rollers with a sturdy arm to hold your bike upright, keeping you from falling over, and compatible with the most popular indoor cycling app Zwift.

Ultiracer

Sunny

Offering over 20 varieties of trainers, you will find something to fit your taste and budget.

Smart Pro Belt Drive Indoor Cycling Exercise Bike

Accessories

Alps Alpine

This rear-facing camera sends a live view to a display on your handlebars of traffic coming from behind you, keeping you safer from motorists.

RS 1000 Bike Camera

 

Aizip

Trek Bike and Aizip collaborated to create a demo of a Small Language Model Assistant for biking, bringing together Aizip technology and Trek Bike domain expertise. The Trek e-MTB has an Aizip demo helmet to make off-road rides and routes easier to plan, so that you don’t get lost,  recommend new routes, offer coaching and provide a safety alert in case of a crash.

Aizip and Trek

Livall

Smart helmets for road and mountain bikers include lighting to indicate braking, fall detection and SOS alert, voice navigation, and an alarm for security. My friends with rear lights on their helmets really improve visibility for motorists, as the high position of the lights are closer to eye level.

BH60SE Neo

SuperTooth

This gizmo clips onto your existing bike helmet and provides a hands-free Bluetooth connection for listening to music, making phone calls, or as an intercom, all while cancelling out wind noise.

Roamee

aabo

Instead of measuring heart rate on a chest-strap monitor, why not use a ring that also tracks your sleep, stress and other physical activities?

aaboRing

CRNK

Protecting your head while cycling is paramount to safety and CRNK has designed over a dozen models, and some have added lighting to improve visibility.

Genetic Alpha

Circular

Another ring-based fitness device to monitor your heart rate along with haptic feedback and an app to show you what’s happening throughout the day and even sleep time.

Circular Pro

Garmin

A long-time provider of bike computers ranging from entry-level to the flagship 1050 device.

Garmin 1050

Riduck

Get some pro-level cardio training with this AI-based app that looks at your heart rate monitor and cycling power meter data recorded by Strava. Learn what your FTP, VO2MAX and FATMAX numbers are.

Riduck app

Bosch

Locking your e-bike makes sense, but adding even more security comes from Bosch’s eBike Lock system that turns your battery off when you step away from the e-bike. A thief can still cut your physical bike lock off, but then be stopped from riding your e-bike away with any motor support as the battery is still turned off. You install an app on your phone, or use the Bosch Kios or Nyon e-bike removable displays as your key to unlock or lock the battery.

eBike Lock

 

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Can LELE Multipatterning Help Against EUV Stochastics?

Can LELE Multipatterning Help Against EUV Stochastics?
by Fred Chen on 01-06-2025 at 6:00 am
Categories: Lithography

Can LELE Multipatterning Help Against EUV Stochastics

Previously, I had indicated how detrimental stochastic effects at pitches below 50 nm should lead to reconsidering the practical resolution limit for EUV lithography [1]. This is no exaggeration, as stochastic effects have been observed for 24 nm half-pitch several years ago [2,3]. This then leads to the question of whether using multipatterning to get below the practical resolution limit can be of any help in avoiding these stochastic effects.

Multi-patterning in its most basic form involves forming a layer pattern with at least two mask exposures. In the simplest case, the LELE (Litho-Etch-Litho-Etch) approach, the target layer pattern is divided into two portions, which are combined by interleaving features such as lines. This is necessary when a single exposure cannot resolve (without defects, deformation, or feature loss) the minimum pitch between two features. The two features separated by this minimum pitch must then be exposed separately. For example, two 15 nm lines separated by 30 nm pitch would need to have two exposures: a first exposure to pattern one 15 nm line in resist, followed by an etch, and a second exposure to pattern the second 15 nm line in a subsequently recoated resist, followed by the etch.

Given that 15 nm lines on 30 nm pitch are known to be impacted by stochastic effects, it is natural to ask whether the same lines fare better on 60 nm pitch. Figure 1 shows a qualitative comparison. Without the actual mask structure details being known, a classical binary grating is used to represent the mask, and the illumination is the dipole used for 30 nm pitch, which will generated two beams from the mask for the 30 nm pitch case, and three beams from the mask (1st order being the middle beam) for the 60 nm pitch case. The same simulation model and conditions were used as in [1].

Figure 1. A 15 nm drawn line on 60 nm pitch (left) and 30 nm pitch (right). The same illumination is used for both cases (dipole for 30 nm pitch). The lines were modeled using binary grating features as the mask pattern. Under the shown modeling conditions, the 60 nm pitch is slightly better due to the higher photon and electron density in the exposed area.

The photon density happens to be higher for the 15 nm drawn line on 60 nm pitch. However, the NILS of the 15 nm line on 60 nm pitch is lower than on 30 nm pitch (1.7 vs. 2.8 even without blur). This means more pixels within the exposed region have a higher chance of the local photon density dropping below the threshold to become defective. The dark defect pixel % is a little lower for the 60 nm pitch compared to 30 nm pitch (~23% compared to ~30%). While it visually looks a little better, the edge definition from the scattered electron density is still poor. In addition, the stochastic defect rate has been found to be higher when the CD is less than the half-pitch [5,6]. Therefore, we must conclude that LELE patterning does not help avoid detrimental stochastic effects. The key reason is the CD being printed is still too small.

A way around this is to use spacers to define the CD. This is used in self-aligned double patterning (SADP) as well as SALELE (self-aligned LELE) [6]. This allows larger features to be printed by the exposure, e.g., 30 nm instead of 15 nm on 60 nm pitch. Interestingly, at around 40 nm pitch, double patterning by SADP or SALELE may overlap for DUV and EUV, since stochastic effects still look severe at 40 nm pitch [1], while 80 nm pitch is achievable by DUV single exposure [7].

Thanks for reading Exposing EUV! Subscribe for free to receive new posts and support my work. Pledge your support here.

References

[1] F. Chen, Stochastic Effects Blur the Resolution Limit of EUV Lithography.

[2] D. van den Heuvel et al., “Process Windown Discovery Methodology Development for Advanced Lithography,” ASMC 2016.

[3] S. Das et al, “E-beam inspection of single exposure EUV direct print of M2 layer of N10 node test vehicle,” Proc. SPIE 10959, 109590H (2019).

[4] P. de Bisschop and E. Hendrickx, “On the dependencies of the stochastic patterrning- failure cliffs in EUVL lithography,” Proc. SPIE 11323, 113230J (2020).

[5] J. Church et al., “Fundamental characterization of stochastic variation for improved single-expose extreme ultraviolet patterning at aggressive pitch,” J. Micro/Nanolith. MEMS MOEMS 19, 034001 (2020).

[6] F. Chen, SALELE Double Patterning for 7nm and 5nm Nodes.

[7] H. Hu et al., “K=0.266 immersion lithography patterning and its challenge for NAND FLASH,” CSTIC 2015.

Also Read:

Stochastic Pupil Fill in EUV Lithography

Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV

Why NA is Not Relevant to Resolution in EUV Lithography

Posted on

WEBINAR: 2025 Semiconductor Year in Preview

WEBINAR: 2025 Semiconductor Year in Preview
by Daniel Nenni on 01-03-2025 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights

Webinar 2025 semiconductor year in preview

TechInsights has been in the semiconductor analysis business for more than 35 years and is THE most trusted source of semiconductor information. TechInsights started as a reverse engineering and IP analysis company but has grown into much more. I remember waiting for the teardown reports before buying electronics to make sure I knew what was inside. Now I read them to get detailed information on semiconductor process technologies.

SemiWiki blogger Scotten Jones sold his company IC Knowledge to TechInsights two years ago and before that TechInsights bought Dan Huctheson’s research company VLSI Design. They also acquired The Linley Group and The McClean Report amongst others. Rest assured, our semiconductor secrets are safe with TechInsights.

To start the new year TechInsights is hosting a free webinar preview of 2025. I hope to see you there:

2025 will be an eventful year in the semiconductor industry—don’t expect the unexpected, be prepared!

Join TechInsights experts behind The McClean Report for our latest webinar 2025 semiconductor year in preview. Get advance insight into the key events in 2025 and what they mean to your business:

Register: January 15, 2025 – 10:00 AM EST
Register: January 16, 2025 – 11:00 AM JST / KST

Key Topics to be Covered:
2025 Tariff Shake-Up: Are You Ready?

January starts with a new US administration promising to shake up tariffs—what are the scenarios you should plan for?

NVIDIA vs. AMD & Intel: AI Accelerator Showdown

In March, NVIDIA will unveil the successor to GraceHopper, and later in the year AMD and Intel will launch next generation AI accelerators. Will NVIDIA keep its crown?

2nm Breakthroughs: Intel, TSMC, and Rapidus Lead

2025 will be the year of 2nm and beyond, with Intel 18A and TSMC N2 coming online in the first and second half of 2025 respectively, and details of Rapidus’ 2nm process expected to emerge.

And that’s not all… Altera, Cerebras, Coreweave, KIOXIA, and SanDisk will all woo Wall Street with new listings, Apple will launch new devices at WWDC in June, and HBM4 specifications will be announced. 2025 will be an eventful year in the industry—don’t expect the unexpected, be prepared!

Presenters:

David MacQueen, Director, Executive Insights and James Sanders, Senior Analyst.

As the Director, Executive Insights, David MacQueen is tasked with covering the semiconductor value-chain to identify emerging technologies and new opportunities for research teams, while ensuring alignment across the research produced by TechInsights. He has over 20 years of experience in semiconductor-related industries and has an inherent ability to contextualize data that helps clients understand the big picture.

James Sanders is a Senior Analyst at TechInsights with over 5 years of experience as an industry analyst, and 7 years of experience as a technology journalist. James has a passion for researching the innovations being made possible through high performance and quantum computing and is fascinated by application processor and system architecture design that enables these innovations. He enjoys having the ability to work closely with clients and provide insights on the value and utility of these new advancements.

About TechInsights

Regarded as the most trusted source of actionable, in-depth intelligence related to semiconductor innovation and surrounding markets, TechInsights’ content informs decision makers and professionals whose success depends on accurate knowledge of the semiconductor industry—past, present, or future.

Over 650 companies and 100,000 users access the TechInsights Platform, the world’s largest vertically integrated collection of unmatched reverse engineering, teardown, and market analysis in the semiconductor industry. This collection includes detailed circuit analysis, imagery, semiconductor process flows, device teardowns, illustrations, costing and pricing information, forecasts, market analysis, and expert commentary. TechInsights’ customers include the most successful technology companies who rely on TechInsights’ analysis to make informed business, design, and product decisions faster and with greater confidence. For more information, visit www.techinsights.com.

Also Read:

5 Expectations for the Memory Markets in 2025

VLSI Technology Symposium – Intel describes i3 process, how does it measure up?

Intel High NA Adoption

Posted on

Accelerating Automotive SoC Design with Chiplets

Accelerating Automotive SoC Design with Chiplets
by Kalar Rajendiran on 01-02-2025 at 10:00 am
Categories: Automotive, Cadence, Chiplet, EDA, IP

System Chiplet

The automotive industry is evolving rapidly with the increasing demand for intelligent, connected, and autonomous vehicles. Central to this transformation are System-on-Chip (SoC) designs, which integrate multiple processing units into a single chip for managing everything from safety systems to in-car entertainment. However, as these systems become more complex, traditional SoC designs face challenges around performance, power, and scalability. Chiplet-based architectures are now driving innovation by offering more flexible, efficient, and customizable solutions for automotive SoCs.

Cadence recently hosted a webinar on this topic, with Moshiko Emmer, a Distinguished Engineer for the company’s Silicon Solutions Group (SSG) presenting.

Benefits of Leveraging Chiplets in Automotive SoC Design

Chiplet-based designs are reshaping automotive SoC development by offering a modular and scalable approach. Each chiplet, such as CPU cores, memory units, or specialized processing units like NPUs, is a self-contained module that can be easily integrated into larger systems. As automotive systems advance, especially with ADAS, infotainment, and autonomous driving, chiplet architectures provide several key advantages.

-Enable engineers to focus on specific value-added functions, reducing development time, cost, and risk while improving time-to-market.

-Allow for highly scalable designs, meeting the varying performance and power needs of different vehicle segments.

-Ensure long-term cost efficiency and adaptability to new technologies through reuse of chiplets across multiple generations of SoCs

By combining off-the-shelf chiplets with specialized automotive IP, manufacturers can build comprehensive solutions, benefiting from a broad ecosystem of reference designs and industry-standard IP.

Accelerating Automotive SoC Design

Adopting chiplet-based designs for automotive SoCs involves several essential efforts to ensure performance, safety, and reliability.

Chiplet Frameworks

A robust chiplet framework ensures the seamless integration of chiplets from different vendors. Standardized protocols and interfaces, such as UCle™, streamline the integration process, allowing for more efficient chiplet-based SoC designs. Cadence’s System Chiplet framework enables designers to integrate and connect multiple chiplets in a cohesive architecture, facilitating high-performance, scalable designs tailored for automotive applications.

SoC Design Cockpit

The SoC Design Cockpit approach helps automate the design process with correct-by-construction tools, ensuring that the final system meets all performance and safety requirements. This platform enables extensibility for customizing automotive-specific features like real-time processing and high-speed data handling. For example, the Cadence System Chiplet comes with pre-designed frameworks for automotive applications, allowing engineers to quickly select the necessary chiplets and integrate them efficiently into a full SoC. The cockpit’s automated tools help reduce manual intervention, ensuring high-quality and safe designs for automotive use.

Virtual Platforms

Virtual platforms enable early software development before hardware is available, which is especially valuable for complex systems like ADAS and infotainment. Tools like Cadence Helium™ software digital-twin allow engineers to simulate hardware, test software, and avoid costly errors before physical hardware is built. By integrating Cadence’s Neo NPU chiplet, which is designed for AI and machine learning tasks, into a virtual platform, developers can simulate the performance of advanced automotive applications such as real-time object detection, predictive analytics, and autonomous driving algorithms.

Design Services and Ecosystem Collaboration

Collaborating with design services partners and leveraging off-the-shelf chiplets accelerates the integration of complex systems such as sensor fusion and machine learning. Working within a broad ecosystem of partners can also speed up the development of automotive SoCs. Cadence’s Neo NPU chiplet enables integration with machine learning workflows, supporting the development of intelligent, real-time systems for automotive applications. Together with the System Chiplet framework, these chiplets facilitate rapid prototyping and customization, accelerating time-to-market.

Chiplet Testchips: Ensuring Automotive SoC Reliability

Given the critical nature of automotive applications, ensuring the reliability and safety of chiplet-based SoCs is paramount. Chiplet testchips validate the performance and functionality of individual chiplets before integration into the full SoC. Testchips are essential for verifying that chiplets meet the functional requirements of automotive systems like ADAS and infotainment, as well as for ensuring compliance with safety standards such as ISO 26262.

Summary

Chiplet-based architectures are transforming automotive SoC design by offering scalable, customizable, and cost-efficient solutions. By leveraging Cadence’s System Chiplet and Neo NPU chiplet frameworks, as well as tools like the SoC Design Cockpit and Cadence Helium™ software digital-twin, automotive manufacturers can accelerate the development of next-generation vehicle technologies like ADAS, autonomous driving, and infotainment. Chiplet testchips further ensure the reliability and safety of these designs. As chiplet technology continues to evolve, it will unlock new opportunities for the automotive sector, driving smarter, safer, and more connected vehicles.

For more details, refer to the following:

Cadence Automotive Solutions page.

You can access this webinar on-demand from here.

Also Read:

Accelerating Simulation. Innovation in Verification

Accelerating Electric Vehicle Development – Through Integrated Design Flow for Power Modules

Compiler Tuning for Simulator Speedup. Innovation in Verification