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Kirin 9030 Hints at SMIC’s Possible Paths Toward >300 MTr/mm2 Without EUV

Kirin 9030 Hints at SMIC’s Possible Paths Toward >300 MTr/mm2 Without EUV
by Fred Chen on 12-28-2025 at 2:00 pm
Categories: Lithography, Semiconductor Services, TechInsights

Number of masks required for the M0 through M3 layers

Earlier this month, TechInsights did a teardown of the Kirin 9030 chip found in Huawei’s Mate 80 Pro Max [1]. Two clear statements were made on the findings: (1) the transistor density of SMIC’s “N+3” process was definitely below that of the earlier 5nm processes from Samsung and TSMC, and (2) metal pitch was aggressively scaled using DUV multi-patterning. Given that the density (formula defined in [2]) is less than 125 MTr/mm2 (Samsung 5LPE), corresponding to a track pitch of 36 nm and gate pitch of 54 nm [3], we can infer that it is the minimum metal pitch that was aggressively scaled, going beyond double patterning. In this article, we will go over the possible paths ahead for SMIC that could ultimately enable transistor densities >300 MTr/mm2, knowing that minimum metal pitch is now likely being patterned by some form of self-aligned quadruple patterning (SAQP).

Some Guiding Numbers for Pitch Scaling

The actual pitches for SMIC’s latest N+3 and previous N+2 processes were found by TechInsights but never revealed publicly. When those processes are discussed in this article, representative pitches will be used.

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It will be assumed that getting to >300 MTr/mm2 will follow the path shown in Table 1. At N+3, the M0 layer was shrunk aggressively; this will be repeated for M2 at N+4.

Table 1. Possible pitch shrink path from N+2 to >300 MTr/mm2. See text for explanations.

A number of clarifications are needed to explain the numbers used in Table 1.

The transistor density is calculated from the gate pitch and the track pitch, which is taken to be M2 here. We know that for N+3, the track metal is not the minimum pitch metal. The formula is the same as used in [2], with 60% weight on 4-transistor NAND cells covering 3 gate pitches, and 40% weight on a 32-transistor flip-flop covering 19 gate pitches. This gives [6*4/3+0.4*32/19]/(gate pitch*cell height)=1.474/(gate pitch*cell height) as the transistor density formula.

At the “2nm” node, the transition to buried power rail is expected, which enables the cell height to go from 6 tracks to 5 tracks.

For older nodes, M1 pitch can be less that gate pitch, e.g., 2/3 gate pitch, but 36 nm pitch with EUV has stochastic defect density concerns [4,5], so it has been expected that M1 pitch will be relaxed to the same as gate pitch.

A 44 nm gate pitch and 22 nm pitch with buried power rails allowing 5-track cells would be necessary to get over 300 MTr/mm2.

Different SAQP Approaches Proposed

Achieving a minimum metal pitch as small as 30 nm or smaller is no trivial feat. Two methods have been proposed by Huawei and SiCarrier.

Double SALELE

Huawei’s patent CN117751427 discloses what is essentially the SALELE [6] approach applied twice. “SALELE” stands for “self-aligned litho-etch-litho-etch;” it is a more sophisticated version of the traditional litho-etch-litho-etch double patterning approach. Double SALELE means doing SALELE twice to get the quadruple patterning effect (Figure 1).

Figure 1. Double SALELE approach. Left: First litho-etch (blue), followed by spacer (gray), then etch block/cut (yellow). Center: Second litho-etch (green), followed by etch block/cut (purple). This completes the first SALELE. Right: Second SALELE completed.

In the SALELE approach, sidewall spacers are applied to a first set of lines, formed conventionally, by “litho-etch.” Then these lines may be cut using etch blocks patterned by a second mask. A third mask is used to pattern the second set of lines, with alignment assisted by the sidewall spacers. Then, this second let of lines is cut, using a fourth mask.

This approach consumes an excessive number of masks. Four masks are needed for four sets of lines, so that each line printed by a given mask is separated by sufficient distance (≥ minimum allowed pitch). Four additional masks are needed for the etch block/cut locations, corresponding to each of the four sets of lines. This gives a total of eight masks! Fortunately, this is not the only approach.

Double SADP

SiCarrier’s patent CN117080054 [7] discloses an SAQP-class approach that uses half the number of masks used for double SALELE. In a way, it is a kind of cascaded, double self-aligned double patterning (SADP) (Figure 2).

Figure 2. Double SADP approach. Left: First spacers (gray) are formed on sidewall of mandrel pattern (blue). Center left: Etch block/cut (black) is applied to the spacer pattern. This completes the first SADP. Center right: Second spacers (yellow) are formed on the sidewalls of the first spacer pattern, followed by a gap fill (green). Etch block/cut (red) is applied to the gap fill pattern. This completes the second SADP. Right: Wide features are formed with a separate (fourth) mask.

The first SADP leaves a set of first spacers which correspond to the first set of metal lines. The gaps left after the second follow-on SADP correspond to the second set of metal lines. Wide metal lines are completed at the end. Like in SALELE, the two sets of lines are cut separately. However, SADP enables twice the line density compared to a single litho-etch, and the cuts can also be made two lines at a time. Thus, the number of masks is halved from 8 to 4.

Diagonal FSAV Grid Becomes a Must

With metal pitches of 30 nm or less, metal linewidths become 15 nm or less. It is actually difficult to focus, even with High-NA EUV, down to a spot as small as this; the Rayleigh resolution limit would be 0.61 wavelength/NA = 0.61*13.5/0.55 = 15 nm. But looking ahead to the sub-2nm node, stochastics will become the overwhelming reason why even with High-NA EUV, directly printing a via is not feasible (Figure 3).

Figure 3. Absorbed photon density (1 nm pixel) for a 22 nm x 11 nm via on 44 nm x 22 nm pitch, with 6 mJ/cm2 absorbed EUV dose.

Lithographic difficulty has been a key driving reason for using diagonal via grids [8]. The minimum via pitch at advanced nodes cannot be as small as the minimum metal line pitch (Figure 4). Routing doesn’t require it anyway [8,9].

Figure 4. Left: The minimum via pitch cannot be as small as the minimum metal line pitch. Right: Diagonal via locations could be allowed.

It will become necessary to fill the intersection area between vertically adjacent metal layers, using the fully self-aligned via process [10]. A focused EUV spot will be wider than the metal linewidth at 3nm and below.

Based on the pitches in Table 1, we can predict the maximum number of masks used for patterning the V0, V1, and V2 layers. With ArF immersion, we allow 80 nm distance between vias [11]. Brute force via multipatterning will result in up to four masks used (Figure 5). A more efficient approach that fits the diagonal via grid is to use LELE double patterning to print portions of diagonal lines that cover the targeted via locations; a third mask would be used if needed to trim the portions if necessary.

Figure 5. Via multipatterning options. Each color represents a different mask. Top left: double patterning is sufficient for N+2, and some via layers of N+3. Top right: triple patterning would become necessary for N+4 and N+5. Bottom left: for N+6, quadruple patterning would become a necessary allowance if still using brute force multipatterning. Bottom right: Diagonal LELE (plus trim mask if necessary) is most efficient for accommodating the diagonal via grid.

Counting Cuts

Besides vias, metal line cuts add significantly to the mask count. For the M0 and M2 layers, the double SADP approach only requires two cut masks, while the double SALELE approach depends on the node pitches. The distances between cuts follow the same rules as for the vias. It could go up to four masks for the 1.x nm node (Figure 6).

Figure 6. Cut mask count for double SALELE metal layers. Each color represents a different mask.

The M1 and M3 layers are likely patterned by SALELE, so that narrow straight line cuts may be used to cut alternate lines, skipping lines in between. This would mean up to four masks (Figure 7).

Figure 7. Cut mask count for the SALELE metal layers (M1 and M3). Each color represents a different mask.

For EUV, SALELE cuts would still require two masks. Thus, DUV quadruple patterning for this purpose is still cheaper than EUV double patterning [12].

Smooth Ride Forward?

When the mask count increases for the M0 through M3 layers are tallied up for the different possible approaches, we get the overall result in Figure 8.

Figure 8. Number of masks required for the M0 through M3 layers for the representative nodes N+2 through N+6, for the different possible multipatterning combinations. “2xSALELE” = double SALELE, “2xSADP” = double SADP, “DFSAV” = diagonal line LELE on FSAV, with trim mask. SALELE is assumed applied to the M1 and M3 layers.

The double SALELE approaches will consistently require more masks than the double SADP approaches. The use of diagonal line double patterning with trim mask on FSAV saves three masks for N+6 (44 nm pitch M1, 22 nm pitch M0 and M2). In the best case, only 7 masks have been incrementally added from N+2 to N+4, and the total remained unchanged until N+6. This is to be compared with the worst case, where the mask count increase from N+2 continued after N+5, leading up to 18 masks for N+6.

N+5 is seen to be a convenient shrink of N+4, with no added masks.

Thus, the multipatterning path must be carefully planned several nodes ahead in advance in order to ensure that mask count increase can be manageable.

References

[1] R. Krishnamurthy, “SMIC Steps Toward 5nm: Kirin 9030 Analysis Shows the Foundry’s N+3 Progress,” TechInsights.

[2] Skyjuice, “The Truth of TSMC 5nm,” Angstronomics.

[3] D. Schor, “Samsung 5 nm and 4 nm Update,” Wikichip Fuse.

[4] Y. Li, Q. Wu, Y. Zhao, “A Simulation Study for Typical Design Rule Patterns and Stochastic Printing Failures in a 5 nm Logic Process with EUV Lithography,” CSTIC 2020.

[5] Y-P. Tsai, C-M. Chang, Y-H. Chang, A. Oak, D. Trivkovic, R-H. Kim, “Study of EUV stochastic defect on wafer yield,” Proc. SPIE 12954, 1295404 (2024).

[6] Y. Drissi, W. Gillijns, J. U. Lee, R. R-H. Kim, A. Hamed-Fatehy, R. Kotb, R. N. Sejpal, F. Germain, J. Word, “SALELE Process from Theory to Fabrication,” Proc. SPIE 10962, 109620V (2019).

[7] F. Chen, “SiCarrier’s SAQP-Class Patterning Technique: a Potential Domestic Solution for China’s 5nm and Beyond,” Multiple Patterns.

[8] S-W. Peng, C-M. Hsiao, C-H. Chang, J-T. Tzeng, US Patent Application 20230387002; Y-C. Xiao, W. M. Chan, K-H. Hsieh, US Patent 9530727.

[9] F. Chen, “Exploring Grid-Assisted Multipatterning Scenarios for 10A-14A Nodes,” Multiple Patterns.

[10] J-H. Franke, M. Gallagher, G. Murdoch, S. Halder, A. Juncker, W. Clark, “EPE analysis of sub-N10 BEoL flow with and without fully self-aligned via using Coventor SEMulator3D,” Proc. SPIE 10145, 1014529 (2017).

[11] M. Burkhardt, Y. Xu, H. Tsai, A. Tritchkov, J. Mellmann, “Ultimate 2D Resolution Printing with Negative Tone Development,” Proc. SPIE 9780. 97800E (2016).

Podcast EP324: How Dassault Systèmes is Creating the Next Generation of Semiconductor Design and Manufacturing with John Maculley

Podcast EP324: How Dassault Systèmes is Creating the Next Generation of Semiconductor Design and Manufacturing with John Maculley
by Daniel Nenni on 12-26-2025 at 10:00 am

Daniel is joined by John Maculley, Global High-Tech Industry Strategy Consultant at Dassault Systèmes. John has over 20 years of experience advancing innovation across the semiconductor and electronics sectors. Based in Silicon Valley, he works with leading foundries, OSATs, design houses, and research institutes worldwide to accelerate technology co-optimization and strengthen ecosystem resilience.

In this informative and forward-looking discussion, Dan explores the evolving focus on what kind of IP is curated and leveraged in the semiconductor industry with John, who describes knowledge and know-how as the new strategic differentiating IP for many companies. He explains why the ability to codify and curate this information across the enterprise is becoming quite valuable. John describes how IP management is now shifting to governance and intelligence, and with AI-augmented IP engineers can now design with a focus on manufacturability.

John discusses many other benefits of the work Dassault Systèmes is doing to facilitate an AI-augmented future for the semiconductor industry. Methods to capture institutional knowledge and make it available to all members of the team are discussed. The impact to design productivity for advanced 3DIC systems is significant.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Why TSMC is Known as the Trusted Foundry

Why TSMC is Known as the Trusted Foundry
by Daniel Nenni on 12-26-2025 at 6:00 am
Categories: Foundries, TSMC

TSMC Ivey Fab

Taiwan Semiconductor Manufacturing Company (TSMC) is widely regarded as the world’s most trusted semiconductor foundry, a reputation built over decades through technological leadership, business model discipline, operational excellence, and reliability. In an industry where trust is as critical as transistor density, TSMC has become the backbone of the global digital economy.

First and foremost, TSMC’s pure-play foundry model is the foundation of its trustworthiness. Unlike integrated device manufacturers (IDMs) such as Intel and Samsung, which design and manufacture their own chips, TSMC does not compete with its customers. It manufactures chips exclusively for third parties and has maintained a strict firewall between customer designs. This neutrality reassures customers, from Apple and NVIDIA to AMD, Qualcomm, and countless startups, that their intellectual property will not be used against them. Over time, this consistency has created deep confidence across a vast ecosystem, making TSMC the default manufacturing partner for the world’s most valuable chip designers.

Second, TSMC’s technological leadership reinforces that trust. The company has consistently been first, or decisively best, to mass-produce advanced process nodes such as 7nm, 5nm, and 3nm at high yields. In semiconductor manufacturing, reliability is not just about innovation, but about delivering that innovation at scale, on schedule, and with predictable silicon. TSMC’s ability to translate cutting-edge research into stable, high-volume production has made it indispensable for customers whose product cycles depend on certainty. When companies commit billions of dollars to a chip design, they need confidence that the foundry can deliver exactly as promised and TSMC has repeatedly proven it can.

Third, manufacturing excellence and yield consistency distinguish TSMC from competitors. Advanced chips are extraordinarily complex, and small variations can destroy profitability or product viability. TSMC’s laser focus on process control, defect reduction, and continuous improvement results in industry-leading yields. High yields mean lower costs for customers, faster ramp-ups, and fewer surprises after tape-out. This operational discipline is a major reason customers trust TSMC with their most advanced and sensitive designs.

Fourth, TSMC has built a reputation for strong intellectual property protection and confidentiality. Semiconductor designs represent years of research and billions in investment. TSMC has demonstrated, across thousands of customers, that it can securely handle highly confidential data without leaks or misuse. This trust is reinforced by TSMC’s internal culture, strict access controls, and long-standing customer relationships. In an era of increasing cyber and industrial espionage, this reliability is invaluable.

Fifth, TSMC’s scale and ecosystem integration create trust through inevitability. The company has invested hundreds of billions of dollars in fabrication plants, equipment, and talent, creating manufacturing capabilities that few others can match. Its close collaboration with equipment suppliers (such as ASML and Applied Materials), EDA vendors (Synopsys, Cadence, Siemens EDA), and IP companies (Synopsys, Arm, Analog Bits) also known as the Grand Alliance allows customers to design within a mature, silicon-proven and well-supported ecosystem. This reduces risk and shortens time-to-market, further cementing TSMC as the safest choice.

Sixth, TSMC’s long-term strategic thinking strengthens customer confidence. The company invests aggressively ahead of demand, often years before returns are guaranteed. This willingness to absorb risk ensures that capacity is available when customers need it, even during industry upcycles or shortages. During recent global chip shortages, TSMC’s capacity planning and prioritization reinforced its image as a stable, responsible industry steward.

Finally, TSMC’s global credibility and governance matter. While geopolitical risks exist, TSMC has demonstrated transparency, regulatory compliance, and cooperation with governments and customers worldwide. Its expansion into the United States, Japan, and Europe reflects a commitment to supply chain resilience and global trust.

Bottom line: TSMC is the trusted foundry not because of a single advantage, but because of a rare combination: neutrality, technological supremacy, manufacturing reliability, IP protection, scale, and long-term vision. In an industry where failure is catastrophic and trust is earned slowly, TSMC has become the gold standard and the cornerstone of modern semiconductor manufacturing.

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Journey Back to 1981: David Patterson Recounts the Birth of RISC and Its Legacy in RISC-V

Journey Back to 1981: David Patterson Recounts the Birth of RISC and Its Legacy in RISC-V
by Daniel Nenni on 12-25-2025 at 10:00 am
Categories: Events, IP, RISC-V

RISC V Summit 2025 David Patterson

In a warmly received keynote at the RISC-V Summit, computer architecture legend David Patterson took the audience on a captivating trip back to 1981, using scanned versions of his original overhead transparencies to recount the birth of Reduced Instruction Set Computing (RISC) at UC Berkeley.

Patterson began with humor, noting his wife’s love for time-travel movies and explaining how age allows easy travel backward. Digging through old files, he rediscovered those classic plastic slides, artifacts unfamiliar to much of the younger audience, and used them to recreate the talk he gave across campuses over four decades ago.

The computing landscape of February 1981 was starkly different: mainframes and minicomputers dominated serious work, with IBM as the undisputed leader. DEC’s VAX, a refrigerator-sized 32-bit minicomputer running at 5 MHz with a 2 KB cache, represented the pinnacle. The IBM PC had not yet launched, and Intel’s 8086 was the cutting-edge 16-bit microprocessor. Cultural markers included Ronald Reagan’s presidency, disco music, and the release of Raiders of the Lost Ark.

Against this backdrop, Complex Instruction Set Computers (CISC) reigned supreme. The prevailing philosophy held that richer, more varied instructions would close the “semantic gap” between high-level languages and hardware. Microprogramming, enabled by growing memory densities under Moore’s Law, made complex instructions seemingly inexpensive. Marketing reinforced the idea that sophistication meant smaller programs and greater reliability, while registers were dismissed as old-fashioned.

Reality proved otherwise. High-level language programming used only a small subset of instructions. Complex operations, such as the VAX’s array-indexing instruction or IBM 370’s multi-register moves, were often slower than sequences of simpler ones. Design cycles lengthened dramatically, and microcode bugs were rampant; Patterson’s 1979–1980 sabbatical at DEC exposed constant patching of VAX microcode.

These observations crystallized into RISC principles: favor simplicity unless a compelling reason exists; prioritize fast clock cycles, easy decoding, and pipelining over instruction count or program size; recognize that microcode offers no magic; and rely on advancing compiler technology.

To illustrate, Patterson, a car enthusiast, likened CISC to an over-ornamented 1950s Cadillac and RISC to a sleek, agile sports car.

The ideas gained traction with Patterson and student David Ditzel’s 1980 paper, “The Case for the Reduced Instruction Set Computer,” published alongside a rebuttal from VAX architects—sparking immediate controversy and lively RISC vs. CISC debates at conferences.

Berkeley proved the concept through graduate courses. Leveraging DARPA-funded CAD tools, a simplified instruction set, and sheer beginner’s luck, roughly a dozen students designed, laid out, fabricated, and tested RISC-I in under two years. Remarkably, the RISC-I instruction set closely resembles today’s RISC-V core—Patterson called RISC-V’s version slightly more elegant.

Porting Berkeley UNIX was straightforward, and early benchmarks showed the student-built RISC-I roughly twice as fast as the professional, multi-year VAX effort—a stunning validation.

Patterson closed by honoring the original team, including faculty Carlo Séquin and John Ousterhout, and graduate students. He shared photos from a 2015 ceremony installing a plaque for the first RISC microprocessor, where RISC-I pioneers met RISC-V leaders, creating a touching cross-generational moment.

Bottom line: Forty-five years later, the simplicity and elegance born in those Berkeley classrooms power billions of devices worldwide and live on vibrantly in the open RISC-V ecosystem.

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The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

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Assertion-First Hardware Design and Formal Verification Services

Assertion-First Hardware Design and Formal Verification Services
by Kalar Rajendiran on 12-25-2025 at 6:00 am
Categories: AI, EDA, LUBIS EDA

LUBIS EDA Modelling

Generative AI has transformed software development, enabling entire applications to be built in minutes. But despite similar progress in AI-generated RTL, hardware verification remains a major bottleneck. RTL can be produced quickly, yet proving its correctness is extraordinarily difficult. This has revived a long-standing but historically unattainable idea, namely, a complete set of formal properties. Hardware design in RTL should begin with Assertion IP that precisely define the intended behavior of the design, rather than generated after the fact. For decades, this approach was out of reach. Today, the landscape has shifted, making assertion-first hardware design increasingly viable.

Tobias Ludwig, CEO of LUBIS EDA addressed this very topic at the Verification Futures Conference recently held in Austin, Texas. His talk covered how the company is moving the industry toward this long-awaited direction.

AI Can Generate RTL But Verification Is Still the Bottleneck

AI-generated RTL may look plausible, but correctness in hardware is a hard requirement. Chips must work under every possible condition, and AI systems trained on similar datasets often share similar failure patterns. Using AI to verify AI does not eliminate risk but rather compounds it. Verification continues to dominate engineering cost and schedule because ensuring correctness requires precise, formalized intent. Assertion IP provides that precision, but historically it has been too difficult to produce at scale.

Assertion IP: What Hardware Design Should Have Started With

Assertion IP captures design intent in its most accurate form. It describes how the design must behave across states, cycles, inputs, and transitions. In an ideal process, assertions would come first, serving as the specification against which RTL is implemented and proven. This would eliminate ambiguity and allow mathematical verification throughout development.

Why Hardware Has Not Started From Assertions

Creating a complete assertion set manually was impractical. Writing hundreds or thousands of assertions by hand was slow and error-prone. High-level modeling languages were inconsistent, lacked structure and were difficult to analyze. Property generation tools did not exist. And Formal Verification engines lacked the computational strength to handle the depth and complexity of real IP blocks.

While waiting for tools capable of generating Assertion IP automatically, the industry’s culture centered on “RTL-first,” with assertions treated as an afterthought rather than the foundation.

What Has Changed Now

The situation has changed dramatically. High-level model analysis engines can now extract states, transitions, invariants, and dataflow from C++/SystemC models. Automated property generation tools can transform these models into complete assertion suites that capture timing behavior, and correctness requirements. Formal verification engines have grown powerful enough to handle deep pipelines, cryptographic algorithms, and large state spaces. AI assistance now makes creating structured models easier, allowing engineers to translate natural-language intent into analyzable code. Together, these breakthroughs make assertion-first design far more practical than ever before.

Where LUBIS EDA Fits In: Opening the Window to Assertion-First Design

LUBIS EDA is turning this renewed possibility into a practical methodology. Its technology automatically generates comprehensive Assertion IP from high-level executable models, bridging the gap between abstract model and RTL implementation. Through refinement techniques that align abstract models with cycle-accurate RTL, LUBIS ensures that properties reflect bit-level reality.

Alongside the company’s formal verification services, LUBIS EDA provides training that help teams adopt assertion-driven workflows and achieve formal sign-off on complex blocks. As AI accelerates RTL generation, LUBIS EDA’s model-first, property-driven approach becomes essential for ensuring correctness and preventing hidden bugs.

Summary

For the first time, hardware teams can move toward a design process where intent is explicit, properties are complete and RTL correctness is provable from the start. This paradigm is now within reach thanks to advances in modeling, property generation, formal tools, and AI support. LUBIS EDA is helping the industry make this transition, prying open the door to a future where hardware design can begin with formal assertion IP.

To learn more, visit www.lubis-eda.com

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Automating Formal Verification

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TSMC’s Customized Technical Documentation Platform Enhances Customer Experience

TSMC’s Customized Technical Documentation Platform Enhances Customer Experience
by Daniel Nenni on 12-24-2025 at 10:00 am
Categories: Foundries, TSMC

TSMC Online 2025

Taiwan Semiconductor Manufacturing Company, the world’s leading dedicated semiconductor foundry, has long prioritized customer-centric innovation to maintain its competitive edge in a rapidly evolving industry. TSMC is known as “The Trusted Foundry” for this reason.

Amid increasing complexity in chip design and manufacturing, driven by advanced nodes like 3nm and beyond, TSMC recognized the need for more efficient digital tools to support its global clientele. In response, the company upgraded its flagship customer self-service portal, TSMC-Online™, transforming it into a sophisticated Customized Technical Documentation Platform that significantly enhances user experience and operational efficiency.

Launched with upgrades beginning in April 2021, this platform embodies TSMC’s philosophy of being “Everyone’s Foundry.” The core objective was to address challenges posed by escalating technology and design intricacies, where customers from fabless designers to major tech giants require seamless access to vast amounts of technical data. Previously, navigating extensive documentation and production updates often demanded significant time and occasional support from TSMC’s customer service teams. The revamped TSMC-Online™ introduces a customer-oriented architecture, creating a truly customized service environment that empowers users to manage information as if operating their own fabrication facility.

Key enhancements revolve around three innovative methods:

A standard operation interface, personalized workspace, and intelligent guidance service. The standard operation interface provides a unified, intuitive layout that simplifies navigation across diverse functions, reducing learning curves and minimizing errors. Users benefit from consistent workflows, whether querying process design kits (PDKs), foundation IPs, or real-time wafer status updates.

The personalized workspace stands out as a hallmark of customization. Customers can tailor their dashboards with widgets aligned to specific roles and project stages—such as design verification, tape-out preparation, or manufacturing monitoring. For instance, engineers focused on advanced packaging like 3DFabric™ can prioritize relevant tools, while those in automotive applications highlight AEC-Q100 qualified resources. This flexibility accommodates varied stakeholder needs within a single organization, streamlining collaboration and boosting productivity.

Complementing these is the intelligent guidance service, which leverages smart features like contextual tutorials, animated walkthroughs, and real-time assistance modules. Previously, over half of users reportedly sought external help for document-related tasks due to platform complexity. Now, embedded animations and AI-driven prompts enable self-guided exploration, allowing instant access to tutorials without waiting for support, crucial across time zones.

Security remains paramount, with robust confidential information protection mechanisms ensuring sensitive data, including proprietary designs and production metrics, stays secure. Customers gain comprehensive visibility into the entire lifecycle, from design enablement through wafer manufacturing to shipment, fostering trust and operational transparency.

The impact has been profound. By January 2023, TSMC-Online™ averaged over 3,000 daily logins, reflecting high adoption and reliance. This digital collaboration tool accelerates product success by shortening time-to-market, reducing dependency on manual interventions, and enabling innovative outcomes in high-growth sectors like mobile, high-performance computing, AI, automotive electronics, and IoT.

TSMC’s commitment extends beyond this platform; it integrates with broader initiatives like the Open Innovation Platform® (OIP), which includes ecosystems for EDA tools, IPs, and cloud-based design environments. However, the Customized Technical Documentation Platform within TSMC-Online™ directly tackles day-to-day pain points, exemplifying how digital transformation can elevate service quality in semiconductor manufacturing.

Bottom Line: In an era where speed and precision define success, TSMC’s platform not only optimizes customer experience but also strengthens partnerships. By continuing to refine these tools, TSMC reinforces its role as a trusted enabler of global technological advancement, ensuring customers can focus on innovation while the foundry handles the complexities.

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The 10 Practical Steps to Model and Design a Complex SoC: Insights from Aion Silicon

The 10 Practical Steps to Model and Design a Complex SoC: Insights from Aion Silicon
by Daniel Nenni on 12-24-2025 at 6:00 am
Categories: Aion Silicon, Semiconductor Services

10 Practical SoC Steps AION Silicon

In the fast-evolving world of semiconductor design, creating a complex System-on-Chip (SoC) requires meticulous planning to ensure performance, power efficiency, and cost-effectiveness. Aion Silicon’s white paper, authored by Piyush Singh, outlines a streamlined methodology that leverages advanced modeling to bridge the gap from abstract concepts to silicon-ready specifications. Drawing on proprietary tools built atop EDA solutions from Arm and Synopsys, the paper emphasizes early architectural validation to mitigate risks and accelerate time-to-market. This approach is particularly vital for domains like AI, automotive, and high-performance computing, where SoCs integrate diverse components such as CPUs, GPUs, DSPs, and custom IP.

The white paper begins with an overview of SoC modeling’s role in preempting design flaws. Before placing any transistors, accurate models assess key metrics like bandwidth, latency, and Network-on-Chip (NoC) configuration. Aion Silicon’s custom modeling flow enhances vendor tools with extensive tweakable settings, enabling rapid iterations. Unlike traditional spreadsheet-based methods that take months, this flow delivers insights in days, allowing quick evaluation of variants to match customer use cases.

A core section explains how an ASIC evolves from an abstract view, depicted as application tasks on initiators (hardware blocks generating traffic) and targets (memory receivers), to a detailed specification. Central to this is the interconnect fabric, which connects compute and memory elements. Its design remains fluid until floor planning, influenced by timing constraints and die layout. Modeling provides a starting point, refining the NoC iteratively.

The paper highlights modeling’s advantages: estimating architecture, playing “what-if” scenarios, and enabling early software development. It categorizes modeling types, from dataflow (MATLAB / Python / C++ algorithms without timing) to loosely timed (for software prototyping) and approximately timed/fast timed models (ideal for exploration with transaction-level tracing). Cycle-accurate RTL simulations, while precise, are too slow for initial analysis.

Performance exploration is deemed essential because IP blocks, validated in isolation, face real-world constraints when integrated. Other blocks’ traffic patterns impact interconnect and memory, necessitating simulations to size subsystems appropriately.

The heart of the white paper is the “10 Steps to Architecture Success,” a phased approach breaking down complexity. The first four steps are analytical, often spreadsheet-based:

  1. System OI Analysis: Examine input/output dataflows, including burstiness, latency, timing, and formatting to determine buffer needs.
  2. Processing Analysis: Decompose algorithms into sub-tasks, grouping functionalities (e.g., MPEG decode and image analysis).
  3. IP Analysis: Identify third-party IP blocks, incorporating datasheet details on memory and compute requirements for accurate modeling.
  4. Data Interchange Analysis: Decide data exchange methods—on-chip SRAM/FIFO for small data or external DDR for large—based on size and access frequency.
The remaining steps shift to simulation:
  1. Workflow Model (Transactional): Create software representations of algorithm stages as simulation objects (e.g., green boxes in diagrams) with latency/processing settings, connected by channels for sequencing.
  2. Simulate to Verify Processing: Run simulations to visually confirm algorithm sequencing using modeling tools’ visualization features.
  3. Quantify Data Interchange: Model hardware with Virtual Processor Units (VPUs) and local memory, defining communication domains and verifying configurations.
  4. Data Physical Exchange: Remodel memory as external via a common controller, enhancing connectivity accuracy.
  5. Implement Interconnect: Add NoC fabric, replacing direct connections, and evaluate timing/performance impacts, iterating as needed.
  6. Optimize Performance: Adjust settings to identify bottlenecks, reduce latency, and improve throughput through quick simulations (minutes to hours).

These steps progressively refine models, eliminating dead ends and focusing resources logically. The paper concludes with Aion Silicon’s profile: founded in 2002, it offers end-to-end ASIC/SoC services across global centers, emphasizing first-time-right silicon.

Bottom line: This methodology underscores modeling’s transformative power in SoC design, reducing project risks and fostering innovation. By integrating custom flows with established EDA tools, Aion Silicon empowers designers to deliver optimized chips efficiently, proving that a structured path from abstraction to reality is key to semiconductor success.

See more AION Silicon Whitepapers here.

Also Read:

Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon

Architecting Your Next SoC: Join the Live Discussion on Tradeoffs, IP, and Ecosystem Realities

The Sondrel transformation to Aion SIlicon!

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PDF Solutions’ AI-Driven Collaboration & Smarter Decisions

PDF Solutions’ AI-Driven Collaboration & Smarter Decisions
by Kalar Rajendiran on 12-23-2025 at 10:00 am
Categories: AI, EDA, Foundries, PDF Solutions

11 Commandments of AI Application Adoption

When most people hear the term PDF, they immediately think of a PDF file, a universal, platform-independent way to share electronic documents.

There is, however, another PDF that many outside the semiconductor industry may not be familiar with. And this PDF actually predates the PDF file format. It is short for PDF Solutions, a company whose software platforms are widely used across the semiconductor ecosystem, from design through manufacturing and test.

While the company does not formally expand the initials “PDF,” they can be logically interpreted as Process, Design, and Fabrication, reflecting its long-standing mission to connect design intent with manufacturing reality using silicon data. As Qualcomm’s Mike Campbell has described them, the software tools offered by PDF Solutions have become “the industry’s tools,” underscoring how deeply embedded they are across leading semiconductor companies.

PDF Solutions held its annual User Conference earlier in December, and the following article provides a synthesis of the key themes, technologies, and customer perspectives presented at the event.

The industry’s new reality

Explosive demand for AI, data center, and edge workloads is driving aggressive investment in advanced nodes, chiplets, and 3D integration, pushing semiconductor revenues toward the low-trillion-dollar range before 2030. At the same time, the move to sub-2 nm processes, multi-die systems, and globally distributed manufacturing has shifted the industry’s core challenge from linear scaling to systemic complexity.

Yield, cost, and cycle time are no longer determined within a single fab or toolset. They depend on tightly coupled decisions across design, front-end manufacturing, advanced packaging, final test, and a supply chain that spans continents. More fabs are coming online, more test insertions are required per device, and more data is being generated at every step. Yet only a small fraction of that data is actively analyzed using conventional approaches.

Traditional economies of scale are increasingly difficult to realize in this environment. Operations are fragmented across sites and companies, experienced talent is constrained, and data lives in incompatible schemas and tools that make holistic analysis slow and expert-dependent.

Why AI-driven collaboration is becoming essential

Across the industry, AI is now applied to yield optimization, predictive maintenance, planning, and logistics. However, as discussed at the User Conference, its impact remains limited when data is locked in silos or when AI initiatives stall at the proof-of-concept stage rather than becoming operational systems.

In semiconductor manufacturing, a disproportionate amount of data-science effort is still consumed by data preparation rather than modeling or decision-making. Many AI projects fail not because algorithms are inadequate, but because they lack robust data foundations, governance, and deployment pathways.

Source: Adapted from Michael Campbell’s presentation at the 2025 PDF Solutions Users Conference.

From John Kibarian’s perspective, the next major wave of value, potentially in the hundreds of billions of dollars annually at an industry level, will come from AI-driven collaboration across the semiconductor ecosystem, not isolated point optimizations. Realizing that value requires secure, standards-based connectivity, AI-ready data platforms, and workflows that link design, manufacturing, test, and supply-chain decisions into a continuous, data-backed loop.

PDF Solutions’ AI strategy

The strategy rests on three reinforcing pillars: enterprise-grade ModelOps, deep data integration with semiconductor-specific semantics, and a secure, LLM-based agentic workflow platform designed for high-stakes manufacturing environments. The goal is to deliver not only actionable insights, but prescriptive guidance while de-risking AI adoption at production scale.

Source: PDF Solutions 2025

Enterprise ModelOps: closing the last mile

At the core is Exensio AI / Studio AI, an enterprise ModelOps layer designed to train, deploy, and manage thousands of models using the massive legacy datasets already resident in Exensio. The focus is on closing the “last mile” between analytics and sustained production deployment.

Roadmap capabilities discussed include reusable analytics workflows, bring-your-own-model support, a secure enterprise model registry, and full traceability between training data, models, and outcomes. This approach addresses long-standing challenges around governance, reproducibility, and operational trust.

Data integration and semantic understanding

A second pillar is breaking down silos between yield, design, and equipment data to accelerate root-cause analysis. Conference discussions highlighted persistent gaps, including limited integration with design-diagnosis ecosystems, incomplete equipment telemetry, and AI tools that force engineers to context-switch.

To address this, PDF Solutions is integrating with partners such as Siemens Tessent YieldInsight, combining design-for-test diagnosis data and layout context with Exensio’s manufacturing and test datasets. On top of this, the company is building a semiconductor semantic knowledge graph layer spanning lots, wafers, dies, packages, test structures, and yield metrics.

This pragmatic, evolving semantic layer allows analytics and language models to interpret data in context, selectively incorporating design information where it materially improves diagnosis and decision-making.

Agentic LLM infrastructure with governance by design

The third pillar is an LLM-driven, agentic workflow platform designed for secure, high-stakes environments. PDF Solutions is implementing on-premise and air-gapped LLM infrastructure so sensitive IP and yield data remain behind the customer’s firewall.

Built on the Model Context Protocol, Exensio is evolving into an engineer-directed agentic system, assisting with multi-step workflows, from ingesting raw logs to generating diagnostics and guiding engineers toward likely root causes. A synthetic validation engine stress-tests these workflows before production deployment.

Customer value in practice

A customer deep dive illustrated how this PDF Solutions’ strategy translates into value during yield ramp and failure analysis. In modern GPUs and complex SoCs, scan testing generates rich defect information, but scan diagnosis, layout review, and volume data analysis have traditionally lived in fragmented tools.

By integrating Siemens Tessent Diagnosis and YieldInsight directly into Exensio MA, PDF Solutions provides a single environment for analytics, visualization, machine learning, and layout-aware investigation.

From New Product Introduction (NPI) to High Volume Manufacturing (HVM)

This unified platform turns what was historically an NPI-focused, expert-driven flow into an HVM-ready capability that scales across products, sites, and teams. Engineers gain faster access to diagnosis results and layout context, increasing the likelihood of pinpointing failure locations and shortening the path to corrective action.

Because it is built on Exensio’s scalable data and AI infrastructure, the solution can be deployed across on-premise and cloud environments and extended with agentic capabilities as customers mature. This enables applications such as automated triage, pattern-based excursion detection, and conversational copilots to be grounded in governed data.

Summary

Across John Kibarian’s industry framing, the company’s platform roadmap, and the Siemens use-case deep dive, a consistent theme emerged. The next era of semiconductor manufacturing will be won by companies that treat data, AI, and collaboration as a unified operating system, not a collection of disconnected tools.

PDF Solutions’ mission is to provide a backbone that is semantic, agentic, and secure. With this, customers can turn the growing avalanche of manufacturing and design data into smarter, faster, and more collaborative decisions at scale.

The content of the 2025 PDF Solutions Users Conference can be found here:

https://www.pdf.com/company/pdf-solutions-users-conference/

In January, look out for a post featuring excerpts from a PDF Solutions Conference dinner chat between John Kibarian, CEO of PDF Solutions, and Tom Caufield, Executive Chairman of GlobalFoundries.

Also Read:

PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day

PDF Solutions Calls for a Revolution in Semiconductor Collaboration at SEMICON West

PDF Solutions Adds Security and Scalability to Manufacturing and Test

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Bringing Low-Frequency Noise into Focus

Bringing Low-Frequency Noise into Focus
by Admin on 12-23-2025 at 6:00 am
Categories: EDA, Primarius

1. Primarius offers a one stop RTN solution

Key takeaways

  • The challenge of acquiring high-quality, reproducible noise data becomes achievable with Primarius’ wafer-level low-frequency noise characterization solution, which is essential for advanced nodes.
  • The Primarius 981X family raises the bar for low-frequency noise measurement metrology with its unique advantages demonstrated below, along with recent innovative solutions such as the 9812HF and 9812AC.
  • Process engineers should use low-frequency noise as a key figure of merit for process quality monitoring and improvement during technology development. Design teams also require accurate low-frequency noise models to characterize devices and enable effective design optimization.

Noise, defined as any unwanted signal superimposed on an ideal one. Low-frequency noise is dominated by 1/f noise and RTN, both directly linked to crystalline defects in semiconductor materials. As semiconductor devices continue shrinking, even a single trap can cause current fluctuations. Consequently, this noise effect is emerging as a latent failure mechanism that threatens system performance.

Since the 28 nm technology node, low-frequency noise models have become a standard component of PDKs. Accurate RTN modeling not only supports circuit design and process optimization but also opens new avenues for statistical 1/f noise modeling and circuit simulation. High quality noise data is therefore a key modeling requirement.

Primarius offers a one-stop RTN solution
Practical challenge VS Technical breakthrough

Accurate low-frequency noise characterization demands more than a sensitive amplifier.

You need:

  • An instrument with ultra-low background noise.
  • Wide impedance matching to cover different types of DUTs.
  • High dynamic range to capture tiny fluctuations.
  • The ability to report both time-domain RTN signatures and frequency-domain PSDs with traceable statistics.

One practical breakthrough for noise test systems is the automatic, signal-aware switching between AC and DC coupling. With Primarius’ advanced low-frequency noise filtering and amplification technologies, the 981X Series Noise Testing System achieves high speed, high precision, and stable data acquisition. This core technology elevates noise testing to a new performance tier.

981X series supports automatic AC/DC coupling

9812DX: Golden standard

The Primarius 981X series Noise Testing System has been the golden standard for low frequency noise testing in the semiconductor industry for decades. It sets new records in measurement speed, system resolution, and coverage of different types of measurement requirements for flicker noise and RTN. The 9812DX, succeeding 9812D, has been adopted by leading foundries as the new golden tool for lowrequency noise testing. 9812DX stands out for its rare ability to measure both high impedance and low impedance devices with consistent accuracy.

Notable 9812DX highlights:

  • Wide voltage and current range: 200V, 200mA
  • Broad impedance matching range: 3 Ω to 30 MΩ
  • Lots of device types: Suitable for devices such as MOSFETs, BJTs, FinFETs, LDMOS, JFETs, HBTs, Diodes, Resistors, etc.
  • Hight resolution & bandwidth: 10 e-27A^2/Hz @ 20KHz
  • Ready for all advanced process nodes: 7/5/3nm and more
9812HF: VHF reach

Launched as the high bandwidth extension of the 981X family, the 9812HF is designed to bridge traditional low-frequency noise analysis and higher frequency noise concerns. This extension matters for applications where noise mechanisms span large frequency ranges.

Notable 9812HF highlights:

  • VHF bandwidth: Brings low-frequency noise measurement into 100 MHz range so designers can observe how low frequency mechanisms interact with the front-end up conversion and wideband circuits.
  • Maintains series sensitivity: Keeps low-current sensitivity and wide impedance coverage as 9812DX while extending frequency reach—so you don’t trade sensitivity for bandwidth.
  • Application fit:
    Meeting growing demands in satellite communications, automotive electronics, and other advanced applications requiring wideband noise analysis.

 

9812AC: Noise under realistic dynamic drive

Historically, most noise research and device qualification have focused exclusively on DC bias conditions. Yet, recent studies reveal that RTN under AC bias exhibits statistical properties distinct from DC-based measurements. While DC-based analysis provides a safe and conservative reliability estimate, it may unnecessarily constrain the circuit design space for advanced CMOS technologies.

To address this industry gap, Primarius launched the commercial grade 9812AC test system in 2023. The 9812AC enables designers to measure noise under dynamic operating conditions, delivering a comprehensive understanding of device behavior. This insight is crucial for making smarter design and verification trade-offs.

Noise data from 9812AC: behaviors not observable under DC bias
M9800: Industry parallel system

To meet wafer-level production demands for higher throughput and lower cost, M9800 system becomes a preferred choice for large-scale testing. Compared with conventional solutions, the M9800 increases overall test efficiency by 2-4×, accelerating process development for advanced technology nodes.

M9800 system
9812 & FS-Pro: Integration to speed up noise measurement

FS-Pro, Primarius’ all-in-one semiconductor parameter analyzer, is another flagship product in the portfolio. Compared with traditional IV meter or SMU, FS-Pro compact size and light weight (less than 8kg) makes it easier to be assembled with 9812DX as a whole system. While maintaining measurement accuracy and resolution, FS-Pro can significantly speed up DC measurement thus enable more efficient overall measurement with 9812DX.

FS-Pro delivering high accuracy and wide dynamic range for device characterization
Summary

Low-frequency noise has evolved from a niche laboratory characterization to a critical process and system-level metric in silicon development. Great low-frequency noise metrology can shorten the feedback loop between process engineers, device physicists, and circuit designers: it turns poorly quantified risk into actionable defect localization, process optimization, and realistic design margins.

The Primarius 981X family gives teams a practical, wafer-scale toolkit to measure what matters—across time, frequency and operating conditions—so they can design and qualify chips with less guesswork and more physics-backed evidence.

Also Read:

Primarius Technologies at the 2024 Design Automation Conference

Free Webinar on SPICE Simulation

Low Frequency Noise Challenges IC Designs

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A Brief History of TSMC Through 2025

A Brief History of TSMC Through 2025
by Daniel Nenni on 12-22-2025 at 10:00 am
Categories: Foundries, TSMC

About TSMC 2025

Taiwan Semiconductor Manufacturing Company, the world’s largest dedicated semiconductor foundry, has transformed from a modest startup into a global technology powerhouse. Founded on February 21, 1987, by Morris Chang, a veteran of Texas Instruments, TSMC pioneered the “pure-play” foundry model. This innovative approach separated chip design from manufacturing, allowing fabless companies to outsource production without competing directly with integrated device manufacturers (IDMs).

Historically, IDMs dominated the industry before the 1980s rise of specialization. Companies like Intel pioneered this model, optimizing processes for proprietary designs. Major IDMs today include Intel, Samsung Electronics, Texas Instruments, Infineon, STMicroelectronics, and Renesas.

Chang, recruited by Taiwan’s government to head the Industrial Technology Research Institute (ITRI), envisioned TSMC as a neutral partner. Initial capital came from the Taiwanese government (48%), Philips (28%, with technology transfer), and private investors. Located in Hsinchu Science Park, TSMC’s early focus was on mature processes like 1-micron CMOS, serving fabless startups.

The 1990s brought rapid growth. TSMC went public on the Taiwan Stock Exchange in 1994 and listed ADRs on the NYSE in 1997, the first Taiwanese company to do so. Technological milestones included 0.5-micron in 1994, 0.35-micron copper interconnects, and overseas ventures like WaferTech in the U.S. (1996). Despite challenges like the 1997 Asian financial crisis and 1999 earthquake, revenue soared, reaching over 50% foundry market share by 2000.

Entering the 2000s, TSMC advanced to 0.13-micron (2002) and 90nm (2004), powering the PC and mobile booms. The Open Innovation Platform (OIP) launched in 2008 fostered ecosystem partnerships. Leadership saw Chang retire briefly (2005-2009) before returning amid the global financial crisis. By 2010, revenue hit $13.9 billion, with nodes like 28nm ramping.

The 2010s marked dominance in advanced nodes. Co-CEOs Mark Liu and C.C. Wei took over in 2013, with Chang as chairman until 2018. Breakthroughs included 16nm FinFET (2015), 10nm (2017), 7nm with EUV (2019), and capturing Apple’s A-series chips from Samsung. Revenue reached $45 billion by 2020, market share ~55%. Geopolitical tensions emerged, including U.S. sanctions halting Huawei shipments.

The 2020s accelerated amid COVID shortages and AI surge. 5nm (2020), 4nm (2021), and 3nm (2022) debuted, powering Apple’s M-series and Nvidia’s GPUs. In 2025, 2nm (N2) entered mass production late in the year, offering 10-15% speed gains or 25-30% power savings over 3nm, using gate-all-around transistors. A16 (1.6nm) is slated for 2026/2027 with backside power delivery.

Global expansion diversified risks. Arizona’s Fab 21 began N4 production in Q4 2024, with yields matching Taiwan. By 2025, investment swelled to $165 billion for six fabs, two packaging sites, and R&D—third fab groundbreaking in April for N2/A16. Japan’s JASM (Kumamoto) started mature nodes in 2024, expanding to advanced. Germany’s ESMC (Dresden) progresses for automotive/specialty.

Financially, TSMC is thriving on AI demand. Q3 2025 revenue grew 30% YoY, with 72% foundry share. TTM revenue ~$88 billion, market cap ~$1.5 trillion. Advanced nodes (<7nm) drive ~74% wafer revenue.

Bottom Line: TSMC’s “trusted foundry” status stems from IP protection, neutrality, and innovation. From 1987’s vision to 2025’s AI linchpin, it powers global tech while navigating geopolitics. With C.C. Wei as CEO, TSMC targets net-zero by 2050 and continued leadership in the angstrom era.

Also Read:

Cerebras AI Inference Wins Demo of the Year Award at TSMC North America Technology Symposium

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival

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