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Going Beyond DRC Clean with Calibre DE

Going Beyond DRC Clean with Calibre DE
by Mike Gianfagna on 03-24-2025 at 6:00 am
Categories: EDA, Siemens EDA

Going Beyond DRC Clean with Calibre DE

For advanced semiconductor designs, achieving both design rule check clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. Balancing electrical performance and layout integrity is a difficult task. Achieving an optimal and balanced solution demands deep technical understanding of all the nuances and impact of each set of requirements. There are often unexpected interactions at play. Achieving a result that satisfies all requirements can result in an overly pessimistic design. Pushing the envelope in the other direction can result in a non-functional design.

Siemens Digital Industries Software recently published a comprehensive technical paper on these challenges. It turns out Calibre DesignEnhancer (DE) possesses the required deep understanding of the technology requirements and interactions at play. The product delivers an analysis-based, signoff-quality layout modifying EMIR solution that enhances power integrity and reduces IR drop. This results in improved design reliability and manufacturability across multiple foundry technologies, reduced support costs and increased usability for foundries, CAD teams, and designers. The technical paper gets into substantial detail on how Calibre DE accomplishes this. There are also detailed use cases from Google and Intel. A download link is coming but first let’s explore going beyond DRC clean with Calibre DE.

About the Technical Paper

I find it interesting that Google and Intel are cited side-by-side in this piece. It wasn’t that long ago that Intel would never disclose anything about its design capability and Google would really have nothing to say about chip design. It seems that semiconductor companies are becoming system companies and system companies are becoming semiconductor companies. And so, we move forward.

Jeff Wilson

The technical paper is entitled How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability. The author is Jeff Wilson. Jeff is a product management director for DFM applications in the Calibre organization at Siemens Digital Industries Software. He is responsible for the development of products that analyze and modify the layout to improve the robustness and quality of the design. Before joining Siemens, Jeff worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.

About Calibre DE

Foundries face many challenges with each new technology, like the need for new analysis and qualified DRC/LVS decks. Calibre DE addresses this challenge by reading the relevant data from DRC rules file, then using its built-in expertise with SVRF commands to create a deck that modifies the layout to solve identified EMIR problems. These files create a design kit that includes specific DRC values from the foundry/IDM.

At the core of all this is Calibre’s deep understanding of design rules. One example use case is adding DCAP and filler cells after P&R has completed power, performance and area iterations. This can be tricky since P&R tools are not good at filling open spaces with very specific design rules. If you run PV on a medium to large design with DCAP and filler cells inserted by a P&R tool, runtime can exceed 10 hours. Calibre DE Pvr (physical verification ready) flow uses the world’s best correct-by-construction fill tool, SmartFill, to place DCAP and filler cells. The runtime for this approach will take ~1 hour, delivering much better results.

Another example is the challenge of ensuring that designs are free from electrical violations like IR drop. This is getting more important at advanced nodes. Calibre DE Pge (power grid enhancement) and Calibre DE Via (via insertion) are tools that optimize the power delivery network and reduce the impact of IR drop, improving electromigration/IR drop and overall yield. By using these tools, design teams can minimize the risks of power failure and other integrity issues that affect product performance.

The technical paper gets into lots of details about these capabilities and more. You can also access a lot of detailed information on Calibre DesignEnhancer here. Let’s now take a brief look at what Google and Intel found. This information was taken from recent conference presentations from both companies.

Google’s Experience

Google’s goal was to reduce IR drop at 3 nm. The Google team found that finding IR drop issues at the chip finishing stage was particularly challenging and that conventional solutions came with unfortunate consequences:

  • Derating means decreased speed.
  • Changing floorplan or re-designing the power distribution network (PDN) means additional design cycles.
  • Fixing the PDN becomes very complicated and ineffective due to the huge increase in DRC rules, especially if attempted manually or using conventional tools.
Google flow incorporating Calibre DesignEnhancer during the chip finishing stage

Google used Calibre DE via insertion to improve IR drop with little or no timing impact, and Calibre DE power grid enhancement to improve the power grid by creating parallel run lengths. They used the EMIR results to focus layout modifications on design areas where the power grid needed to be enhanced. They also used built-in functionality to limit edits around critical nets and establish priorities for the power signals.

There is a lot more detail on what Google found in the technical paper. You will definitely want to review this data. The figure on the right shows what Google’s flow looks like.

Intel’s Experience

Intel’s goal was to improve power grid robustness at 5nm and beyond. The Intel team had created a PDN during automated floorplanning but found corner cases that prevented some via hookups. The result was a weak power grid and inadequate power hookups that caused inaccurate electrical modeling.

The team provided several nets that needed additional via hookups for Calibre DE Via to work on to maximize the number of vias to reduce IR drop issues. The P&R team did their job based on their understanding of the design rules. They were forced to take a conservative approach to the rules. Using Calibre DE, the P&R team was able to insert an additional 9 million vias on the nets that they specified on the 5 nm process node. These additions were very targeted as shown in the figure below.

Via counts per net

By leveraging Calibre DE’s detailed understanding of via-related DRC rules—such as spacing, width and width-dependent rules—Intel was able to insert the additional vias without introducing DRC violations. This significant increase in vias had a measurable impact on IR drop, improving both electrical performance and yield. More details of Intel’s experiences are provided in the publication.

To Learn More

I have just scratched the surface of what is discussed in the new Siemens Digital Industries technical paper, How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability. If balancing electrical performance and layout integrity at advanced nodes is giving you a headache, you will definitely want to read this paper. You can download your copy here.  And you can learn more about the family of Calibre DE products here.  All this will help you understand going beyond DRC clean with Calibre DE.

Also Read:

Siemens Fleshes out More of their AI in Verification Story

Speeding Up Physical Design Verification for AMS Designs

Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing

Podcast EP278: Details of This Year’s Semiconductor Startups Contest with Silicon Catalyst’s Nick Kepler

Podcast EP278: Details of This Year’s Semiconductor Startups Contest with Silicon Catalyst’s Nick Kepler
by Daniel Nenni on 03-21-2025 at 10:00 am

Dan is joined by Nick Kepler, COO and Director at Silicon Catalyst. Nick has over 30 years of experience in the semiconductor industry, with varied leadership and technology management roles including semiconductor process technology development and manufacturing, design enablement, technical program management, and customer-facing marketing and technical sales.

Nick describes the details of Silicon Catalyst’s third Semiconductor Startups Contest with Dan. The contest is opening today and like prior events is co-sponsored by Arm. Nick explains the history and goals of the event, along with a description of prior winners. He describes the prizes of the current contest, which are substantial and include $150K – $250K of prize money along with admission to the Arm Flexible Access program which includes try before you buy access to Arm IP, tools training, support and simpler legal agreements.

Dan also explores the details of how and when to apply to the contest and when results will be announced with Nick. Details about the contest can be found here, and you can submit an application here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview with Jonas Sundqvist of AlixLabs

CEO Interview with Jonas Sundqvist of AlixLabs
by Daniel Nenni on 03-21-2025 at 6:00 am
Categories: CEO Interviews

04 AlixLabs portrait 211116

Jonas Sundqvist received his PhD in inorganic chemistry from Uppsala University, Department for Materials Chemistry at The Ångström Laboratory in 2003 where he developed ALD and CVD processes for metal oxide ALD and CVD processes using metal iodides. Jonas is in charge of the daily business at AlixLabs – as a co-founder, he’s been with the company since day one in 2019.

Tell us about your company?
AlixLabs is the world’s only pure-play Atomic Layer Etch (ALE) equipment company, pioneering a breakthrough technique called APS (ALE Pitch Splitting). Our technology enables precise, atomic-scale feature definition in semiconductor manufacturing, helping chipmakers achieve critical dimensions below 10 nm at dense line pitch. By reducing the number of process steps in advanced patterning, we offer a more cost-effective and sustainable alternative to multi-patterning and extreme ultraviolet (EUV) lithography.

What problems are you solving?
We address the growing challenges in semiconductor manufacturing as the industry continues to scale down feature sizes. Traditional multi-patterning approaches introduce complexity, cost, and yield loss. APS streamlines the patterning process, reducing lithography steps, improving throughput, and lowering costs by up to 40% per multi patterning mask layer. Additionally, our solution minimizes energy and material consumption, supporting a more sustainable semiconductor industry.

What application areas are your strongest?
Our APS technology is particularly valuable for advanced logic (leading-edge node processors and GPUs) and DRAM memory. Our focus is on high-volume leading edge 300 mm semiconductor manufacturing, where reducing cost and improving yield are critical.

What keeps your customers up at night?
Chipmakers are constantly seeking ways to improve yield, reduce costs, and extend Moore’s Law. The increasing complexity of patterning techniques, rising lithography costs, and sustainability concerns around energy and material use are major challenges. Our APS technology directly addresses these pain points by simplifying manufacturing, lowering cost per wafer, and improving process efficiency and limiting the use of fluorinated gases with high GWP and PFAS issues.

What does the competitive landscape look like and how do you differentiate?
The advanced patterning landscape is dominated by EUV lithography and multi-patterning techniques. Competitors include optical lithography equipment provider ASML and alternatives like Canon’s and EVG’s Nano Imprint Lithography and companies offering complex self-aligned multi-patterning solutions. AlixLabs differentiates itself by providing a complementary or alternative solution that significantly reduces the reliance on costly lithography steps. APS enables manufacturers to scale down features without the added process complexity and cost burden of traditional patterning methods.

What new features/technology are you working on?
We are continuously refining our APS process for even finer feature scaling and expanding our compatibility with additional wafer sizes and materials. Our R&D team is focused on optimizing APS for future semiconductor nodes and integrating it with emerging process flows to enhance manufacturability, yield, and sustainability.

How do customers normally engage with your company?
Our customers typically engage with us through early-stage evaluations and process development collaborations. We work closely with leading semiconductor manufacturers, foundries, and research institutes to qualify and integrate APS into their production workflows. Engagements range from feasibility studies and we are developing a Beta tool (RFP 3Q2025) for early pilot design verification and pilot production to be followed by full-scale implementation for high-volume manufacturing in 2027-2029.

Also Read:

CEO Interview with Dr. Thang Tran of Simplex Micro

CEO Interview with Fabrizio Del Maffeo of Axelera AI

CEO Interview with Dinesh Bettadapur of Irresistible Materials

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Cut Defects, Not Yield: Outlier Detection with ML Precision

Cut Defects, Not Yield: Outlier Detection with ML Precision
by Kalar Rajendiran on 03-20-2025 at 10:00 am
Categories: Analytics, Automotive, EDA, IP, proteanTecs

Part Average Testing

How much perfectly good silicon is being discarded in the quest for reliability? During high-volume chip manufacturing, aggressive testing with strict thresholds may ensure quality but reduces yield, discarding marginal chips that could function flawlessly. On the other hand, prioritizing yield risks allowing defective chips into the field, leading to costly return merchandise authorizations (RMAs), system failures, or Silent Data Corruption (SDC). SDC, in particular, is a stealthy threat that causes undetected faults to propagate through the system, leading to catastrophic outcomes. So how do you strike the balance between rigorous error detection while maintaining yield?

Conventional methods like Part Average Testing (PAT) or Good Die in a Bad Neighborhood (GDBN) rely on statistical analysis to improve quality but are limited in granularity. They miss subtle defects while discarding healthy chips, exacerbating the quality-yield tradeoff. Thus, chipmakers have historically faced the tricky challenge of improving quality while preserving yield. Striking this balance is essential for industries like automotive and data centers, where reliability and performance are critical.

Chipmakers can now overcome this tricky challenge using proteanTecs’ outlier detection solution. proteanTecs recently published a whitepaper that discusses the details of this solution. 

proteanTecs Solution: A Paradigm Shift in Outlier Detection

proteanTecs Outlier Detection redefines semiconductor testing by integrating telemetry-based data analytics and machine learning (ML) to detect latent defects early, even at the wafer sort stage. Embedded Agents in chips collect parametric data, which proteanTecs analyzes using advanced algorithms. These models predict normal chip behavior and identify anomalies that traditional pass/fail tests cannot detect.

proteanTecs’ solution includes edge software deployed on testers and a cloud-based analytics platform. The edge software compares predicted behavior with real-time test data, flagging outliers for further review or discard before chips progress down the production line. Additionally, the software provides resiliency to prevent production drift using both local and distribution-based drift detection mechanisms.”

IDDQ Prediction-Based Detection

This method identifies leakage current anomalies at the transistor level, targeting defects invisible to traditional tests. proteanTecs combines design-profiling and process-classification data to train predictive ML models that estimate the expected IDDQ per chip. By comparing measured and predicted values during testing, latent defects are flagged and discarded. This approach not only prevents field failures but also reduces false positives that could unnecessarily lower yield.

Timing Margin-Based Detection

This method monitors timing issues at both the transistor and path levels. proteanTecs’ Margin Agents monitor timing margins across millions of IC logical paths, identifying subtle timing issues below conventional pass/fail thresholds. ML models trained on expected timing behavior detect deviations that signal potential field failures, such as timing faults or SDCs. Unlike tightening traditional test limits, this approach detects marginal defects without compromising yield.

How proteanTecs’ Outlier Detection Stands Apart

Traditional Best-Known Methods (BKMs) rely on statistical population analysis and stricter thresholds, leading to blind yield losses and missed defects. proteanTecs surpasses these limitations by leveraging dedicated on-chip Agents and predictive analytics. Its solutions operate beyond pass/fail metrics, detecting anomalies with unmatched granularity and precision. By integrating machine learning with hardware telemetry, proteanTecs enables manufacturers to meet stringent quality standards without compromising yield, delivering a dual benefit previously considered unattainable.

Benefits of proteanTecs’ Solution

proteanTecs enhances quality assurance by isolating chips with latent defects, ensuring higher reliability and performance while minimizing the risk of defective chips reaching consumers. By distinguishing true defects from benign variances, it improves yield, enabling the recovery of chips that would otherwise be discarded. This reduces waste and boosts productivity. Early detection of latent defects also prevents costly returns (RMAs) and silent data corruption (SDC), ensuring system reliability throughout the product lifecycle. Addressing issues at the Wafer Sort stage saves time and resources, reducing downstream testing, rework and packaging costs.

proteanTecs’ cloud-based platform aggregates data from chips, wafers, and lots, enabling comprehensive analysis across test stages. With advanced visualization tools, historical data storage, and real-time insights, it supports root cause analysis and proactive decision-making. Additionally, proteanTecs’ machine learning algorithms continuously refine their models, adapting to evolving manufacturing processes and ensuring ongoing detection accuracy in dynamic environments.

Tangible Proof Points from Customers

Automotive: Over time, automotive electronic systems have become the most complex element of vehicle architecture. Software in today’s cars can contain more than 100 million lines of code. Reliable implementation of these advanced technologies must meet stringent zero-downtime requirements, while accommodating unpredictable environmental and operational conditions. One manufacturer reduced Defective Parts Per Million (DPPM) by 396 using proteanTecs’ IDDQ-based detection, saving over $250,000 in testing and packaging costs. HTOL testing validated the effectiveness, with 70% of flagged outliers failing stress tests.  Read case study here: Automotive Chipmaker Slashes DPPM With ML-Powered Outlier Detection.

Data Centers: As datacenters scale to accommodate the requirements for AI applications, the demand for reliable and high-performance semiconductors increases. Semiconductor reliability is essential to maintain the uninterrupted performance of critical systems that require continuous and real-time operation. A networking chipmaker decreased DPPM by 252, avoiding latent defects that could snowball into RMAs. This early detection saved over $1,000,000 by eliminating late-stage failures and system disruptions. Read more here in our white paper: Redefining RAS in Datacenters with Real-Time Health Monitoring White Paper

Real-Time Analytics for Reliability and Cost Efficiency

proteanTecs represents a new era in semiconductor testing, combining real-time analytics, adaptive learning, and actionable insights. Its transformative approach is imperative for industries where reliability and performance cannot be traded off. By addressing the root causes of chip failures and slashing DPPM rates, proteanTecs empowers manufacturers to exceed customer expectations while reducing operational costs.

For chipmakers navigating stringent quality and yield demands, proteanTecs’ outlier detection solution is a necessity for staying competitive in a precision-driven market.

Access the whitepaper from here: “Cut Defects, Not Yield: Outlier Detection with ML Precision”

Also Read:

2025 Outlook with Uzi Baruch of proteanTecs

Datacenter Chipmaker Achieves Power Reduction With proteanTecs AVS Pro

Podcast EP214: The Broad Impact of proteanTecs with Noam Brousard

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Variable Cell Height Track Pitch Scaling Beyond Lithography

Variable Cell Height Track Pitch Scaling Beyond Lithography
by Fred Chen on 03-20-2025 at 6:00 am
Categories: Lithography

Fred Chen Litho 1

Two approaches compared

With half-pitch approaching 10 nm, EUV patterning is heavily impacted by stochastic effects, which are aggravated from reduced image contrast from electron blur [1]. A two-mask (“LELE”: Litho-Etch-Litho-Etch) approach was proposed to pattern core features for self-aligned double patterning (SADP) to get to design rules expected for 2nm node [2], in order to handle the wide and narrow linewidths of the 6-track cell. However, this LELE patterning still suffers from sensitivity to overlay due to two masks being used. In this article, we look at two approaches which use one mask, which can be applied to any number of tracks.

Multiple Deposition-Etch

The multiple deposition-etch approach is described in the expired patent US10325777 [3]. As shown in Figure 1, it is basically a sequence of iterations of deposition followed by etch. Each iteration produces a sidewall spacer adjacent to a sidewall spacer from the previous iteration. The number of iterations depends on the largest cell height. In Figure 1 it is the 8-track cell toward the right. Six deposition-etch iterations are required.

Figure 1. Multiple deposition-etch approach. Each deposition-etch iteration adds two spacers to each originally standing wide feature.

A couple of important comments need to be made. First, it should go without saying that etching the purple material must be highly selective against the gray and cyan materials, and the etching of the gray material must be highly selective against the cyan materials. Likewise, the final etch of the cyan substrate layer should be sufficiently selective against the purple material as the etch mask.

The second point is that the etch profiles of the etched spacers are not expected to be rectangular. The top of the spacer is expected to be etched more at the outward exposed side, leading to a horn-like shape from asymmetric sidewall erosion. For a few iterations, this may not be too much of a concern, but with several or more iterations, the danger is that the last few spacers are moved from their target positions from the accumulated sidewall erosions. Thus, an alternative approach we consider next may be helpful.

Multilayer-Spacer

The multiple-layer spacer approach is described in the expired patents US6300221 [4] and US7919413 [5]. Rather than iteratively alternating deposition and etch, all the layer depositions are done at once conformally, such as with atomic layer deposition (ALD); then all the etching is done (Figure 2). The etching after spacer multilayer deposition has also been demonstrated after gate patterning [6].

Figure 2. Multilayer spacer approach. Note that the starting wide feature height needs to be sufficiently tall.

This approach avoids the horn-like appearance since there is no asymmetry from the outward facing spacer corner; each spacer top is equally surrounded on both sides. Consequently, the position of each spacer doesn’t change. On the other hand, this approach does require the starting features to be sufficiently tall so that enough alternating spacers fit in between with the conformal deposition. In the case of Figure 2, the initial features need to exceed 7 spacer layers in height. Similar to the case of the multiple deposition-etch approach above, this is linked to the largest cell height determining the required number of alternating spacer material layers.

The Ultimate Pitch Reduction Booster

If we take the spacer thickness to be 10 nm, then the minimum lithographic pitch for the structure of Figures 1 and 2 is 120 nm, for the 6-track cell on the left. The pitch for the 8-track cell on the right is 160 nm. Thus, pitch reductions of 6x and 8x respectively are shown by these approaches. The required lithographic pitch is easily achievable with an ArF immersion scanner with a numerical aperture of 1.2 or higher. Thus, both the multiple deposition-etch and multilayer spacer approaches above are extremely effective scaling boosters going beyond lithography in reducing pitch.

References

[1] F. Chen, A Realistic Electron Blur Function Shape for EUV Resist Modeling.

[2] F. Chen, Rethinking Multipatterning for 2nm Node.

[3] US10325777, filed by IBM.

[4] US6300221, assigned to Intel.

[5] US7919413, assigned to ITRI.

[6] C-J Weng, Microel. Rel. 50, 1951 (2010).

Pledge your support

Also Read:

A Realistic Electron Blur Function Shape for EUV Resist Modeling

Powering the Future: How Engineered Substrates and Material Innovation Drive the Semiconductor Revolution

Rethinking Multipatterning for 2nm Node

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2025 Outlook with James Cannings QPT Limited

2025 Outlook with James Cannings QPT Limited
by Daniel Nenni on 03-19-2025 at 10:00 am
Categories: CEO Interviews

James2

Tell us a little bit about yourself and your company.
I’m James Cannings, the Executive Chairman of QPT. QPT is a power electronics start-up with a vision to reduce global electricity consumption by 5%, saving billions and moving the needle on the Net Zero challenge. Electric motors use up to 50% of the world’s electricity and our innovations allow these motors up to be driven up to 10% more efficiently.

Most electric motors are driven by power electronics using silicon-based transistors but these have a limit to how fast they can be switched and drive the motors with a low-frequency PWM signal that causes further losses in the motor. QPT enables the development of high-frequency (1MHz) Gallium Nitride (GaN)-based motor drives with an integrated, very low loss, sine wave filter. This means a motor drive that is up to 20x smaller, reducing up to 80% of the losses and driving the electric motor with a smooth sine wave, further increasing motor efficiency, reducing noise, vibration and harshness and significantly reducing system costs.

What was the most exciting high point of 2024 for your company?

In 2024, we announced the development of the world’s first 1MHz GaN-based 7.5KW motor drive with our lead customer ABB, one of the world’s largest suppliers of industrial electric motors. Since the motor drives market has effectively plateaued in terms of the underlying efficiency of the silicon-based drives for over a decade (with some progress being made with silicon carbide in the EV market) this project generated a huge influx of interest in the business.

As a small start-up, we have been directly approached by almost all of the major global motor and drive companies, a number of the major automotive companies, as well as several tier 1 suppliers of EV drivetrains. Interest from the automotive sector increased further when we won the Innovate UK ARMD3 grant to develop a GaN-based 75KW inverter for Cenex 2025.

What was the biggest challenge your company faced in 2024?

As a deep tech hardware company solving very complex challenges (this is our 5th year of R & D) funding is an ongoing challenge, especially whilst VCs and other investors are drawn to AI-based investments which can offer faster time-to-market and potential exits. As we are initially targeting industrial markets, investors understand that these are sectors that can take a long time to deliver products to market.

How is your company’s work addressing this biggest challenge?

The work with ABB helped to reposition the company as having overcome the major R & D challenges that come with hard-switching GaN transistors at 1ns, coping with the thermal and EM challenges which are so critical to solve at high-frequency, which is the only viable route to small, efficient, sine wave motor drives. As well as demonstrating that we were into a more traditional engineering phase for the business, filing key patents (like qAttach) also allowed us to start licensing discussions with key partners. This has the double benefit of showing ABB (and other potential motor drive companies) that there is a commercial route to market for them with our IP, but also shows investors that there are faster routes to revenue for the business. qAttach, for example, has benefits for existing packaged GaN devices, beyond just the motor drives application.

What do you think the biggest growth area for 2025 will be, and why?

Once the data is released from the ABB project in Q1 2025, the question is how many other engagements and evaluations QPT can actually cope with, at the same time helping customers like ABB take the next-generation of GaN-based motor drives to market. The ABB project has created huge interest given the huge potential of GaN to significantly disrupt the motor drives market.

We already have the Innovate UK project to develop the 75KW EV demonstrator and we have a long line of companies wanting to engage. It would certainly be easy for a start-up to be stretched too thin! We are also now able to start licensing and partnership deals in order to help scale the building blocks of our IP. There is a lot of interest in this area too and we’ll need to pick our engagements wisely.

How is your company’s work addressing this growth?

For 2025 it will simply be a case of picking our strategic partners carefully and staying very focussed on our mission to avoid over committing. We expect significant funding opportunities to unlock once the ABB project is complete and the benefits can be fully quantified. A more significant series A funding round in 2025 will help us to scale to meet the demands of the interested parties.

What conferences did you attend in 2024 and how was the traffic?

In 2024 QPT attended:

  • Hello Tomorrow (Paris)
  • CS International (Brussels)
  • Power Electronics International (Brussels)
  • PCIM (Nuremburg)
  • ISES EU Power Summit (Porto)
  • The Centre for Power Electronics Conference (CPE)
  • ISES US Power Summit (North Carolina)

I would probably have to pick PCIM as a highlight where we were invited to display on the Infineon stand as one of their key partners (we use Infineon GaN transistors in our solution). We were absolutely swamped on our stand for three days solid as people wanted to learn more about our 1MHz motor drive.

Will you attend conferences in 2025? Same or more?

Yes, most of the conferences listed above we’ll look to attend in 2025. We also plan to attend the Applied Power Electronics Conference (APEC) at the Georgia World Congress Center in Atlanta in March 2025. We’ll be on the Infineon stand if anyone wants to swing by and learn more.

How do customers engage with your company?

Potential customer and partners are welcome to email me directly (james@q-p-t.com). 2025 isn’t going to be a case of ramping up with hundreds of customers. But it’s going to be a very exciting year as, after over 5 years of R & D to solve the complex problems, we finally get to show the world the benefits of unleashing GaN to its full potential. Only high-frequency GaN can enable high efficiency motor drives with best-in-class power density and integrated sine wave filters to provide huge benefits to the motor. It’s an exciting time to be part of a truly transformative moment in power electronics.

Additional questions or final comments?

I don’t think so! Thanks for reading. If you’re involved in electric motor driven systems, please do get in touch!

Also Read:

2025 Outlook with Dr Josep Montanyà of Nanusens

CEO Interview: John Chang of Jmem Technology Co., Ltd.

CEO Interview: Dr. Zeynep Bayram of 35ELEMENTS

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Compute and Communications Perspectives on Automotive Trends

Compute and Communications Perspectives on Automotive Trends
by Bernard Murphy on 03-19-2025 at 6:00 am
Categories: AI, Cadence, Chiplet, EDA

Automotive Growth Pillars min

Automotive electronics is a fast-moving space, especially around sensing and distilling intelligence from that sensing. This serves three main pillars: autonomy, electrification and advances in the car cockpit. Autonomy at multiple levels remains an important goal and continues to advance, technically and geographically. Now the automotive cockpit has become a focus for innovation, with advances in infotainment, connectivity, driver and occupancy monitoring systems, even health monitors. Lots of demand for new and advanced functionality, yet OEMs are detemined to minimize bill of materials and to emphasize software driven functionality for flexibility and growth. Which, coming back to sensing, demands higher levels of integration in multi-modal sensing, fusion, and connectivity from the edge to zonal controllers to central compute. Cadence just released a webinar on this topic, hosted by Amit Kumar (Director Product Marketing and Management, Tensilica Product Group) and William Chen (Group Director, Product Marketing for Protocol Interface IPs).

Trends and Solutions in Sensing

Modern cars now run to 40 sensors or more: cameras, radar, lidar, even thermal is on the horizon. Some sensors are narrow focus, long range for forward and rear collision avoidance at speed, some are medium range perhaps for more detailed scene analysis, side sensors are shorter range still for detection in blind spots. Since each has its strengths and weaknesses, the most reliable inferencing often depending on fusion between two or more sensing streams, say between vision and radar for complementary object detection (and velocity info) in good light or poor light conditions.

In-cabin, driver monitoring systems (DMS) check the driver’s gaze and head pose (are they looking at the road ahead or falling asleep). These sensors are typically camera-based, sometimes augmented by radar or other methods. Occupant monitoring systems (OMS) detect other occupants in the car to provide additional input for warnings (someone not wearing a seatbelt, or you left a child in the car) or corrective actions. These may also use camera sensors, though radar provides better coverage to detect objects out of visual range (small children, pets, packages in the footwell). There is even work now on monitoring driver health, through radar or seatbelt sensors. Finally, sensor-based voice and gesture control help keep a driver’s eyes on the road, though I won’t touch on these topics here.

Each of these sensor streams requires specialized conditioning before an AI stage: image signal processing for a camera, a radar pipeline for radar systems (FFTs for range/Doppler, beamforming, multiple other steps on the way to building a point cloud), a different pipeline for LIDAR, and (I’m guessing) something like a camera pipeline for IR/thermal. Then comes fusion, blending these inputs together in an ML analysis to refine detection/classification. Cadence Tensilica has been strong in this space for many years, through their Vision and ConnX families of DSPs for vision/radar pipelines. The Neo family of NPU cores handles AI processing, though some simpler neural net functions can also be hosted in the Vision/ConnX cores.

You can see above how these products map to different SAE levels from L1 to L5. Hardware products come with deep support libraries and SDK, together with an extensive software ecosystem. Naturally all of this is functional safety qualified in ASIL B or ASIL D as appropriate.

Trends and Solutions in Connectivity

I must thank the webinar hosts for helping me tie together an important trend behind electronic design for automotive. Not just the point concepts – sensing, AI, zonal controllers – but the grand plan and needs that emerge from that plan. Sensing and AI give us intelligent autonomy at various levels. At the same time, auto OEMs want to keep cars affordable. That motivates a trend to a multi-purpose SoC which can serve edge, zonal or central compute needs with (as mentioned earlier) software-defined behavior to adapt to different objectives.

Such big multi-purpose systems must stuff more functionality within a package, hence the need for chiplet integrations. Chiplet subsystems will support multiple sensor interfaces, for video/radar streams (connecting through MIPI), DSP functions for image and other signal processing, GPU functions for infotainment, an AI subsystem for recognition/classification, a CPU cluster for multithreaded compute and an interface subsystem for the wide range of protocols that must be supported, from UCIe to connect between chiplets, to Ethernet for longer range, PCIe for fast point-to-point, CAN for engine control, and so on. (When you consolidate everything, you must also consolidate communications interfaces.)

Here also Cadence has strength in their family of interface solutions from PCIe (Gen 3.1 through Gen7), MIPI CSI-2, Ethernet ( up to 224G and UCIe 2.0., together with the latest DDR, LPDDR, GDDR and HBM memory interfaces. To highlight these and to help accelerate chiplets and chiplet-based systems, they recently released a reference chiplet available to be used by chiplet and full system designers as an aid in prototyping and testing their own products. In addition to very active deployment across a wide range of Tier1s and OEMs, these guys are serious about continuing to push the boundaries on automotive connectivity.

Very instructive webinar. You can watch it HERE.

Also Read:

Compute and Communications Perspectives on Automotive Trends

Bug Hunting in Multi Core Processors. Innovation in Verification

Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures

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CEO Interview with Dr. Thang Tran of Simplex Micro

CEO Interview with Dr. Thang Tran of Simplex Micro
by Daniel Nenni on 03-18-2025 at 10:00 am
Categories: CEO Interviews, RISC-V

ThangTran SimiWiki

Dr. Thang Tran is an innovator in modern computing, drawing inspiration from pioneers like Seymour Cray, Thornton, and Tomasulo. His work leverages the simplicity of the RISC-V ISA to advance microprocessor efficiency, integrating vector processing and scoreboarding principles foundational to early supercomputing. Thang has adapted Tomasulo’s dependency checking algorithm to enable ahead-of-time instruction scheduling, improving CPU execution throughput. His contributions extend to AI and ML applications, ensuring processors are optimized for high-speed, parallel computation in today’s most demanding workloads.

Tell us about your company.
Simplex Micro was incorporated in December 2021 with a focus on developing processors for AI and ML applications. Our foundation is built on RISC-V, an open-source ISA that differs significantly from x86 and ARM. Unlike traditional architectures, RISC-V fosters innovation in microprocessor design while offering significant advantages in performance, power efficiency, and area optimization (PPA).
What problems are you solving?
The rapid expansion of AI, natural language processing (NLP), and augmented/virtual reality (AR/VR) demands more efficient computing solutions. RISC-V’s vector ISA offers key advantages over both GPUs and SIMD-based architectures such as Intel AVX and ARM Neon. A new class of design—incorporating ahead scheduling with deterministic out-of-order execution—opens up new possibilities for AI and data center applications, improving efficiency and scalability.
What application areas are your strongest?
Our configurable and programmable vector processor is well-suited for a wide range of applications, from AI edge computing to large-scale data centers. Meta’s MTIA project has already demonstrated the potential of vector processors in data centers, and our approach builds on this foundation to deliver even greater efficiency and performance.
What keeps your customers up at night?
While many companies emphasize performance, power consumption remains a primary concern for our customers. Our simplified design delivers out-of-order execution without requiring register renaming, minimizing area while maintaining high efficiency. Additionally, our deterministic approach to time-based scheduling significantly reduces power consumption. Another critical challenge is memory latency. Our vector processor architecture is designed to tolerate load latency when fetching from memory—whether it takes 10 cycles or 100 cycles, performance remains unaffected. Unlike conventional designs, our execution model is independent of load latency, ensuring consistent performance. Furthermore, we leverage RISC-V’s customization capabilities, enabling customers to integrate their own proprietary custom instructions to enhance both performance and security.
What does the competitive landscape look like, and how do you differentiate?
We have developed the first-ever processor designed with a time-based execution model. In the IP market, we currently outperform competitors by at least 2X in performance. Looking ahead, we plan to expand into the chiplet market, bringing the same disruptive impact to a broader range of applications.
What new features or technologies are you working on?
We started with an innovative vector processor design and have an ambitious roadmap ahead. Our future developments include adding multithreading, automotive optimizations, and matrix accelerators while continuously adapting to industry demands. Unlike traditional fixed-configuration processors, our designs are fully parameterized, allowing for maximum flexibility, configurability, and customization to meet diverse application requirements.
How do customers normally engage with your company?
As a stealth-mode startup, we engage selectively with early adopters, industry partners, and strategic collaborators under NDA. Customers typically connect through direct introductions, technical briefings, and proof-of-concept discussions. We focus on co-developing solutions for AI, cloud, and HPC, with plans to expand through early access programs and pilot deployments.
Also Read:

CEO Interview with Dinesh Bettadapur of Irresistible Materials

CEO Interview with Pierre-Yves Lesaicherre of Finwave CEO

CEO Interview with Matt Desch of Iridium

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Semidynamics adds NoC partner and ONNX for RISC-V AI applications

Semidynamics adds NoC partner and ONNX for RISC-V AI applications
by Don Dingee on 03-18-2025 at 6:00 am
Categories: IP, Semidynamics

Baya x Semidynamics teaming up on RISC-V AI applications

When Semidynamics added support for int4 and fp8 data types to their RISC-V processors, it clearly indicated their intent to target AI inference with hundreds or perhaps thousands of concurrent threads running in their advanced caching and pipelining scheme. Two recent announcements around Embedded World 2025 reinforce their positioning for RISC-V AI applications – a partnership with Baya Systems on NoC technology, and added support for the ONNX Runtime as part of its widening software offering for its RISC-V processors.

WeaverPro enables rapid optimization of low-latency interconnects

At the RISC-V core level, Semidynamics has spent enormous energy creating a deeper, out-of-order RISC-V pipeline and keeping it busy at all times. It’s a key part of their scalability story. But what happens when an application calls for many smaller cores to work together? An increasingly popular option for AI inference is a sea of small RISC-V cores that can provide faster detection and more intense region-of-interest processing in the same system architecture.

In these applications, interconnects between cores and from cores to memory immediately rise to the top of the list of designer concerns. The aggregate bandwidth flowing across an AI inference chip can be staggering, even with efforts to strategically distribute memory in smaller blocks to get it closer to processing units. Hand-designed interconnects easily become bottlenecks with more than a few cores participating.

Baya Systems is a relatively new player in the NoC space with its next-generation WeaveIP and is gaining rapidly thanks to its software-driven, system-level optimization technology, WeaverPro. The partnership between Semidynamics and Baya is a broader effort for scalability into HPC space, but it also provides designers with excellent tools for AI inference chip design. WeaverPro has two components: CacheStudio to analyze cache and memory hierarchy with loading, and FabricStudio to analyze and optimize NoC parameters in actual workloads. The tools provide designers working with Semidynamics RISC-V processors an efficient path to creating high-bandwidth, low-latency interconnects optimized for AI inference applications.

Moving highly portable ONNX models onto RISC-V

Laying down RISC-V hardware is one thing, but the crucial factor in AI inference design is the ability to map a software model onto hardware and optimize the configuration. As AI inference proliferates, designers frequently use open-source AI models to speed their prototyping cycles by applying proven code. ONNX originated within Microsoft as a common format for AI models and is often a lingua franca for import and export between AI frameworks.

The ONNX Runtime can be thought of as a microkernel for AI, accelerating AI models via interfaces to integrated hardware-specific libraries. Semidynamics extended its Kernel Library with ONNX Runtime support to leverage its RISC-V processors efficiently. The library includes primitives for matrix multiplication, transposition, activation functions, and more features for faster development and optimization of RISC-V AI applications.

ONNX support is part of a broader effort, the Aliado RISC-V SDK, providing enhanced software for Semidynamics RISC-V processors. Many RISC-V tools come from the robust open-source ecosystem. Semidynamics gathers those plus its hardware-specific RISC-V processor enhancements into a single environment, saving designers time.

Semidynamics resources for RISC-V AI applications

Semidynamics is carving out a powerful niche in RISC-V AI applications, addressing a whole product with hardware and software ready for designers to focus on adding value on top. The SMD ONNX Runtime and a Model Zoo for Semidynamics RISC-V processors, along with the Aliado Quantization Recommender and the Aliado SDK, are available for download at:

https://semidynamics.com/software

More information on the partnership with Baya Systems and support for the ONNX Runtime is available in the Semidynamics newsroom.

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Intel has a new Billionaire CEO!

Intel has a new Billionaire CEO!
by Daniel Nenni on 03-17-2025 at 10:00 am
Categories: Foundries, Intel Foundry
2 Comments

Lip Bu Tan was appointed chief executive officer of Intel Corpor

Great news last week as Intel fills the CEO slot for the 9th time in 56 years with industry legend Lip-Bu Tan. From what I hear, Intel employees, and the entire industry for that matter, are overjoyed. I’m sure there are one or two competing companies that are concerned but overall it is an absolute love fest.

If you look at education alone Lip-Bu is definitely worthy of the CEO title. When you look at his experience, however, I would say he is a bit over qualified.

Robert N. Noyce
Intel CEO, 1968-1975, Co-founder of Fairchild Semiconductor
Education: Ph.D in physics, Massachusetts Institute of Technology

Gordon E. Moore
Intel CEO, 1975-1987, Co-founder of Fairchild Semiconductor
Education: Ph.D in chemistry and physics, California Institute of Technology

Andrew S. Grove
Intel CEO, 1987-1998, previously worked at Fairchild Semiconductor
Education: Ph.D. in chemical engineering, University of California-Berkeley

Craig R. Barrett
Intel CEO, 1998-2005
Education: Ph.D. in materials science, Stanford University

Paul S. Otellini
Intel CEO, 2005-2013
Education: MBA, University of California-Berkeley, 1974; B.A. in economics, University of San Francisco, 1972

Brian M. Krzanich
Intel CEO 2013-2018
Education: BA in Chemistry from San Jose State University

Robert Swan
Intel CEO January 2019-2021
Education: Bachelor’s degree in Business Administration from the University of Buffalo, MBA from Binghamton University.

Pat Gelsinger
Intel CEO 2021-2024
Education: Bachelor’s degree in Electrical Engineering from Santa Clara University, Master’s degree in Electrical Engineering from Stanford University.

Lip-Bu Tan
Intel CEO 2025-Present
Education: Bachelor of Science in Physics from Nanyang University in Singapore, a Master of Science in Nuclear Engineering from the Massachusetts Institute of Technology (MIT), and an MBA from the University of San Francisco.

Founding Managing Partner of Walden Catalyst Ventures and a Founding Managing Partner of Celesta Capital. Received the Semiconductor Industry Association 2022 Robert N. Noyce Award and Global Semiconductor Alliance 2016 Dr. Morris Chang’s Exemplary Leadership Award. Walden Catalyst Ventures boasts $5B of committed capital over the last thirty years, 600 portfolio companies in 12 countries, and 120 IPOs on fifteen exchanges around the world.

Semiconductor insiders like myself first met Lip-Bu when he joined Cadence Design Systems in 2004 as a member of the Board of Directors. In fact, I knew Cadence even before they were Cadence. EDA legend Jim Solomon merged companies to create Cadence and served as CEO from 1988-1989 before appointing Joe Costello. Joe was CEO from 1989-1997 and made Cadence and EDA in general what it is today, a force of nature in the semiconductor industry. Jack Harding, Ray Bingham, and Mike Fister were CEOs before Lip-Bu took over in 2009 ($853 million in revenue) and resigned in 2021 ($2.99 billion in revenue). Cadence experienced some difficult times after Joe Costello left but Lip-Bu brought Cadence back to a leadership position in EDA, absolutely.

In case you are interested there is an EDA/IP Mergers and Acquisitions Wiki which has been viewed millions of times. EDA in itself is a result of hundreds of mergers and acquisitions.

In addition to working with Intel while at Cadence, Lip-Bu joined the Intel board in 2022 and resigned in August of 2024, Pat Gelsinger resigned on December 1st 2024, probably not a coincidence. Hopefully you understand my “overqualified” comment now?

Bottom line: Lip-Bu Tan knows Intel better and is more qualified than any of the other CEO candidates that have been mentioned in the press by a very wide margin.

The question some may have now is: Why did an overly successful person like Lip-Bu Tan risk his golden reputation and accept the CEO position at a struggling semiconductor legend like Intel?

First let’s look at his compensation:

  • Base Salary: $1 million per year.
  • Annual Cash Bonus: Eligible for up to $2 million, based on performance metrics.
  • Long-Term Equity Awards: Approximately $66 million in stock options and grants, vesting over a multi-year period.
  • Stock Purchase: Agreed to purchase $25 million worth of Intel shares within the first 30 days of his tenure.

Given that Lip-Bu is a billionaire I would argue that it is not about the money. In the short term his compensation package is less than Pat Gelsinger’s. Pat had a salary of $1.25M and cash bonuses of up to $3.4M annually. Long term, however, Lip-Bu seems to have the stock advantage if successful and I can assure you the $25M stock purchase was Lip-Bu’s idea. He did the same when he joined Cadence. This clearly tells me that this is not a short term mission for Lip-Bu Tan. There is also a clause where Lip-Bu can continue his work with Walden which is an important point. He had the same agreement with Cadence.

I think it is obvious but this is my opinion based on my 40+ years in the semiconductor industry. Lip-Bu Tan is all about establishing his legacy as one of the all-time greatest semiconductor CEO’s. I seriously doubt he would risk his hard earned reputation if he did not see a clear path of success for Intel.

And for you analysts and media who think Lip-Bu only has one year to accomplish this, or are underestimating Lip-Bu’s ability as a CEO: stop embarrassing yourself. And for those of you who are calling Lip-Bu Tan LBT please stop. It sounds like a sandwich.

Also Read:

The Intel Common Platform Foundry Alliance

What would you do if you were the CEO of Intel?

Intel Presents the Final Frontier of Transistor Architecture at IEDM