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The Smartphone Snitch in Your Pocket

The Smartphone Snitch in Your Pocket
by Roger C. Lanctot on 01-05-2023 at 6:00 am
Categories: Automotive
4 Comments

The Smartphone Snitch in Your Pocket

The story in the New York Times came with a sensational headline: “Couple in Car Survive 300-foot Fall into a Canyon.” The canyon in question was Monkey Canyon in the Angeles National Forest outside Los Angeles and the couple survived, so the story goes, thanks to their satellite-connectivity-enhanced iPhone.

This is the kind of story that can transform what consumers think they know about SOS calling. It might lead one to believe that automatic crash notification, of the sort provided by OnStar-like services, are unnecessary in a world populated with iPhones and Google Pixel phones equipped with satellite-based SOS calling capability.

You might buy that idea until you read further in the Times story and learn that the iPhone that “saved” the couple in California was found by them 10 yards away from the car with a smashed screen – though somehow still working. The device prompted the couple that it could call for help with the new satellite functionality.

This couple is clearly lucky to be alive and lucky they had an iPhone. Had they been unconscious or unable to find the phone, the outcome might have been different.

The Times story contrasts with reports from across the Internet of iPhones at amusement parks mistaking rollercoaster rides for car crashes. Of course, users could leave their iPhones behind or turn off the emergency function before getting on a roller coaster – but the iPhone misinformation is likely creating at least minor headaches for emergency call centers.

The increasing promotion of smartphone based automatic crash notification is unfortunate but expected given the steadily expanding role of smartphones in cars. Every new car today comes with a companion application that allows for locating the car, operating the car remotely, determining the car’s functional status, and monitoring driver behavior.

If you have bought a new car in the past year or two or intend to in the next year or two your car will provide you with a driving score that you may use to obtain insurance quotes. Simultaneous with this shift has been an industry-wide embrace of mobile apps by insurers.

Insurers also want to evaluate your driving – for obvious reasons – but they also want you to use your phone to report claims. In fact, leading claims management company CCC Intelligent Solutions tells us that 20% of repairable claims are reported today using photo-based estimates derived from smartphones. More than 80% of consumers prefer using mobile claims management, the company says.

Smartphone-based insurance claims management does sound attractive, particularly from the standpoint of accelerating the claims process. But surely consumers will want to retain control of this process.

New technology from companies such as Sfara and Cambridge Mobile Telematics allow for the smartphone-based detection of low-speed crashes. These are precisely the kinds of vehicular interactions that many consumers prefer not to report to their insurance companies.

As we connect our cars and our insurance companies via mobile apps, we might all take care to ensure that we understand precisely which data is being collected and shared and under what circumstances. It’s not clear to me that the default mode for these applications is “opt out,” but it should be.

Smartphones are amazing devices and it is possible for a smartphone – these days – to be a life-saving tool. But the potential for misuse or abuse of personal data is enough to give any smartphone user pause before jumping into this particular pool.

It is also a heads up that the best form of OnStar-like automatic crash notification is built into the vehicle and able to detect the airbag deployment and gather important data from vehicle sensors to be shared with SOS call centers and first responders. Smartphones simply cannot replace this function.

Also Read:

Regulators Wrestle with ‘Explainability’​

Functional Safety for Automotive IP

Don’t Lie to Me

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Formal Datapath Verification for ML Accelerators

Formal Datapath Verification for ML Accelerators
by Bernard Murphy on 01-04-2023 at 10:00 am
Categories: AI, Synopsys
1 Comment

Datapath complexity min

Formal methods for digital verification have advanced enormously over the last couple of decades, mostly in support of verification in control and data transport logic. The popular view had been that datapath logic was not amenable to such techniques. Control/transport proofs depend on property verification; if a proof is found in a limited state space it is established absolutely. For large designs the check is often “bounded” – proven correct out to some number of cycles but not beyond. Experienced product teams generally had no problem with this limitation. Most electronic products allow for some threshold – perhaps 2 weeks or a month – before a reset is needed. But for one class of functions, datapaths, we will not tolerate any errors. These require a completely different approach to formal verification, which proves to be very important for math-intensive ML accelerators.

What are datapaths and why are they hard to verify?

A datapath is the part of a compute engine that does data processing, particularly math processing. It typically supports integers, fixed point numbers and floating-point numbers, with a range of precision options. Operations span from basic arithmetic to exponents and logs, trig, hyperbolic trig and more. Our intolerance of even occasional errors in such functionality was most infamously demonstrated by the Pentium FPDIV bug, estimated to occur in only one in 9 billion operations yet considered responsible for a $475M charge for replacement and write-off and a significant black eye for Intel. (In fairness, Intel are now leaders in applying and advancing state-of-the-art formal methods for more complete proving.)

Datapath verification (DPV) far exceeds the reach of simulation, as illustrated in the figure above. Faster machines and massive parallelism barely dent these numbers. Formal methods should shine in such cases. But property checking quickly runs out of gas because bounded model checkers (like SAT) can only search out through so many cycles before an exponentially expanding design state space becomes unmanageable. Instead, formal methods for datapaths are based on equivalence checking. Here equivalence is tested not between RTL and gate-level designs, but between RTL and reference C (or C++ or SystemC) models. If the reference model is widely trusted (such as Soft-float) this comparison should provide high confidence in the quality of the implementation.

VC Formal DPV and the Synopsys ARC NPX6 NPU Processor for AI

Synopsys recently hosted a webinar on application of their formal datapath verifier built on these principles. After an intro to the tool from Neelabja Dutta, Shuaiyu Jiang of the ARC group described how he used VC Formal DPV to verify datapath logic for their ARC NP6X Neural Processing Unit (NPU) IP.

The convolution accelerator example is useful to understand how the ARC team decomposed the verification task for what I think of as an assume/verify strategy though here applied to equivalence checking. The multiply phase is one such sub-component. Here assumptions would be that inputs to the C reference and the RTL implementation must be the same. In place of an output property check the proof defines a “lemma” requiring the outputs are the same. A similar process is run over each component in the convolution accelerator, followed by a top-level check for the assembled sub-proofs.

Shuaiyu also talks about application to the ARC Generic Tensor Ops Accelerator (GTOA). Briefly, ML frameworks (TensorFlow, TF-Lite, PyTorch, JAX, etc) work with tensor objects – here 2D image x color depth x sample size for a 4D tensor. These build on large sets of operators somewhat unique to each network (>1000 for TF), impeding portability, uniformity, etc. Following the ISA philosophy, Arm developed and open-released TOSA – Tensor Operator Set Architecture with ~70 basic instructions. TOSA-compliant frameworks and inference platforms should eliminate such inconsistencies. Though Shuaiyu did not comment on this point I assume ARC GTOA is built in line with the TOSA approach. The ARC ALU for these operations is necessarily even more math intensive than the convolution example, making it an even better example for DPV proofs, suitably decomposed.

To learn more

You can register to watch the webinar HERE. Also I suggest you read the second edition of “Finding Your Way Through Formal Verification (Second Edition)”. This has been updated in several areas since Synopsys released the first edition five years ago. There is a whole chapter now dedicated to DPV. Well worth a read – I’m a co-author 😀

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How to Efficiently and Effectively Secure SoC Interfaces for Data Protection

How to Efficiently and Effectively Secure SoC Interfaces for Data Protection
by Kalar Rajendiran on 01-04-2023 at 6:00 am
Categories: IP, Synopsys

secure interfaces article fig1

Before the advent of the digitized society and computer chips, things that needed protection were mostly hard assets such as jewelry, coins, real estate, etc. Administering security was simple and depended on strong guards who provided security through physical means. Then came the safety box services offered by financial institutions such as banks. The bank vaults themselves were not easily penetrable and the assets remained safe. But the service itself was not of much value if the assets couldn’t be taken out and put back in whenever the bank customer wanted. And therein was the vulnerable aspect of the service, which was at the time and point of access. What if an unauthorized party gets hold of the safety box key and accesses the contents? The institutions offering the service instituted a two-step process. The first step was to authenticate the party who wants to access the box contents. This was accomplished by checking the person’s relevant identity credentials. The second step was to use the appropriate key to open the box itself. To prevent any bad actors within the institution itself from opening the box without the customer being present, a dual-key mechanism was deployed.

Fast forward to the digitized society, other than the house we live in and the vehicles we drive, most other assets are not physical in nature. Stocks, bonds, intellectual property ownership, fiat currencies, crypto currencies, etc. The list goes on. These assets are secured not by some physical means but rather through encryption and storage in the form of zeroes and ones in electronic form around the world. In other words, security is being provided through a combination of electronic hardware/software solutions. For every security solution that is deployed, cyber criminals are always working to identify a weakness to break-in and steal assets. The goal of digital security mechanisms deployed in electronic systems is efficiency and effectiveness. At a conceptual level, the mechanism is similar to the bank safety box access method. Authenticate the user and decrypt the data using valid keys. Given this, how to protect and secure the interfaces without compromising on fast access time for legitimate users of the assets? Low latency authentication and encryption are key.

Starts with the Design

The added complication with digital security mechanisms is that they have to deal with many different types of interfaces to the data. This is pushing the industry to look at security as an integral part of electronic design architecture, not as an afterthought. The block diagram below showcases the various types of data interfaces in an electronic system.

Securing all of these interfaces at a hardware level and implementing zero-knowledge architecture so that the data is encrypted and can’t be used maliciously is critical. To add complexity to the mix, the interface standards bodies are regularly upgrading existing protocol specifications and bringing out new interfaces standards as well. These changes need to be implemented in designs either at the controller level, PHY level or both without compromising throughput and latencies.

The Demand for Secure Interface Solutions Keeps Growing

As an example, while the autonomous vehicle market is still in its early stage, it has already exposed security risks that are being addressed by today’s specifications used in cars for networking, ADAS camera/sensor connectivity, and displays. As advances in various fields of technology and markets happen, better security implementations will be needed. For example, quantum computing will have the capability to break today’s public key algorithms. Interface standards will need to adapt with quantum-safe algorithms over the coming years.

Implementing data security will continue to be on the top of the list of SoC designers’ tasks.

Synopsys Secure Interfaces

Synopsys offers the entire spectrum of interfaces that designers need for a variety of different applications. Their Interface IP products are pre-verified solutions that include silicon-proven Synopsys Controllers integrated with security features and offer reduced risk solutions for optimal security, low latency and area without compromising on performance. This makes it easier for SoC designers to address and implement data protection and security for quick time-to-market.

For more details on the following interfaces, visit the interfaces portfolio page.

Summary

Incorporating security into SoCs is a fundamental requirement for complying with international laws and regulations and satisfying privacy and data protection requirements of electronic systems users. Synopsys offers the industry’s broadest secure interfaces built for various applications such as HPC, Mobile, Automotive and IoT. For more details on Synopsys’ secure interface IP products, visit the product page.

Also Read:

Synopsys Crosses $5 Billion Milestone!

Configurable Processors. The Why and How

New ECO Product – Synopsys PrimeClosure

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9 Trends of IoT in 2023

9 Trends of IoT in 2023
by Ahmed Banafa on 01-03-2023 at 6:00 am
Categories: IoT

9 Trends of IoT in 2023

The year 2023 will hit all 4 components of IoT Model:

  • Sensors,
  • Networks (Communications),
  • Analytics (Cloud)
  • Applications

With different degrees of impact.

 IoT Trend 1: Growth in Data and Devices with More Human-Device Interaction

By the end of 2019 there were around 3.6 billion devices that are actively connected to the Internet and used for daily tasks. With the introduction of 5G that will open the door for more devices, and data traffic.

You can add to this trend the increase adoption of edge computing which will make it easier for business to process data faster and close to the points of action

IoT Trend 2: AI a Big Player in IoT (again)

Making the most of data, and even understanding on a basic level how modern infrastructure functions, requires computer assistance through artificial intelligence.

The major cloud vendors, including Amazon, Microsoft, and Google, are increasingly looking to compete based on their AI capabilities.

Various startups hope to increase their market share thorough AI algorithms able to leverage machine learning and deep learning, allowing businesses to extract more value out of their ever-growing volumes of data.

Artificial intelligence is the fundamental ingredient needed to make sense of the vast amount of data collected these days, and increase its value for business. AI will help IoT data analysis in the following areas:

  • data preparation,
  • data discovery,
  • visualization of streaming data,
  • time series accuracy of data,
  • predictive and advance analytics,
  • real-time geospatial and location (logistical data)

IoT Trend 3: (VUI) Voice User Interface will be a Reality

It’s a battle among industry leaders who would like to dominate the market of IoT at an early stage.

Digital assistant devices, including Alexa, Siri and Google Assistant, are the future hubs for the next phase of smart devices, and companies are trying to establish “their hubs” with consumers, to make it easier for them to keep adding devices with less struggle and no frustrations

Voice represents 80% of our daily communications, taking a chapter from Sci Fi movies, talking to robots is the common way of communications, R2D2, C-3PO, and Jarvis to name few.

The use of voice in setting up the devices, change that set ups, giving commands and receiving results will be the norm not only in smart houses, factories but in between like cars, wearables for example.

IoT Trend 4: More Investments in IoT

IoT’s indisputable impact has and will continue to lure more startup venture capitalists towards highly innovative projects in hardware, software and services.

Spending on IoT will hit 1.4 trillion dollars by 2023.

IoT is one of the few markets that have the interest of the emerging as well as the traditional venture capitalists.

The spread of smart devices and the increase dependency of customers to do many of their daily tasks using them, will add to the excitement of investing in IoT startups.

Customers will be waiting for the next big innovation in IoT—such as

  • Smart mirrors that will analysis your face and call your doctor if you look sick,
  • Smart ATM machine that will incorporate smart security cameras,
  • Smart forks that will tell you how to eat and what to eat,
  • Smart beds that will turn off the lights when everyone is sleeping

IoT Trend 5: Finally, a Real Expansion of Smart IoT

IoT is all about connectivity and processing, nothing will be a better example than smart cities, but smart cities have been in a bit of a holding pattern recently.

Smart sensors around the neighborhood will record everything from walking routes, shared car use, building occupancy, sewage flow, and temperature choice 24/7 with the goal of creating a place that’s comfortable, convenient, safe, and clean for those who live there.

Once the model is perfected, it could be the model for other smart neighborhoods and eventually smart cities. The potential benefits for cities, however, make IoT technology especially compelling.

Cities of all sizes are exploring how IoT can lead to better efficiency and safety, and this infrastructure is increasingly being rolled around the world.

Another area of spreading smart IoT is auto industry with self-driving cars become a normal occurrence in the next few years, today tons of vehicles have a connected app that shows up to date diagnostic information about the car.

This is done with IoT technology, which is the heart of the connected vehicle.  Diagnostic information is not the only IoT advancement that we will see in the next year or so. Connected apps, voice search, and current traffic information are a few other things that will change the way we drive.

IoT Trend 6: The Rise of Industrial IoT & Digital Twin Technology

An amalgamation of technologies is pushing this new techno-industrial revolution, and IoT plays a big part in making manufacturing more efficient, less risky, and more profitable.

Industrial IoT brings enhanced efficiency and productivity through data integration and analysis in a way that isn’t possible without an interconnected manufacturing process

Another notion that is gaining popularity is “digital twin” technology. Through its use, organizations can create a clear picture of how their IoT devices are interacting with the manufacturing process.

This gives keen businesses insight into how the life cycle of their machines operates, and allows them to predict changes that may be needed ahead of time.

According to a Gartner survey, 48% of smart manufacturing adopters have made plans to make use of the digital twin concept

IoT Trend 7: More Movement to the Edge

Edge computing is a technology that distributed the load of processing and moved it closer to the edge of the network (sensors in case of IoT).

The benefits of using fog computing are very attractive to IoT solution providers.

Some of these benefits allow:

  • Users minimize latency,
  • Conserve network bandwidth,
  • Operate reliably with quick decisions,
  • Collect secure a wide range of data
  • Move data to the best place for processing with better analysis and insights of local data.
  • Edge computing has been on the rise in recent years, but the growing scope of IoT technology will make this move even more pronounced. Two factors are leading this change:
  • Powerful edge devices in various form factors are becoming more affordable
  • Centralized infrastructure is becoming more stressed.

Edge computing also makes on-device AI a realistic proposition, as it allows companies to leverage real time data sets instead of having to sift through terabytes of data in a centralized cloud in real time. Over the coming years and even decades, it’s likely that tech will shift to a balance between the cloud and more distributed, edge-powered devices.

Hardware manufacturers are building specific infrastructure for the edge deigned to be more physically rugged and secure, and security vendors will start to offer endpoint security solutions to their existing services to prevent data loss, give insights into network health and threat protection, include privileged user control and application whitelisting and control, that will help in the fast adoption and spread of edge computing implementations by businesses

IoT Trend 8: More Social, Legal, and Ethical Issues

IoT devices are a largely unregulated new technology. IoT will inevitably find itself facing social and legal questions in the near future. This is particularly relevant for data collected by these devices, which may soon find itself falling under the umbrella of the General Data Protection Regulation (GDPR). This regulation regarding the handling of personal data and privacy in the European Union, the GDPR extends its reach beyond the European region. Any business that wants to successfully operate within the EU will need to comply with the guidelines laid out in its 88-page document

Security issues are essential when it comes to legal regulation of personal data. Development teams can ensure the required level of security and compliance on various levels, including data encryption, active consent, various means of verification and other mechanisms. Their goal is to collect data legitimately and keep its accessibility, processing, and storage to a minimum that is dictated by the software product

IoT Trend 9: Standardization Still a Problem

Standardization is one of the biggest challenges facing growth of IoT—it’s a battle among industry leaders who would like to dominate the market of IoT at an early stage. But what we have now is a case of fragmentation. One possible solution is to have a limited number of vendors dominating the market, allowing customers to select one and stick to it for any additional connected devices, similar to the case of operating systems we have now have with Windows, Mac and Linux for example, where there are no cross-platform standards.

To understand the difficulty of standardization, we need to deal with all three categories in the standardization process:

  • Platform,
  • Connectivity,            
  • Applications.

In the case of platform, we deal with UX/UI and analytic tools, while connectivity deals with customer’s contact points with devices, and last, applications are the home of the applications which control, collect and analyze data.

All three categories are inter-related and we need them all, missing one will break that model and stall the standardization process. There is no way to solve the problem of fragmentation without a strong push by organizations like IEEE or government regulations to have common standards for IoT devices

Ahmed Banafa, Author the Books: Secure and Smart Internet of Things (IoT) Using Blockchain and AI

Blockchain Technology and Applications

Quantum Computing

References

1. “Secure and Smart IoT Using Blockchain and AI “ Book by Prof. Ahmed Banafa

2. “Blockchain Technology and Applications “ Book by Prof. Ahmed Banafa

Also Read:

Microchips in Humans: Consumer-Friendly App, or New Frontier in Surveillance?

5G for IoT Gets Closer

Webinar: From Glass Break Models to Person Detection Systems, Deploying Low-Power Edge AI for Smart Home Security

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IEDM 2022 – TSMC 3nm

IEDM 2022 – TSMC 3nm
by Scotten Jones on 01-02-2023 at 6:00 am
Categories: Events, Foundries, Semiconductor Services, TechInsights, TSMC
11 Comments

TSMC CPP

TSMC presented two papers on 3nm at the 2022 IEDM; “Critical Process features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond” and “A 3nm CMOS FinFlexTM Platform Technology with Enhanced Power Efficiency and Performance for Mobile SOC and High Performance Computing Applications”.

When I read these two papers prior to the presentations, my initial reaction was the first paper was describing TSMC’s N3 process and the second paper is describing the N3E process, this was confirmed by the presenter during the second presentation.

My second reaction was these papers continue TSMC’s habit of minimizing the amount of technical detail they present. As I discussed about TSMC’s 5nm paper in 2019 here there is minimal critical pitch information and in 2019 all the electrical results were normalized. In these two papers the electrical results are at least in real units, but the first paper only has Contacted Gate Pitch and the second paper only has a minimum metal pitch. I find this very frustrating, the critical pitches will be measured and disclosed as soon as parts hit the open market and insiders and TSMC’s competitors likely already know what they are, I don’t see how presenting a quality technical paper would be a problem. When Intel presented Intel 4 at the VLSI Technology Symposium last year they presented an excellent paper with all of the key data (I wrote about that paper).

N3 Paper

In the first paper, a Contacted Gate Pitch (Contacted Poly Pitch, CPP as I describe it) of 45nm is disclosed. CPP is made up of Gate Length (Lg), Contact to Spacer Thickness (Tsp), and Contact Width (Wc), as illustrated in figure 1.

Figure 1. CPP.

From figure 1. We can see TSMC has been reducing CPP for each new node by reducing all three elements that make up CPP. Logic designs are done by using standard cells and CPP is a major driver of standard cell width, therefore shrinking CPP is a key part of improving density for a new node.

Minimum Lg is a function of gate control of the channel, for example moving from single gate planar devices with unconstrained channel thickness to FinFETs with 3 gates surrounding a thin channel enabled shorter Lg. Gate control of a FinFET is weakest at the base of the fin and optimization is critical. Figure 2 illustrates DIBL versus Lg for multiple TSMC nodes and also how optimizing the fin reduced DIBL for the current work.

Figure 2. DIBL versus Lg.

The second element in shrinking CPP is the Tsp thickness. Reducing Tsp drive up parasitic capacitance unless the spacer is optimized to lower the k value. Figure 3 illustrates TSMC’s investigation of low-k spacers versus an air gap spacer. TSMC found that a low-k spacer was the best solution for scaled CPP.

Figure 3. Contact to Gate Spacer.

The final element of CPP is contact width. In this work an optimized self-aligned contact (SAC) scheme was developed that provided lower contact resistance. The left side of figure 4 illustrates the SAC and the right side illustrates the resistance improvement.

Figure 4. Self-Aligned Contact.

This work enabled the N3 process with a high-density SRAM size of 0.0199μm2. This work will also be important as TSMC moves forward to their 2nm process. At 2nm TSMC is going to move to a type of gate-all-around (GAA) architecture known as a horizontal nanosheet (HNS) and HNS enables shorter Lg (4 gates instead of three surrounding a thin gate), but Wc and Tsp will still have to be optimized.

N3E

The N3E process is described by TSMC as an enhanced version of N3, interestingly N3E is believed to implement relaxed pitches versus N3, for example CPP, M0 and M1 are all believed to be relaxed for performance and yield reasons. There are varying stories about TSMC N3 and whether it is on time or not. The way I look at it is N5 entered risk starts in 2019 and by Christmas 2020 there were Apple iPhones in store with N5 chip. N3 entered risk starts in 2021 and iPhones won’t hit the market with N3 chips until next year. In my view the process is at least 6 months late. In this paper a high-density SRAM cell size of 0.021 μm2 is disclosed. Larger than the N3 SRAM cell of 0.0199 μm2. The yields for N3 are generally described as being good with 60% to 80% mentioned.

There are two major features of this process discussed in this paper:

  1. FinFlexTM
  2. Minimum metal pitch of 23nm with copper interconnect with an “innovative” liner for low resistance.

FinFlexTM is a kind of mix and match strategy with double height cells that can be 2 fins cells on top with 1 fin cells on the bottom for maximum density, 2 fin cells over 2 fin cells as kind of mid performance and density and 3 fin cells over 2 fin cells for maximum performance. This give designers a lot of flexibility to optimize their circuits.

Figure 5 illustrates the various FinFlexTM configurations and figure 6 compares the specifications for each configuration to a standard 2 over 2 fin cell at 5nm.

Figure 5. FinFlexTM cells.

 

Figure 6. 3nm FinFlexTM cell performance versus 5nm cells.

 A plot in this paper is the via resistance distribution for the 15 level metal stack at approximately 550 ohms. In current processes power comes in through the top of the metal stack and has to travel through the via chain down to the devices, 550 ohms in a lot of resistance in a power line. This is why Intel, Samsung and TSMC have all announced backside power delivery for their 2nm class processes. With extreme wafer thinning the vias bringing power in from the backside should offer a >10x improvement in via resistance.

Comparisons

One question you may have as a reader is how this process compares to Samsung’s 3nm process. TSMC is still using FinFETs while Samsung has transitioned to GAA – HNS they call multibridge.

At 5nm by our calculations TSMC’s densest logic cells are 1.30x the density of Samsung’s densest logic cells. If you look at TSMC density values in figure 6., the 2-2 fin cells are 1.39x denser than 2-2 cells in 5nm, and the 2-1 cells offer a 1.56x density improvement. Samsung has two versions of 3nm with the SF3E (3GAE) version 1.19x denser than 5nm and the SF3 (3GAP) version 1.35x denser than 5nm, falling further behind TSMC’s industry leading density. I also believe TSMC has better performance at 3nm and slightly better power although Samsung has closed the power gap likely due to the HNS process.

Also Read:

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

Does SMIC have 7nm and if so, what does it mean

SEMICON West 2022 and the Imec Roadmap

Podcast EP134: A New Year’s Perspective with Daniel Nenni and Mike Gianfagna

Podcast EP134: A New Year’s Perspective with Daniel Nenni and Mike Gianfagna
by Daniel Nenni on 12-30-2022 at 6:00 am
1 Comment

Dan is joined by his podcast partner and producer Mike Gianfagna. Dan and Mike review the hot topics that trended on SemiWiki over the past year.

Included are discussions about how the semiconductor industry is changing, touching on Moore’s law, chiplets. and government intervention.The forces that are changing semis are also discussed. There are also some observations about two cornerstone industries: foundry and EDA/IP. And some observations about the new post-COVID normal.Are we there yet?

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Analog to Digital Converter Circuits for Communications, AI and Automotive

Analog to Digital Converter Circuits for Communications, AI and Automotive
by Daniel Payne on 12-29-2022 at 6:00 am
Categories: Alphacore, Events, IP

RF Data Converters, analog to digital converter, min

Sensors are inherently analog in nature, and they get digitized for processing by using an Analog to Digital Converter (ADC) block. At the recent IP SoC event I had the chance to see the presentation by Ken Potts, COO of Alphacore on their semiconductor IP for ADCs. I learned that Alphacore started out in 2012, now offering both standard and custom IP for AMS, RF, imaging and radiation hardened electronics through a global organization, based in Arizona.

Data converters can be designed in any IC process node, however the FD-SOI technology provides the lowest power while being tolerant to radiation effects. A 28nm FD-SOI chip will consume 70% lower power when compared to a bulk CMOS process.

RF data converters need to have both high bandwidth and low power to fit applications like phase array architectures, direct to RF sampling, beamforming and 5G radios.

Alphacore designed a hybrid ADC named the A11B5G with a sampling rate of 5GS/s, resolution of 11 bits, with a 800mV supply, and a power of just 50mW by using a 22nm FD-SOI process from GlobalFoundries. One useful feature of this ADC is an integrated auto-calibration, as it eliminates interleaving spurs.

Output spectrum before calibration
Spurs removed after calibration

Another Analog to Digital Converter with even lower power is the A10B3G with a sampling rate of 3GS/s, 8.6 Effective Number Of Bits (ENOB) at 100MS/s, consuming just 13mW, fabricated on the 22nm FD-SOI process from GlobalFoundries.

A10B3G ADC

The first low-power Digital to Analog Converter (DAC) that Ken showed was the D6B5G, and it consumed only 16mW, with 5.4 ENOB, 6-bit input and running at 5GS/s.

Phase Locked Loop (PLL) circuits can be used when demodulating a signal, to distribute clock signals inside an SoC, create a new clock frequency multiple, or recover a signal from a communication channel. The PLL5G is a very low jitter <150fs design, taping out in January 2023 in the 22FDx node.

For serial communications a SerDes circuit is used, and Alphacore has a 22FDx-based design taping out in January 2023, dubbed the SD16G, supporting a data rate from 1Gb/s to 16Gb/s, using either 8 or 16 bit for serialization/de-serialization width. All the popular protocols are supported: PCIe, JESD204, SATA, SRIO, SG-MII, USR/XSR.

All IP from Alphacore comes with a design kit that includes everything that you’ll need for customization:

  • GDSII
  • RTL
  • Schematics
  • DRC/LVS logs
  • Abstract
  • Extracted View
  • Extracted simulation model
  • Verilog-AMS models
  • Integration guide: DFT, I/O

Roadmaps for ADC, DAC, PLL and SerDes were shared for four foundry nodes: TSMC 28HPC+, TSMC 12FFCP, Intel16, GF 22FDx. So 2023 is a very busy year for silicon proven IP.

At Alphacore they are experts at designing radiation hardened circuits, taking special care for effects like Total Ionizing Dose (TID) and Single Event Effects (SEE). They have rad-hard ADC and DAC in GF 22FDx now, then plans for Intel16 in Q2’23, GF 22FDx in Q3’23, and SkyWater RH90 in Q4’23.

Three more rad-hard design examples were for Power Management ICs (PMIC), a 2-color in-pixel ADC, and an imager/camera with high frame rate of 120 FPS.

Summary

Low-power and radiation-hardened applications are a niche market, requiring specialized expertise. At Alphacore there’s a strong track record of delivering a growing family of ADC, DAC, PLL, SerDes, PMIC and imagers. The tapeout schedule for 2023 looks quite full, meaning that you get even more IP that is silicon proven for your designs in 5G, space communications, automotive, even in quantum computing.

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Siemens Aspires to AI in PCB Design

Siemens Aspires to AI in PCB Design
by Bernard Murphy on 12-28-2022 at 6:00 am
Categories: AI, EDA, Siemens EDA

PCB min

This. AI in PCB design is not a new idea. Other PCB software companies also make that claim. But when a mainstream systems technology company like Siemens talks about the subject, that is noteworthy. They already have an adaptive user interface (UI) for their mechanical modeling suite and to assist in low-code development for application flows. Now they are starting to look at how artificial intelligence (AI) could accelerate and improve PCB development and analysis.

A PCB Moonshot

No-one sees PCB design as a career goal – it’s a means to an end. Crafting PCBs is a necessary but thankless task in system design, a task which nevertheless requires massive expertise. To jointly design and optimize for a good layout solution, performance (signal integrity, electromagnetic compatibility, and thermal considerations), together with design for manufacturability. A natural for more automation it would seem, yet this is truly a multiphysics problem crossed with supply chain and business constraints. Established automation is generally good at solving point problems, not so much cross-domain problems. And even within that limitation, some problems like layout and routing continue to depend heavily on heuristics and expert user guidance. In computer science jargon these problems are non-deterministic polynomial time (NP) complete, meaning that deterministic and reasonable run-time algorithms are not feasible.

Which naturally turns attention to AI and machine learning (ML). Since expert PCB designers routinely build high quality PCB designs, perhaps ML systems could capture that expertise. The DARPA IDEA program within the Electronics Resurgence Initiative (ERI) is a moonshot effort aiming at “no human in the loop” electronic design, in which PCB design will be an obvious target. This could span new ML approaches to NP-complete problems, establishing electronic libraries of components, also ML applied to analysis and optimization tools across those multiple domains.

The Siemens view

Siemens recently released a white paper on this topic. The paper is quite high level, not talking too much about specific tools or capabilities. This leads me to believe it is an aspirational stage-setter for upcoming more detailed announcements. I will make that assumption in what follows. The paper talks first about component selection and model creation. I am sure Siemens is following the ERI initiative in their work. For model creation, they suggest tools like natural language processing and image recognition to gather data from documentation data sources to build machine processable models.

For schematic generation, they suggest an intelligent schematic auto-complete feature. When you place a component such as a processor, other components can be added and connected automatically, based on prior experience in similar design applications. They also suggest ML techniques to recognize and suggest reusability potential from earlier generation completed designs.

Constraint creation and management is a natural for AI assistance. Common constraint choices and values should carry over between designs, at least in concept. The tricky part here I would imagine is to minimize the need for supervised learning which could be as cumbersome as simply recreating constraints from scratch. Learning at a meta level, or semi-supervised learning, would be preferable.

Place and route is also an obvious target for AI. Siemens suggest building on their sketch-routing technology (which is pretty neat). They would use these sketch patterns as information to carry between designs (again, a meta level). Finally, they propose using AI for analysis and verification. This to my mind would form the center of a multiphysics design and analysis platform. Siemens is already very experienced in this class of design and analysis for mechanical design. If they bring the same kind of expertise to PCB design, you could image this turning into a powerful suite.

If you missed the link above, you can read the white paper HERE.

 

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The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging

The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging
by Kalar Rajendiran on 12-27-2022 at 6:00 am
Categories: Analytics, Chiplet, proteanTecs

High End Performance Packaging Spectrum

From the multi-chip-modules (MCM) of yester years to today’s System-in-Package (SiP) implementations, things have progressed a lot in terms of package technology. The chiplet movement is not only a big beneficiary of today’s advanced package technologies but drives further advances in this technology area. While a chiplets-based implementation addresses the yield issues of monolithic SoC implementations at 5nm and below, it introduces or exacerbates other challenges. The challenges being signal integrity issues, longer latencies, increased power and test complexities. This puts the spotlight on the Die-to-Die (D2D) interfaces for successful SiP implementations. Solution leaders who are involved with SiP implementations have developed proprietary D2D interfaces but also recognize the need for standardization to accommodate heterogeneous chiplets implementations. The result is the push from an industry consortium to promote an open standard called Universal Chiplet Interconnect Express™ (UCIe™). The consortium includes a long list of technology leaders including heavyweights such as AMD, Arm, ASE, Google, Intel, Meta, Qualcomm, TSMC and others.

All these initiatives are great but chiplets-based system implementations still have to grapple with the “elephant in the room” requirement of delivering defect-free products over its guaranteed lifetime. Scrapping a defective device in an advanced package is a very expensive proposition. BIST techniques detect gross failures such as opens and shorts but are often unable to detect small variations that may cause catastrophic system failures in the future. Current approach to handling this challenge is to implement spare lanes that can replace defective ones. But how to identify which lanes are candidates for replacement? This essentially is the context and crux of a recent webinar hosted by proteanTecs. The presenters included Stefan Chitoraga, a technology and market analyst, Igor Elkanovich, a CTO and Nir Sever, a senior director of business development. Click here to listen to the entire recorded webinar. If you are involved in the advanced packaging space or chiplets implementation space, you will find the webinar quite informational.

Following are some salient points from the webinar.

Yole Intelligence – Stefan Chitoraga

The design cost growth trend from 65nm to 5nm node is one of the drivers behind heterogeneous chiplets adoption. High computational applications in markets such as datacenter networking, high-performance-computing and autonomous vehicles, is another driver.

Yole Intelligence, part of Yole Group, predicts the high-end performance packaging market total to grow at 19% CAGR between 2021 and 2027 to reach $7.87B. The growth rate of technologies such as UHD FO, HBM, 3DS, 3DNAND, etc., will far outrun the growth rate of Si Interposer technology. The barrier to entry is getting high to get into high-end packaging supply chain. Intel, Samsung and TSMC are making heavy investments and offering their innovative products and services for high-end performance applications.

Global Unichip Corporation (GUC) – Igor Elkanovich

The GLink™-2.5D interface improves power efficiency by more than 80% and reduces end-to-end latency by more than 75% compared to a 2D interface. The GLink-3D interface improves power efficiency by more than 96% and reduces end-to-end latency by more than 97%, compared to a 2D interface.

GUC offers its 2.5D and 3D Multi-die Advanced Packaging Technology (APT) platform to its ASIC customers as part of its services. proteanTecs’ interconnect monitoring solution is integrated into GUC’s GLink D2D interface that is used to implement heterogeneous chiplets based SiP solutions. The proteanTecs’ technology monitors signal quality trends and repairs low signal quality lanes to prevent future failures. This in turn improves the quality and production yield of the final product. Without proteanTecs’ technology, many marginal lanes would have gone unnoticed until they failed during field operation.

proteanTecs – Nir Sever

proteanTecs’ D2D interconnect monitoring enables comprehensive visibility and parametric lane grading. The signal monitoring solution for D2D connectivity is supported on InFO, CoWoS®, 3DFabric™ and EMIB technologies and can be implemented with GLink™, AIB, HBM3, OpenHBI and UCIe interfaces.

The solution covers 2GHz to 8GHz speed range with full eye visibility provided on DDR signals. Lane performance is monitored for all lanes over the PVT range during the characterization phase. During the mass production stage, the solution identifies marginal pins and recommends candidates for spare lane swapping, early alerting and spare lane activation as available. In the field, the solution makes predictive maintenance possible by alerting about pins that show signs of wear-out. With this information, lane swapping or module swapping is executed during the next boot of the system, thereby avoiding a catastrophic system failure.

The power of proteanTecs’ technology extends beyond the lane monitoring benefit covered above. Earlier posts on SemiWiki cover how proteanTecs technology based solutions can benefit the development phase as well as the device testing phase for minimizing scrap.

Also Read:

proteanTecs Technology Helps GUC Characterize Its GLink™ High-Speed Interface

Elevating Production Testing with proteanTecs and Advantest’s ACS Edge™ Platforms

How Deep Data Analytics Accelerates SoC Product Development

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Micron Ugly Free Fall Continues as Downcycle Shapes Come into Focus

Micron Ugly Free Fall Continues as Downcycle Shapes Come into Focus
by Robert Maire on 12-26-2022 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services
1 Comment

Micron Crashing 2022

-Micron off the proverbial cliff and falling faster
-Looking at a much longer/deeper decline in memory
-Layoffs, capex cuts, slowdowns- battening down the hatches
-Micron seems to imply more of a “U” or “L” shaped downcycle

Micron’s numbers as bad as we expected And much worse than most on the street expected

We have been involved with the semiconductor industry for over 30 years and have always felt that upsides are usually more than expected and down cycles are usually worse than expected. All you need a is a little imbalance, in either direction, between supply and demand , and the industry seems to start a run away reaction.

Memory is always the worst given its commodity like nature. Micron suggested we are in one of the worst memory downturns in the last 13 years.

Revenue was off an astounding 39% quarter over quarter as both pricing and demand have collapsed.

We see no signs of it getting any better any time soon and neither does Micron as they announced further cuts to capex to “survival” levels, cuts in wafer production and layoffs of 10%. We had projected the layoffs in prior notes as well as capex cuts.

We again would not be surprised to see it get even worse before any signs of it getting better. While Micron does have cash, its net cash position is not great especially if we hemorrhage cash through increasing losses. Management is clearly aware of this and will obviously take further steps to slow losses.

We remain concerned about Samsung and other memory makers

We are very worried that Samsung and other large memory makers could use the industry weakness combined with their deeper pockets to continue to spend to try to take share from Micron in the downturn. It would not be totally out of character for Samsung to press its size advantage here and now.

Not surprisingly, the number of memory makers in the world almost always gets reduced in down cycles.

Maybe a small reprieve from Yangtze memory risk

We have been even more concerned about the new and upwardly rocketing Yangtze memory in China. They tend to aggressively price at or below a 20% discount to the market to take share. Even Apple was headed in their direction. They clearly want to duplicate China’s takeover in the memory market much as what happened in both LED and solar where non Chinese manufacturers were wiped out by aggressive pricing.

Yangtze has been finally put on the “entity” list (Santa’s naughty list) by the US government, which means they will be starved of equipment. However this may be a bit of closing the barn door after the cows have left town as Yangtze seems to have caught up with Micron and Samsung in technology in leading edge NAND.

We had heard that there was a huge rush of equipment going to Yangtze as equipment makers wanted to ship before the embargo door was closed.
They probably have enough equipment still in crates to unbox for the next year….

The embargo of Yangtze will eventually help Micron but not before they grab further share of the NAND market over the next year or two.

Even Apple has now been scared away from doing business with Yangtze but they have more than enough internal demand inside China to keep their fab running flat out as compared to Micron’s slowing production.

The big question? Is it a “V”, “U” or “L” shaped downcycle/recovery?

It seems fairly clear that the memory market looks a lot more like an “L” or “U” shaped downcycle at best. 2023 will be a weak year and 2024 is obviously in question. Foundry is a big of a mixed story with leading edge weaker due to slow PC/server and high end chips while low end and automotive still needs capacity. The issue for equipment makers is that the part of the market that needs capacity are older 200MM fabs making cheap parts while the memory market, which buys 300MM tools by the boatload is weak.

This obviously does not bode well for a recovery in semiconductor equipment. We have never seen a “real” upcycle without the memory makers participating. With memory maker’s capex weak the equipment market will do little more than tread water.

The bottom line is that memory has to get better before we have a “true” upcycle. Memory also can’t get better just by cuts in production, we have to se demand ticking up….. unlike oil, you can’t cut your way to a supply/demand balance.

For now, it feels like 2023 will be the bottom of the “U” shaped down cycle.

Hair on fire mode

We recently visited silicon valley, meeting with industry participants. We got the sense that manufacturers are still frantically rearranging their order book to cope with the China embargo fall out and other cancellations.

Trying to figure out what’s real and what’s not. We don’t think anyone has a clear handle on what the final, bottom level, of business will look like.

This suggests that we still don’t have a clear idea of where the bottom is. This also implies that we still don’t have a good idea of how long before we get there or how long we stay at the bottom. Once the cancelations and order books stabilize we should get a better idea as to where we have wound up and for how long…. until then, all bets are off.

The stocks

We see no good reason to go near Micron any time soon. The odds are that things will continue to worsen in terms of production cuts, lay offs, capex reductions and further delays in new projects. We remain concerned about conservation of cash.

This is obviously not a good harbinger for the rest of the industry as Intel cuts and delays along with others. The macro economic picture is not driving semiconductor demand in the near term, at least not enough to stimulate an up cycle.

We certainly remain very positive about the long term prospects for the industry as strong secular , long term growth remains, however the next year or two could be rough.

One of the issues is that the industry hasn’t gone through a “real”, ” cleansing” down cycle in quite some time so many investors and participants think this is just a one or two quarter blip then back to the races.

We don’t think this is a short blip as evidenced by lay offs and production cuts and cancellations that didn’t happen in prior short blips in an otherwise strong growth pattern. This is a definitive direction change.

We would prefer to sit on the sidelines, perhaps opportunistic if something is overdone, but generally out of the semiconductor space. We don’t see any significant good news coming in 4th quarter results and perhaps some more negative surprises such as we just got out of Micron.

About Semiconductor Advisors LLC‌

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

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