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November 1, 2022January 9, 2023

Why Use PADS Professional Premium for Electronic Design

My IC design career started just a few years before PADS got started in 1985 with a DOS-based tool for PCB design. A lot has changed since then, as PADS was acquired by Mentor Graphics in 2001, and continued to grow under Siemens EDA, now with four versions to choose from, where the top version is called PADS Professional Premium:

This blog focuses on PADS Professional Premium, an EDA tool packed with useful automation, enabling engineers to design and verify their latest electronic systems. I’ll cover the top 12 features to give you an idea of how they help automate engineering tasks.

Schematic Definition

Schematic capture with PADS Designer is the starting point for circuit design and simulation, where components are selected from a centralized library and graphically placed. Hierarchy support allows for abstraction, and you can even use interconnect automation between components and blocks, eliminating manual connections.

Constraints are entered in an intuitive spreadsheet, lowering the time spent on entering physical and electrical rules for PCB designs.

PADS Designer

Part Selection and Library Creation

With billions of parts in the catalog, it’s quick to find the right component using PartQuest Portal Essential, a cloud-based app. For parts that aren’t found you can request they be added, or create your own custom library element.

PartQuest Explorer

Component Sourcing Data

You will always know if your components are available, their price, plus compliance and lifecycle data, because the Supply Chain cloud app is connected with 80 suppliers from around the globe. No more surprises about component shortages, and creating a BOM is quickly done in the Supply Chain app.

Verification by Simulation

Measuring the signal integrity in both pre-layout and post-layout ensures that your design will work reliably in the field, avoiding the time lost and expense of respins. Logic simulation, and AMS simulation using SPICE or VHDL-AMS models verify correctness before manufacturing begins. The analysis environment is integrated with the schematic and layout tools for easier signal integrity analysis.

Signal integrity analysis

Product Variants

Engineers create and manage their product variants by removing and replacing components. Each variant BOM is auto generated, and you can even compare the BOMs for reviews.

Variant Management

Collaboration and Version Management

Having a single source of truth is fundamental to team design, and using cloud access ensures that the right version is being used. Both desktop integration and web browser viewing approaches can be used with Connect for PADS Professional Premium. During the review process designers can mark-up using Connect. Any project related file can be shared with the entire team using Connect.

Web browser and desktop views

PCB Design

Placing components is simplified by using floorplanning groups set in the schematic. Both schematic and layout tools use the same spreadsheet environment for constraints. Automation for plane creation replaces manual effort.

Routing

Users can interactively control the router, instead of manually routing, reducing the PCB layout time up to 80%. The completed PCB layout can be transferred to manufacturing using the popular ODB++ and other formats.

Sketch and Interactive Route

MCAD Integration

PCB and mechanical engineers collaborate by using data exchange standards like ProSTEP file exchange format (IDX). For 3D models you can import into Siemens Solid Edge or NX tools, avoiding the use of two libraries.

Rigid-flex PCB Design

My laptop and smart phone devices both have several rigid-flex boards and this popular design style is supported in a correct-by-construction process used in the Layout tool.

Rigid-flex boards

RF Design

Bluetooth, WiFi and 5G devices have high frequency signals that require RF analysis in tools like Keysight ADS. The PADS tool integrates with RF analysis tools with import/export in schematic and PCB. Layout techniques for RF like via shielding, or tapered and chamfered corner traces are automated.

RF Design

FPGA/PCB Co-design

The high pin counts of FPGAs are challenging to route, so with FPGA/PCB co-design you can have fewer net line crossover, reduced routing layers, improved signal integrity fidelity, shorter traces, and a reduced number of vias.

Before and After: FPGA/PCB co-design

Summary

The PADS Professional Premium tool from Siemens EDA has met the challenges of modern PCB design flow like increased electronic product complexity, through the use of automated features. To get more details there is an 18 page paper, requiring a brief registration.

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October 31, 2022October 31, 2022

Flash Memory Market Ushered in Fierce Competition with the Digitalization of Electric Vehicles

Flash Memory Market Ushered in Fierce Competition with the Digitalization of Electric Vehicles
by Daniel Nenni on 10-31-2022 at 10:00 am
Categories: Automotive, IP

Governments worldwide have been paying close attention to alternative energy vehicles recently. Many have launched related electric vehicle subsidy policies, accelerating global sales over recent years.

In 2021 at IAA Mobility in Munich, Germany, many major car manufacturers, including Porsche, showcased their all-electric or related concept cars. In addition to adding more smart driving features, most new vehicles are equipped with extensive digital touch dashboards. The in-vehicle infotainment system, security and anti-hacking technology and the overall efficiency of electric vehicles have also been improved. In the meantime, cloud and edge computing capabilities are tremendously enhanced, epitomized by digital data streaming processing, zonal structure and digitalization level of the device. New energy storage concepts and new-look environmental enhancements, such as material recycling, have also been introduced.

WEBINAR REPLAY: Increasing Security Concerns in IoT Devices

In June 2022, the European Parliament voted to cease the sale of fossil fuel vehicles from 2035. Although this was opposed, it has become common knowledge that electric vehicles will become mainstream in the future. The digital revolution of the automotive industry has also brought an infinite opportunities to memory chip manufacturers. Among the various types of memory chips, the competition for flash memory chips in the automotive market seems to be more intense.

HPC Platform to become the new standard for future cars with Flash memory

The transition from mainstream fossil fuel vehicles to electric vehicles, and now all-electric and driverless vehicles, requires the constant improvement of driver assistance systems (ADAS), which means that automotive chips must continually strive to deliver higher levels of self-driving features and sustainable enhancements of the AI algorithms.

HPC integrates several complex technologies, such as high-performance multi-core chips, in-vehicle operating systems, diversified software systems, high-speed and low-latency communication, functional safety, information security and OTA to satisfy application requirements like high-level autonomous driving and vehicle control. The introduction of HPC represents a fundamental restructuring of the automotive electrical and electronic architecture. Currently, many Tier 1 automotive manufacturers are considering adopting zonal architecture, where the central HPC platform makes the highest-level decision and then transmits data commands and power through domain control units (DCU) scattered in various parts of the vehicle.

Like today’s smartphones, high-end smart cars with enhanced software and hardware are available at higher costs. As a result, customers can enjoy higher-level audio and video facilities and enhanced security. Customers can also purchase an entry-level configured vehicle that meets regulatory requirements at the lowest cost. For car manufacturers, the source of revenue will no longer rely solely on new car sales or repairs and maintenance, but the software and platform customers can freely choose based on tiered pricing. Customers can subscribe to online video streaming on a monthly or annual basis and even purchase related services such as assisted autonomous driving at a one-time makeup price, which will bring additional revenue to car makers.

According to relevant statistics, the automotive HPC market size in 2022 is about $560 million, and it is expected to grow year on year reaching $8.05 billion by 2025. To seize the market, automotive chip developers have launched various new HPC SoCs (system on chip), some of which are even equipped with AI deep learning accelerators, which will collect, analyze and learn automotive-related data, as well as accumulate extensive data databases, to help future algorithms continue to improve. Therefore, memory chips responsible for collecting and storing vast amounts of information have become the cornerstone of the car’s journey to digitization.

Ensuring a Vehicle’s Information Flow Supports the Flash Memory

With the evolution of automobiles to digitalization, the demand for data storage and the transmission of information is getting higher. The flow of information and the reading/processing of data are key elements in the communication between devices. At the same time, OTA acts as a medium for devices to continuously learn and recognize new devices and communication languages. Therefore, the demand for applications such as OTA wireless updates will increase, and OTA-related personal and vehicle information security maintenance and authentication/authorization will become more critical.

In addition, communicating the flow of information is also required between in-vehicle devices, which created C-V2X (cellular vehicle to everything), a vital role in enhancing road safety, making traffic smoother and saving total energy consumption. As related statistics show, C-V2X is growing at a compound annual growth rate of about 30%. It is estimated that the market will reach $18.8 billion by 2027.

C-V2X is an in-vehicle communication system that includes more specific categories such as V2I (Vehicle-to-Infrastructure), V2N (Vehicle-to-Network), V2V (Vehicle-to-Vehicle), V2P (Vehicle-to-Pedestrian), V2D (Vehicle-to-device) and other information transmission and interpretation between vehicles and different systems or devices. Based on the information flow of these wireless communications, the timely performance and data flow analysis for driving safety is most important.

During this process, all automotive applications require qualified storage products and devices that will endure in embedded environments exposed to extreme temperatures. As a reliable non-volatile memory, NOR flash typically features fast reading speed, high stability, and no data loss when interrupted, which makes it ideal for automotive applications.

WEBINAR REPLAY: Increasing Security Concerns in IoT Devices

However, with the endless increase in the amount of data that devices need to record, such as boot or startup information and user-related information, NAND flash, which has a larger capacity and cost-efficient advantage, gradually revealed its importance.

The Driving Force behind the Automotive Flash Memory Market

After decades of flash memory development, the NOR flash market has already tent to favour niche industries. However, after 2016, the increased demand for consumer electronics and IoT devices with low to medium capacity has led the NOR flash market to pick up and attract new players. The new players have brought NOR Flash into a new era of competition.

From an overall market perspective, benefiting from the rise of emerging application scenarios and the impact of shortages, NOR flash has ushered in a rising cycle. According to an IC Insights report, in the second quarter of 2021, NOR flash only accounted for 4% of the flash memory market. NOR flash products surged by 63% to $2.9 billion last year. NOR flash shipments rose 33 % last year, while average selling prices increased more than 20 %. The NOR flash market is expected to grow another 21% to $3.5 billion in 2022.

However, considering the applications, the current NOR flash is mainly applied in low-capacity applications such as IoT and consumer electronic devices. As competition in this part of the market becomes increasingly fierce, it is easy to fall into a situation where profits diminish. For this reason, major storage manufacturers are trying to break into high-end applications.

The many applications is brought about by the digitalization of automobiles offer opportunities for memory products. According to IC Insights’ statistics on several NOR flash manufacturers’ performance, most NOR flash products’ growth mainly comes from automotive applications. Many manufacturers have seized the automotive market, which has once again activated the vitality of the NOR Flash market.

Winbond is the largest NOR flash supplier, with over $1 billion in sales, accounting for about one-third of the global NOR flash market share. Winbond has been deeply involved in the automotive field for more than ten years as a leading supplier in the NOR flash market. So far, the top ten automobile manufacturers in the world are end customers of Winbond memory products. And their existing niche DRAM, SLC NAND and other product lines have recently expanded their deployment of automotive NOR flash for high-margin product lines.

Winbond Serial NOR Flash has always played a leading role in most automotive applications. However, with the advancement of digitization, the code size that needs to be stored is also increasing. To meet this demand, Winbond launched OctalNAND Flash with 8 I/O ports to fulfil the requirement for instant communication and fast upload and download. Thanks to 8 I/Os, the maximum transmission rate can reach 240MB/s, which can be applied to high-speed and low-latency applications. Octal NOR flash will also join the party shortly.

In addition, Winbond memory products are also suitable for many additional applications, including wireless communication systems, Lidar, tire pressure detectors, in-vehicle wireless charging systems, electric vehicle battery management systems, airbag systems, head-up displays, power management systems and audio systems; as well as the OTA wireless system covering network communication, infotainment and driving recorders. It can support V2X applications, car navigation, digital dashboard, driver monitoring and interactive systems, and it also can be used in gateways, cameras and other in-vehicle fields.

No matter how in-vehicle devices evolve, driving safety will remain a top priority in the automotive industry. Winbond has continuously launched various flash memory products suitable for automotive applications while adhering to the belief of creating high-quality, high-efficiency, low-energy consumption and advanced information security products. Winbond will continue to work closely with automotive manufacturers to fulfil consumers’ wishes.

To learn more, visit Code Storage Flash Memory

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CEVA’s LE Audio/Auracast Solution

VeriSilicon’s AI-ISP Breaks the Limits of Traditional Computer Vision Technologies

October 31, 2022October 31, 2022

Are EDA companies failing System PCB customers?

Are EDA companies failing System PCB customers?
by Rahul Razdan on 10-31-2022 at 6:00 am
Categories: EDA

Electronic Design Automation (EDA) is a critical industry which enables the development of electronic systems. Traditionally, EDA has been bifurcated into two distinctive market segments: Semiconductor and Systems (PCB). If one were to look at the EDA industry in the early 1970’s, one would find significant capabilities for the physical design of both semiconductor (layout) and system PCBs (board layout). Since the 1970’s, the economics of the EDA industry have been highly tied to the semiconductor industry and specifically Moore’s law. Thus, today, the semiconductor EDA business includes massive amounts of automation in synthesis (automatic Place, Route, Floorplanning), verification (formal, simulation, emulation, HW/SW co-verification), and IP (enabling, test, memory controllers, verification IP, etc).

However, interestingly, the System PCB capabilities are largely the same. That is, PCB physical design tools (ex Allegro) continue to provide value and certainly capabilities have been added for improved signal integrity as well as advanced packaging. However, the relative automation to handle the increasingly complex semiconductors at the higher levels of function (programmable fabrics, SW, AI) in a System PCB fabric are completely missing. In this article, we will discuss the nature of this missing functionality, the impact to the marketplace, and the opportunity for EDA to connect the semiconductor and systems parts of the electronic design process.

System PCB Design:

Figure 1: The Modern System PCB Design Process for non-consumer

Traditionally, the relationship between semiconductor companies and their customers has been a function of the volume driven by the customer. In very high volume markets such as the consumer marketplace, large numbers of staff from semiconductor companies work with their system counterparts to effectively co-design the system product.

Figure 2: The System PCB Design Process

For the non-consumer electronics flow, the electronic design steps consist of the following stages (figure one),

System Design: In this phase, a senior system designer is mapping their idea of function to key electronics components. In picking these key components, the system designer often makes these choices with the following considerations:
1. Do these components conform to any certification requirements in my application?
2. Is there a software (SW) ecosystem which provides so much value that I must pick hardware (HW) components in a specific software Architecture ?
3. Are there AI/ML components which are critical to my application which imply choice of an optimal HW and SW stack most suited for my end application?
4. Do these components fit in my operational domain of space, power, and performance at a feasibility level of analysis.
5. Observation: This stage of determines the vast majority of immediate and lifecycle cost.
6. Today, this stage of design is largely unstructured with the use of generic personal productivity tools such as Excel, Word, PDF (for reading 200+ page data sheets), and of course google search. There is little to no EDA support.
System Implementation: In this phase, the key components from the system design must be refined into a physical PCB design. Typically driven by electrical engineers within the organization or sourced by external design services, this stage of design has the following considerations:
1. PCB Plumbing: Combining the requirements of key components with the external facing aspects of the PCB is the job at this stage of design. This often involves a physical layout of the PCB, defining power/gnd/clk architecture, and any signal level electrical work. This phase also involves part selection, but typically of the low complexity (microcontrollers) and analog nature. Today, this stage of design is reasonably well supported by the physical design, signal integrity, and electrical simulation tools from the traditional EDA Vendors such as Cadence, Zuken and Mentor-Graphics. Part Selection is reasonably well supported by web interfaces from companies such as Mouser and Digikey.
2. Bootup Architecture: As the physical design is being put together, a bootup architecture which typically proceeds through electrical stability (DC_OK), testability, micro-code/fpga ramp up, and finally to a live operating system. Typically, connected to this work are a large range of tools to help debug the PCB board. The combination of all of these capabilities is referred to as the Board Support Package (BSP). BSPs must span across all the abstraction levels of the System PCB, so today, often they are “cobbled” together from a base of tools with parts sitting on various websites.

This design flow is a contrast from the System PCB flow of the 1980’s where the focus of a System PCB was largely to build a function. In those days, the semiconductors used to build the function were of moderate complexity and the communication mechanism of a datasheet was adequate. Today, the job of a System PCB designer is really to manage complex fabrics within complex HW/SW ecosystems (AI is coming next).

Yet, the primary method for communication of technical information is with the impression of English sitting in datasheets and websites. Further, most of the non-consumer marketplace has requirements for long life cycles (LLC) which are at odds with the core of the consumer-focused semiconductor chain.

This is all the more ironic because the semiconductor products from EDA companies actually contain all the information which is required by their System PCB EDA counterparts.

Figure 3: The Semiconductor and PCB Tool Disconnect

What is missing? Two fundamental flaws in today’s EDA infrastructure (Figure 2):

Semiconductor Signoff Flow: Today, there is a very strong semiconductor signoff flow supported by EDA tools which transmits information from semiconductor designer to manufacturing. However, there is no signoff flow which transmits information from semiconductor designers to system designers. Rather, this communication interface is manual (legions of folks writing data sheets), lacking deep standards (tool specific symbol libraries), and haphazardly distributed over a variety of channels (websites, downloads, etc).
System PCB Abstraction: Today’s semiconductors not only need to communicate physical layer information, but also various levels of information in the SW (and increasingly AI) layers to system designers. In fact, this information is increasing in value relative to the physical layer information. Currently, while there are plenty of Semiconductor HW/SW/Behavioral EDA capabilities, there is no equivalent in the System PCB space to accept this information.

How do we address this massive gap? Let’s consider the System PCB abstraction.

Building the System PCB Abstraction:

The abstractions can be broadly classified into four categories:

Physical Layer or Hardware Abstraction: This has got to do with component pinouts, component block diagrams and functionality and CAD models for layout etc. This is the bottom layer.
Programmable or Configurability Layer: Microcontrollers, FPGAs, highly programmable multi-function chips are becoming even more flexible as semiconductor vendors drive deeper integrations. For system designers, this means a new arsenal of tools and possibilities for embedded development. The trend towards multiple pre-built configurable options and more importantly towards “Configurable Logic (CL)” which allows embedded programmers to easily add their own custom functionality from simple signal inverters to more complex Mancheter decoders, the CL can operate completely independently from the processor core. This is increasingly creating a very important new level of abstraction for system designers.
Virtual Layer or Software Abstraction: This consists of an entire software stack – from OS ports to drivers to BSPs to IDE environments and libraries that aid end application development. In many end markets, the overwhelming amount of software IP is the driving factor for chip selection.
Artificial Intelligence Abstraction: Finally, given the focus on AI inference on the edge with powerful capabilities around vision or generic data processing, the AI stack supported is increasingly becoming vital for part selection and end application implementation.

However, the state of the union when it comes to availability of these abstractions to system designers is abysmal:

Connecting the Semiconductor and System PCB World

How can this issue be addressed? Two simple steps:

Smart System Designer: The System PCB EDA flow must support all the important abstractions generated and enabled by the Semiconductor Design Process.
Formal Sign Off Flow: The semiconductor signoff flow needs to be extended in formalization, standardization, and content to include the abstractions described above.

Examples of these signoff steps are shown in figure 4 below. In this picture, the validations done in the semiconductor design process are made available in a structured manner to the system designer. Also, machine readable data is made available directly as opposed to being transmitted through a data-sheet.

Fig. 4 Smart System Designer: Connecting the Semi & PCB/System Toolsets

Overall, there is an excellent opportunity for EDA companies to leverage their System PCB and Semiconductor capabilities to add value to the vast number of System PCB customers.

Acknowledgements: Special thanks to Anurag Seth for co-authoring this article.

Related Information:

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Bespoke Silicon Requires Bespoke EDA

Post-Silicon Consistency Checking. Innovation in Verification

Higher-order QAM and smarter workflows in VSA 2023

October 30, 2022March 26, 2023

KLAC- Strong QTR and Guide but Backlog mutes China and Economic Impact

KLAC- Strong QTR and Guide but Backlog mutes China and Economic Impact
by Robert Maire on 10-30-2022 at 5:00 pm
Categories: China, Semiconductor Advisors, Semiconductor Services

-KLA great quarter & guide as backlog mutes China/Economy
-Patterning starts to catch up to wafer inspection outperform
-China impact is limited to leading edge & specific customers
-Cuts in memory capex less impactful on KLA

KLAC reports strong quarter and good guide

Revenues were $2.7B with EPS of $7.06 versus street expectations of $2.6B and EPS of $6.21. Guidance is for $2.65B-$2.95B in revenues and $6.30 to $7.70 EPS versus street expectation of $2.6B and $ 6.15 Guidance is relatively flat but given the current environment thats better than some worst fears.
KLA has always been one of the more reliable financial performers of the group.

Softening outlook with WFE down 20% in 2023

Essentially echoing what Lam said last week, KLAC also expects a 20% or so decline in 2023 WFE. How much of that is China and how much is memory is not immediately clear as the China impact is still being calculated.
Foundry will ikely remain in the 70-75% of business range for the foreseeable future as memory spend in 2023 will be down sharply.

China is $100M impact in Q4 & $600M to $900M in 2023- still unclear

Impact from China embargoes is somewhat limited as much of the product is for trailing edge not contemplated by the controls. However, it is far from zero as KLA equipment is needed to start up new fabs which are mostly found in China. $100M of impact in the December quarter is quite mild as compared to the overall revenue picture. Management suggested that they were still figuring out the full impact of China as the situation is still relatively new and much clarification was needed

Rearranging the order book fills in gaps and smooths revenue

KLAC’s backlog is second only to ASML with many products stretching out over more than a year. This allows the company to rearrange deliveries to fill in gaps of equipment that otherwise would have went to China with other customers in the queue.

KLA could get through most of a downturn on its backlog if the downturn does’t last too long.-maybe just limited to 2023… KLA has always had a history of being able to “dial-in” numbers from existing backlog

Memory less impactful on KLAC than AMAT or LRCX. SK Hynix down 50%+ in Capex

KLA has always done more business in foundry logic and been weaker in memory. Memory capex is clearly being cut much more than foundry as we feel that most memory manufacturers are cutting roughly 50% as we just heard from SK Hynix recently which echoes Micron and others. This should also help KLA weather the storm more so than its peers who have a higher memory exposure, such as Lam.

Reticle catches up to wafer inspection

Wafer inspection has been doing fantastic and reticle inspection has been lagging for quite some time. Reticle inspection is also a bit of a “lumpy” business given large price tags and obviously KLA shipped a number of systems in the quarter. KLA has likely taken share against Applied in this market and/or delivered some new, higher price tag tools.

The stocks

We remain on the sidelines even in the face of what appears to be a relief rally or dead cat bounce in what is a weak outlook for 2023. Investors are obviously happy in that it could have been worse than it appears to be on first blush.
We think that investors may get soft again as growth slows or turns and the full extent of China is known as the year finishes out and 2023 comes into focus.

We also remain concerned about the macro economy and further deterioration of the overall semiconductor market.

Foundry/logic is certainly not immune from cuts and will likely see slowing into 2023. Investors will tire if revenues and earnings go flat or soft for a period.
We have been through many cycles and this one looks harsh given all the negative factors at play.

In the end, secular growth and technology spend will win out but we could have an ugly year or more to get through first and there will likely be opportunities to buy back in at lower valuations before growth returns for good.

KLA is well protected but not nearly as immune as ASML is but they are better than LRCX and AMAT. If we had to own semi equipment it would be ASML first and KLA second with perhaps some smaller cap consumables pays thrown in

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

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Chip Train Wreck Worsens

Podcast EP117: More Good News From Wally Rhines and the SEMI Electronic Design Market Data Report

Podcast EP117: More Good News From Wally Rhines and the SEMI Electronic Design Market Data Report
by Daniel Nenni on 10-28-2022 at 10:00 am

Dan is joined by Dr. Walden Rhines, former CEO of Mentor Graphics, which is now Siemens EDA, and current CEO of Cornami. Wally is also the Executive Sponsor of the SEMI Electronic Design Market Data Report, which is the topic of this podcast.

The current market report for Q2, 2022 documents continued strong performance, with some record-breaking growth. Dan explores the details of the report with Wally, including an assessment of weaknesses in certain regions and what the overall outlook will likely be for the industry.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

October 28, 2022November 28, 2022

TSMC Expands the OIP Ecosystem!

TSMC Expands the OIP Ecosystem!
by Daniel Nenni on 10-28-2022 at 6:00 am
Categories: Chiplet, Events, Foundries, TSMC
4 Comments

This was the 12^th TSMC OIP and it did not disappoint. The attendance was back to pre pandemic levels, there was interesting news and great presentations. We will cover the presentations in more depth after the virtual event which is on November 10^th. You can register HERE.

As I mentioned in my previous post, the Jim Keller Keynote would be worth the price of admission and it was. When I first talked about chiplets I sarcastically said that “chiplets are cheating”. We have spent our entire careers figuring out how to design and manufacture complex monolithic chips and now you can go to Chip Depo and get chiplets, open source software, IP, and even AI tools to more easily design complex chips.

Jim Keller is now the president and CTO of Torrent, an AI chip start up, and that is exactly what he is doing. In his keynote Jim talks about 10 problems to solve during this journey to silicon. Don’t miss it.

Here are my key takeaways from the event:

Contrary to what you may have read from the semiconductor outsider media, TSMC’s progress with advanced nodes is going as planned. N3 wafers are shipping to Apple, N3E, N4X, N3P, N3X, and N2 are on track.

Remember, N3 is Apple SoC specific. N3E is an enhanced version for the masses: Intel, AMD, NVIDIA, Qualcomm, etc… Over the next two years we will see more N3 tape-outs than any prior FinFET node, absolutely.

TSMC also expanded the OIP ecosystem to include a 3D Fabric Alliance. As I have mentioned many times semiconductors is all about the ecosystem and you will never see a more powerful ecosystem in the semiconductor industry or any other industry for that matter.

According to L.C. Lu, TSMC fellow and vice president of design and technology platform, more than 3,000 TSMC employees are part of OIP plus 10,000 people from the more than 100 OIP partners. The OIP now includes 50,000 titles, 43,000 tech files, and 2,800 PDKs.

This new alliance strengthens TSMC’s leadership in the chip packaging business. The press release provides nice detail on the new alliance but here are some clips:

The new TSMC 3DFabric™ Alliance is TSMC’s sixth OIP Alliance and the first of its kind in the semiconductor industry that joins forces with partners to accelerate 3D IC ecosystem innovation and readiness, with a full spectrum of best-in-class solutions and services for semiconductor design, memory modules, substrate technology, testing, manufacturing, and packaging. This alliance will help customers achieve speedy implementation of silicon and system-level innovations and enable next-generation HPC and mobile applications using TSMC’s 3DFabric technologies, a comprehensive family of 3D silicon stacking and advanced packaging technologies.

“3D silicon stacking and advanced packaging technologies open the door to a new era of chip-level and system-level innovation, and also require extensive ecosystem collaboration to help designers navigate the best path through the myriad options and approaches available to them,” said Dr. L.C. Lu, TSMC fellow and vice president of design and technology platform. “Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance offers customers an easy and flexible way to unlocking the power of 3D IC in their designs, and we can’t wait to see the innovations they can create with our 3DFabric technologies.”

OIP 3DFabric Alliance
As the industry’s most comprehensive and vibrant ecosystem, the TSMC OIP consists of six alliances: the EDA Alliance, IP Alliance, Design Center Alliance (DCA), Value Chain Alliance (VCA), Cloud Alliance, and now, the 3DFabric Alliance. TSMC launched OIP in 2008 to help customers overcome the rising challenges of semiconductor design complexity by creating a new paradigm of collaboration, organizing development and optimization across TSMC’s technologies, electronic design automation (EDA), IP, and design methodology.

Partners of the new 3DFabric Alliance have early access to TSMC’s 3DFabric technologies, enabling them to develop and optimize their solutions in parallel with TSMC. This gives customers a head start on their product development with early availability of the highest-quality, readily-available solutions and services from EDA and IP to DCA/VCA, Memory, OSAT (Outsourced Semiconductor Assembly and Test), Substrate, and Testing.

The other interesting announcement was 3Dblox. Dan Kochpatcharin, the new Head of Design Infrastructure Management Division at TSMC, presented the new Open 3dBlox Standard:

TSMC 3Dblox™
To address the rising complexity of 3D IC design, TSMC introduced the TSMC 3Dblox™ standard to unify the design ecosystem with qualified EDA tools and flows for TSMC 3DFabric technology. The modularized TSMC 3Dblox standard is designed to model, in one format, the key physical stacking and the logical connectivity information in 3D IC designs. TSMC has worked with EDA partners in the 3DFabric alliance to enable 3Dblox for every aspect of 3D IC designs, including physical implementation, timing verification, physical verification, electro-migration IR drop (EMIR) analysis, thermal analysis, and more. TSMC 3Dblox is designed to maximize flexibility and ease of use, offering ultimate 3D IC design productivity.

Again, we will cover this in more detail after the virtual event so stay tuned.

Also Read:

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview

Future Semiconductor Technology Innovations

TSMC 2022 Technology Symposium Review – Advanced Packaging Development

October 27, 2022March 26, 2023

LRCX down from here – 2023 down more than 20% due to China and Downcycle

LRCX down from here – 2023 down more than 20% due to China and Downcycle
by Robert Maire on 10-27-2022 at 10:00 am
Categories: China, Semiconductor Advisors, Semiconductor Services
3 Comments

-Lam reports good quarter that is high water mark for cycle
-2023 WFE to be down more than 20%- Cuts spending & Hiring
-If we back out deferred rev outlook would be down for Dec
-Memory already Down & China down $2-$2.5B in 2023

Lam reports good quarter but likely peak of current cycle with clear drop

Lam reported revenues of $5.1B and non GAAP EPS of $10.42. Guidance was essentially flat at $5.1B +-$300M with EPS slightly down at $10 +- $0.75. Its seems quite clear that September 2022 represents the high water mark for the current cycle and we will likely see declines from here with 2023 WFE being down over 20%

Deferred revenues softens the peak and delays revenue decline

Deferred revenues increased another $500M from $2.2B to $2.7B. This represents in part, incomplete systems that have been shipped to be completed later when parts are available.

This tends to reduce the peak revenue and mask/delay the actual decline in business. In our view its likely that December revenue would have already been down more without the deferred revenue instead of appearing somewhat flat.

China and memory/down cycle impacts are similar

Lam said that the loss of China customers would represent a $2 to $2.5B loss for 2023. If we assume an over 20% loss in WFE that Lam projects overall the down cycle and memory weakness likely accounts for more than half of the expected declines in 2023.

China was one the biggest regions for Lam’s business and is obviously not fully coming back from here if ever. It will take a while for China business to stabilize and we won’t know for a while. Lam also commented that “China would be significantly lower” and Korea down as well.

Lam commented on the call that the down cycle could be longer than a typical down cycle given the amount of inventory that had been built up.

“We know how to operate in a down cycle” Lam cuts hiring & manages spending

The company clearly admitted that we are in a down cycle (for all those doubters out there who said its no longer a cyclical industry). The bigger question at hand is how long? This was a very overheated cycle and China was a big part of that overheating. Now a big slug of China is gone and not likely coming back any time soon.

Lam is taking actions by “managing spending” and “slowing hiring to critical hires only”.

Lam remains mainly a turns business with strong competition

As we get into the down cycle, business for Lam will likely take a sharper downturn than others as it is mainly a turns type of business where orders are fulfilled relatively quickly in a normal environment. Lam does not usually have the luxury of a huge order book and backlog that ASML has. Customers can more easily cancel orders with Lam without fear of having to get back on the end of a long waiting line as is the case with ASML. This could potentially lead to a sharper business erosion as memory customers tend to hit the brakes very hard as evidenced by Samsungs prior cutbacks.

Pricing could erode as competition for remaining business heats up

In addition there are obviously many strong competitors to Lam such as Applied Materials, Tokyo Electron, ASMI, and others who all will be going after a much smaller pie. Its highly likely that pricing and therefore margins may be under pressure as it becomes more of a buyers market rather than the sellers market it has been for quite a while.

While Lam does have some unique market niches such as high aspect etch used in NAND, but the vast majority of product is more competitive and far from the ASML’s monopoly on products.

The stocks

WE have very clearly telling investors to avoid Lam due to the risks and clear downturn we are now in. Its going to be quite a while, perhaps through 2023 and maybe beyond before we get an indication of when the cycle will bottom and start to turn.

The typical time to buy these stocks is just before they hit rock bottom in business and we are certainly far from that right now and not likely until sometime in 2023 at the earliest.

We would expect collateral damage to AMAT as they are very much in a similar boar with a similar outgoing tide as well as KLA to a slightly lesser extent due to the more unique products they have.

The main problem is that the tide is going out for everyone with perhaps the main exception being ASML due to its supply limitation and monopoly. Sub suppliers to Lam, Applied and others tend to be at the end of the whip that is about to be cracked. Most all of them have been through many down cycles before and also know how to batten down the hatches as well as Lam does.

We warned it was going to get ugly and here it is

We also warned about the China risk for many years and it clearly will have a long running negative impact. The semiconductor industry and the US will likely be better for it in the long run but in the short term, of the next couple of years, will obviously be painful.

But no pain means no gain and upcycles always follow downcycles

Also Read:

Is ASML Immune from China Impact?

Chip Train Wreck Worsens

Semiconductor China Syndrome Meltdown and Mayhem

October 27, 2022September 22, 2023

Machine Learning Applications in Simulation

Machine Learning Applications in Simulation
by Daniel Nenni on 10-27-2022 at 6:00 am
Categories: Cadence, EDA

Machine learning (ML) is finding its way into many of the tools in silicon design flows, to shorten run times and improve the quality of results. Logic simulation seemed an obvious target for ML, though resisted apparent benefits for a while. I suspect this was because we all assumed the obvious application should be to use ML to refine constrained random tests for higher coverage. Which turned out not to be such a great starting point. My understanding of why those typical constraints are far too low-level to exhibit meaningful trends in learning. The data is just too noisy. Interestingly we had an Innovation in Verification topic some time ago in which (simulation) command-line parameters were used instead in learning. Such parameters represent system-level constraints, ultimately controlling lower-level constraints. That approach was more effective but is not so easy to productize since such parameters tend to be application specific. While it sounds simple, many state-of-the-art ML solutions end up with ineffective results. The reason is that there are so many randomizations made in practical designs and finding key control points to steer test sequences while leaving abundant randomness to stress designs was a challenge.

Cadence has an innovation to address this challenge and recently posted a TechTalk on the progress that has been made.

Regression compression and bug hunting

Increasing coverage is important but just as important is accelerating getting to a target coverage. Cut that time in half and you have more time in your schedule to find difficult bugs, to further increase coverage. There is an additional benefit, that increase focus on rarely hit bins can improve the verification of rare scenarios. If a bug is found with some rare scenario, that area becomes suspect – possibly containing more bugs. Focus on such scenarios increases the likelihood that additional bugs in that area will be found. Naturally, it will also increase general testing around other bins, potentially improving coverage and bug exposure in those cases also.

Overall the tool improves the hit rate in areas that are difficult to hit and provides significant improvement of the environment around challenging areas where holes may be correlated to targeted bins. A targeted attack on such cases may provide extra benefits in increasing coverage.

When can you apply learning?

Xcelium ML distinguishes between augmentation runs and optimization runs. Augmentation runs are those where bugs runs are focused on specific areas of the design or toward rare bins with a goal of improving overall verification quality. Optimization runs are those where the regression run suite is compressed in order to do the same essential work using a fraction of resources. Early in a project, where the simulator is actively learning, the coverage model is not mature, the recommendation is to stick to full regressions but uses Xcelium ML to augment the regression runs to find bug signatures earlier.

By the middle of the project, the coverage model should be sufficient to start depending on compression plus augmentation for nightly regressions. These runs can be complemented periodically with a full regression, for example, running a full regression once a week and an ML-generated regression nightly. Later in the project you can depend even more on compressed runs with only occasional cross-checks against a full regression.

The results across a representative set of designs are impressive. Better than 3X – 5X compression with negligible loss in coverage – as little as 0.1% in several instances to worst case ~1%. Compression may be lower for test suites that have already been manually optimized, but even in these cases 2X compression is still typical. This provides good hints on where Xcelium ML will help most. For example, effectiveness has little to do with the design type and more to do with the testbench methodology. In general, the more randomization is supported in the testbench the better the results you will see.

More detail

An excellent technical talk follows the introduction, explaining in more detail how the tool works and how to use it most effectively. One example they explain is a methodology to hit coverage holes.

You can learn more HERE.

Also Read:

Post-Silicon Consistency Checking. Innovation in Verification

New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development

Test Ordering for Agile. Innovation in Verification

October 26, 2022October 26, 2022

Bespoke Silicon Requires Bespoke EDA

Bespoke Silicon Requires Bespoke EDA
by Michiel Ligthart on 10-26-2022 at 10:00 am
Categories: EDA, Verific
1 Comment

When I first heard the term ‘bespoke silicon,’ I had to get my dictionary out. Well versed in the silicon domain, I did not know what bespoke meant. It turns out to be a rather old-fashioned term for tailor made and seems to be very much British English. The word dates from 1583 and is the past participle of bespeak, according to the Oxford English Dictionary. American English by contrast more commonly uses the word custom. By now, custom silicon has been rebranded to bespoke silicon.

All the same, with plenty of attention in the industry [1], academia [2] and at conferences [3], I am now convinced bespoke silicon is here to stay.

But it seems that most participants in the bespoke silicon conversations miss out on one important aspect. Bespoke silicon requires bespoke EDA (electronic design automation), because one size does not fit all in EDA either. When I say bespoke EDA, I’m not talking about heavy duty work horses like place-and-route tools, static timing analyzers, or HDL simulators. These are fine-tuned to the hilt and support wide varieties of design styles. However, in the first steps of design creation, at the register transfer level (RTL), there are many side steps that can be made to improve the quality of a bespoken silicon design.

An interesting aspect is that it is difficult to provide tangible examples of bespoke EDA. System design houses that we interact with do not tell us what kind of bespoke EDA they are creating. After all, they do not want that information shared with their competitors, although one can easily guess the domains that get the most attention. Low power design tricks, design for test circuitry, intellectual property (IP) customization, and debug functionality quickly come to mind.

Standardization places an important role in bespoke EDA. Without the likes of SystemVerilog, VHDL, UVM, UPF, and encryption standards, it would be difficult to move design content around different EDA tools.

Traditionally, EDA tools are written in C and C++ but those are not languages of choice for semiconductor design teams implementing bespoke EDA. Python, with its vast infrastructure and freely available open source packages, seems to be the front-runner here.

Another advantage that bespoke EDA can bring is the equal treatment of SystemVerilog and VHDL. Rather than dealing with different APIs to obtain, for example, all output ports in a VHDL entity or SystemVerilog module (and ending up with two scripts at the end), it is a lot more productive to have a single API aptly named all_outputs(object)and be done with it. Bespoke EDA’s building blocks will take care of it under the hood.

As I mentioned before, hard-core EDA tools are not going to be replaced by home-grown bespoke EDA applications. But don’t be surprised if real innovation will come from inside semiconductor design organizations that focus significant efforts on their in-house bespoke EDA applications.

About Verific Design Automation

Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

[1] https://www.ansys.com/blog/behold-the-dawning-of-the-era-of-bespoke-silicon

[2] https://www.bsg.ai/

[3] https://www.linkedin.com/pulse/designcon-bespoke-silicon-paul-mclella

Also Read:

Verific Sharpening the Saw

COO Interview: Michiel Ligthart of Verific

Podcast EP116: A Look at the Future of EDA Research With This Year’s Kaufman Award Winner, Dr. Giovanni De Micheli

Podcast EP116: A Look at the Future of EDA Research With This Year’s Kaufman Award Winner, Dr. Giovanni De Micheli
by Daniel Nenni on 10-26-2022 at 8:00 am

Dan is joined by Dr. Giovanni De Micheli, a research scientist in electronics and computer science credited with inventing the network-on-chip (NoC) design automation paradigm and creating EDA algorithms and design tools. Before serving as Professor and Director of the Integrated Systems Laboratory at EPFL, he was Professor of Electrical Engineering at Stanford University. He holds a Nuclear Engineering degree from Politecnico di Milano, and Master of Science and Ph.D. degrees in Electrical Engineering and Computer Science from the University of California, Berkeley.

Dr. De Micheli is also this year’s recipient of the ESD Alliance and IEEE CEDA Phil Kaufman Award.

Dan explores some of the pioneering work being done by Dr. De Micheli and his students. Details on how the NoC paradigm was developed are discussed, along with other work such as superconductors. The discussion ends with an assessment by Dr. De Mikeli of what the future of EDA and semiconductors holds.

The views, thoughts, and opinions expressed in these podcasts belong to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.