SemiWiki – Page 15 – The Open Forum for Semiconductor Professionals

March 18, 2025March 24, 2025

Semidynamics adds NoC partner and ONNX for RISC-V AI applications

Semidynamics adds NoC partner and ONNX for RISC-V AI applications
by Don Dingee on 03-18-2025 at 6:00 am
Categories: IP, Semidynamics

When Semidynamics added support for int4 and fp8 data types to their RISC-V processors, it clearly indicated their intent to target AI inference with hundreds or perhaps thousands of concurrent threads running in their advanced caching and pipelining scheme. Two recent announcements around Embedded World 2025 reinforce their positioning for RISC-V AI applications – a partnership with Baya Systems on NoC technology, and added support for the ONNX Runtime as part of its widening software offering for its RISC-V processors.

WeaverPro enables rapid optimization of low-latency interconnects

At the RISC-V core level, Semidynamics has spent enormous energy creating a deeper, out-of-order RISC-V pipeline and keeping it busy at all times. It’s a key part of their scalability story. But what happens when an application calls for many smaller cores to work together? An increasingly popular option for AI inference is a sea of small RISC-V cores that can provide faster detection and more intense region-of-interest processing in the same system architecture.

In these applications, interconnects between cores and from cores to memory immediately rise to the top of the list of designer concerns. The aggregate bandwidth flowing across an AI inference chip can be staggering, even with efforts to strategically distribute memory in smaller blocks to get it closer to processing units. Hand-designed interconnects easily become bottlenecks with more than a few cores participating.

Baya Systems is a relatively new player in the NoC space with its next-generation WeaveIP and is gaining rapidly thanks to its software-driven, system-level optimization technology, WeaverPro. The partnership between Semidynamics and Baya is a broader effort for scalability into HPC space, but it also provides designers with excellent tools for AI inference chip design. WeaverPro has two components: CacheStudio to analyze cache and memory hierarchy with loading, and FabricStudio to analyze and optimize NoC parameters in actual workloads. The tools provide designers working with Semidynamics RISC-V processors an efficient path to creating high-bandwidth, low-latency interconnects optimized for AI inference applications.

Moving highly portable ONNX models onto RISC-V

Laying down RISC-V hardware is one thing, but the crucial factor in AI inference design is the ability to map a software model onto hardware and optimize the configuration. As AI inference proliferates, designers frequently use open-source AI models to speed their prototyping cycles by applying proven code. ONNX originated within Microsoft as a common format for AI models and is often a lingua franca for import and export between AI frameworks.

The ONNX Runtime can be thought of as a microkernel for AI, accelerating AI models via interfaces to integrated hardware-specific libraries. Semidynamics extended its Kernel Library with ONNX Runtime support to leverage its RISC-V processors efficiently. The library includes primitives for matrix multiplication, transposition, activation functions, and more features for faster development and optimization of RISC-V AI applications.

ONNX support is part of a broader effort, the Aliado RISC-V SDK, providing enhanced software for Semidynamics RISC-V processors. Many RISC-V tools come from the robust open-source ecosystem. Semidynamics gathers those plus its hardware-specific RISC-V processor enhancements into a single environment, saving designers time.

Semidynamics resources for RISC-V AI applications

Semidynamics is carving out a powerful niche in RISC-V AI applications, addressing a whole product with hardware and software ready for designers to focus on adding value on top. The SMD ONNX Runtime and a Model Zoo for Semidynamics RISC-V processors, along with the Aliado Quantization Recommender and the Aliado SDK, are available for download at:

https://semidynamics.com/software

More information on the partnership with Baya Systems and support for the ONNX Runtime is available in the Semidynamics newsroom.

March 17, 2025March 20, 2025

Intel has a new Billionaire CEO!

Intel has a new Billionaire CEO!
by Daniel Nenni on 03-17-2025 at 10:00 am
Categories: Foundries, Intel Foundry
1 Comment

Lip Bu Tan was appointed chief executive officer of Intel Corpor

Great news last week as Intel fills the CEO slot for the 9^th time in 56 years with industry legend Lip-Bu Tan. From what I hear, Intel employees, and the entire industry for that matter, are overjoyed. I’m sure there are one or two competing companies that are concerned but overall it is an absolute love fest.

If you look at education alone Lip-Bu is definitely worthy of the CEO title. When you look at his experience, however, I would say he is a bit over qualified.

Robert N. Noyce
Intel CEO, 1968-1975, Co-founder of Fairchild Semiconductor
Education: Ph.D in physics, Massachusetts Institute of Technology

Gordon E. Moore
Intel CEO, 1975-1987, Co-founder of Fairchild Semiconductor
Education: Ph.D in chemistry and physics, California Institute of Technology

Andrew S. Grove
Intel CEO, 1987-1998, previously worked at Fairchild Semiconductor
Education: Ph.D. in chemical engineering, University of California-Berkeley

Craig R. Barrett
Intel CEO, 1998-2005
Education: Ph.D. in materials science, Stanford University

Paul S. Otellini
Intel CEO, 2005-2013
Education: MBA, University of California-Berkeley, 1974; B.A. in economics, University of San Francisco, 1972

Brian M. Krzanich
Intel CEO 2013-2018
Education: BA in Chemistry from San Jose State University

Robert Swan
Intel CEO January 2019-2021
Education: Bachelor’s degree in Business Administration from the University of Buffalo, MBA from Binghamton University.

Pat Gelsinger
Intel CEO 2021-2024
Education: Bachelor’s degree in Electrical Engineering from Santa Clara University, Master’s degree in Electrical Engineering from Stanford University.

Lip-Bu Tan
Intel CEO 2025-Present
Education: Bachelor of Science in Physics from Nanyang University in Singapore, a Master of Science in Nuclear Engineering from the Massachusetts Institute of Technology (MIT), and an MBA from the University of San Francisco.

Founding Managing Partner of Walden Catalyst Ventures and a Founding Managing Partner of Celesta Capital. Received the Semiconductor Industry Association 2022 Robert N. Noyce Award and Global Semiconductor Alliance 2016 Dr. Morris Chang’s Exemplary Leadership Award. Walden Catalyst Ventures boasts $5B of committed capital over the last thirty years, 600 portfolio companies in 12 countries, and 120 IPOs on fifteen exchanges around the world.

Semiconductor insiders like myself first met Lip-Bu when he joined Cadence Design Systems in 2004 as a member of the Board of Directors. In fact, I knew Cadence even before they were Cadence. EDA legend Jim Solomon merged companies to create Cadence and served as CEO from 1988-1989 before appointing Joe Costello. Joe was CEO from 1989-1997 and made Cadence and EDA in general what it is today, a force of nature in the semiconductor industry. Jack Harding, Ray Bingham, and Mike Fister were CEOs before Lip-Bu took over in 2009 ($853 million in revenue) and resigned in 2021 ($2.99 billion in revenue). Cadence experienced some difficult times after Joe Costello left but Lip-Bu brought Cadence back to a leadership position in EDA, absolutely.

In case you are interested there is an EDA/IP Mergers and Acquisitions Wiki which has been viewed millions of times. EDA in itself is a result of hundreds of mergers and acquisitions.

In addition to working with Intel while at Cadence, Lip-Bu joined the Intel board in 2022 and resigned in August of 2024, Pat Gelsinger resigned on December 1st 2024, probably not a coincidence. Hopefully you understand my “overqualified” comment now?

Bottom line: Lip-Bu Tan knows Intel better and is more qualified than any of the other CEO candidates that have been mentioned in the press by a very wide margin.

The question some may have now is: Why did an overly successful person like Lip-Bu Tan risk his golden reputation and accept the CEO position at a struggling semiconductor legend like Intel?

First let’s look at his compensation:

Base Salary: $1 million per year.
Annual Cash Bonus: Eligible for up to $2 million, based on performance metrics.
Long-Term Equity Awards: Approximately $66 million in stock options and grants, vesting over a multi-year period.
Stock Purchase: Agreed to purchase $25 million worth of Intel shares within the first 30 days of his tenure.

Given that Lip-Bu is a billionaire I would argue that it is not about the money. In the short term his compensation package is less than Pat Gelsinger’s. Pat had a salary of $1.25M and cash bonuses of up to $3.4M annually. Long term, however, Lip-Bu seems to have the stock advantage if successful and I can assure you the $25M stock purchase was Lip-Bu’s idea. He did the same when he joined Cadence. This clearly tells me that this is not a short term mission for Lip-Bu Tan. There is also a clause where Lip-Bu can continue his work with Walden which is an important point. He had the same agreement with Cadence.

I think it is obvious but this is my opinion based on my 40+ years in the semiconductor industry. Lip-Bu Tan is all about establishing his legacy as one of the all-time greatest semiconductor CEO’s. I seriously doubt he would risk his hard earned reputation if he did not see a clear path of success for Intel.

And for you analysts and media who think Lip-Bu only has one year to accomplish this, or are underestimating Lip-Bu’s ability as a CEO: stop embarrassing yourself. And for those of you who are calling Lip-Bu Tan LBT please stop. It sounds like a sandwich.

Also Read:

The Intel Common Platform Foundry Alliance

What would you do if you were the CEO of Intel?

Intel Presents the Final Frontier of Transistor Architecture at IEDM

March 17, 2025March 16, 2025

How FD-SOI Powers the Future of AI in Automobiles

How FD-SOI Powers the Future of AI in Automobiles
by Mike Gianfagna on 03-17-2025 at 6:00 am
Categories: AI, Foundries, Soitec

We are witnessing a significant revolution in automotive design. The software-defined vehicle is taking center stage as disruptive technologies are integrated into mass production. Areas such as autonomous driving, lighting, radar, and other camera-based sensors are all part of this revolution. AI is at the center of many of these changes, delivering continuous advancements in crucial applications such as Advanced Driver Assistance Systems (ADAS).

All this new technology presents many new challenges. Among them are lower power, higher performance and enhanced reliability. It turns out engineered substrates deliver substantial benefits in this environment. Soitec recently published a white paper that provides detailed information about these new trends and the benefits of its fully depleted silicon on insulator (FD-SOI) technology. A link is coming but first let’s explore some of the changes underway and how FD-SOI powers the future of AI in automobiles.

Architectures, Trends and Challenges

The diagram at the top of this post illustrates where Soitec substrates power AI in next-generation ADAS. Stepping back a bit, both the automotive radar and zonal controller markets are poised for significant growth, driven by advancements in AI and semiconductor technologies.

Automotive radar is projected to accelerate rapidly over the next decade. Starting with approximately 80 million units in 2020, mainly comprising Level 1-2 radar systems, each vehicle typically has one radar. By 2025, the market is expected to expand as Level 2++ systems, with around seven radars per vehicle, pushing the total to about 130 million units. By 2030, the market is projected to surge to roughly 530 million units, reflecting the growing prevalence of Level 3-4 systems, which could feature up to ten radars per vehicle.

These systems will be diverse, including in-cabin radar, imaging radar, 3D radar, and standard radar. Standard radar, which measures range and azimuth to detect the distance and direction of objects, is widely used in basic ADAS features like adaptive cruise control and emergency braking. 3D radar is crucial for applications like lane-keeping assistance, blind-spot monitoring, and detecting elevated obstacles, making it a key component of more advanced ADAS levels such as 2+ and 3. The figure below shows the projected growth of this market and the areas where Soitec technology has an impact.

Radar Market Growth

Regarding computing architectures, the traditional organization of electronic control units (ECUs) has been around a decentralized architecture, where each ECU handles specific functions within the vehicle independently. This “distributed ECU” architecture has been popular due to its flexibility and ability to isolate failures to individual ECUs. However, as vehicles become more complex with the advent of ADAS and autonomous driving, the industry is shifting towards more centralized and zonal architectures.

Centralized domain architectures consolidate computing power into fewer, more powerful ECUs or domain controllers, each managing a specific domain such as powertrain or infotainment. This reduces wiring complexity, enhances communication efficiency, and better manages the large data volumes associated with vehicle functions.

Zonal architectures represent the next step, grouping ECUs based on their physical location within the vehicle rather than their functional domain. This reduces wiring length, vehicle weight, and allows for more efficient power distribution and data management, although it increases software complexity. By 2030, vehicles are expected to partially embrace zonal architectures, significantly reducing copper wiring and harness weight, while supporting vast amounts of data generated by these new vehicles.

The diagram below depicts the projected growth of the zonal approach, along with the benefits and challenges this architecture presents.

Evolution of Automotive Architectures

With this background, let’s examine the impact FD-SOI can have.

FD-SOI and its Role to Power the Future of AI in Automobiles

Engineered substrates such as FD-SOI offer significant advantages for next generation automobiles. The key is how the industry can effectively harness FD-SOI to optimize AI in vehicles while maintaining energy efficiency. Soitec’s white paper provides substantial detail on the benefits of its engineered substrates for advanced automotive design. If advanced automotive design is on your horizon, or if you face challenges integrating AI in other types of systems, you will want to get a copy of this white paper. Let’s look at some of the topics that are covered.

By integrating Soitec’s advanced substrates, automakers can deliver more efficient, reliable, and intelligent driving experiences in the next generation of automotive technology. ADAS systems demand significant computational power to process large amounts of sensor data in real-time, requiring trillions of operations per second (TOPS) to perform tasks such as object detection, tracking, and decision-making simultaneously. Energy consumption is also a critical requirement here, as balancing high performance with low power consumption is essential to preserving range autonomy. This tradeoff between power consumption and performance creates a new form of requirement, measured in TOPs/Watt.

The white paper details many commercial applications that benefit from the superior TOPs/W delivered by Soitec’s FD-SOI technology. Details of the impact on Mobileye EyeQ4, NXP’s i.MX 8, STMicroelectronics’ Stellar MCUs, Lattice’s Nexus FPGA platform, and Bosch Radar are all provided.

The vast amounts of data that will be processed by zonal architectures is also discussed. For these systems, lines of code could grow exponentially to between 500 million to 1 billion. Copper wiring will likely be reduced by 50%, along with a 50% reduction in the wiring harness weight. The data generated per day could range between 10 to 12 terabytes, with daily data transfer expected to increase to 40-50GB. This starts to feel like a complex data center in every car.

In addition to reduced power and higher performance (TOPs/W), FD-SOI also offers enhanced reliability. Neutron-induced SRAM failures are discussed, illustrating the technology’s benefits. FD-SOI also offers superior performance with regard to aging effects. Substantial detail is provided on these and many other areas in the white paper.

To Learn More

I have just scratched the surface of the details provided in the new Soitec white paper. As mentioned, if advanced automotive design, or AI integration challenges in other applications are in front of you, this is required reading.

The white paper is titled Powering the Future of AI in Automobiles: FD-SOI’s Transformative Impact on ADAS and Zonal Architectures, and you can access your copy of the Soitec white paper here. And that’s how FD-SOI powers the future of AI in auto.

Also Read:

Powering the Future: How Engineered Substrates and Material Innovation Drive the Semiconductor Revolution

Soitec: Materializing Future Innovations in Semiconductors

EVs, Silicon Carbide & Soitec’s SmartSiC™: The High-Tech Spark Driving the Future (with a Twist!)

Video EP2: A Detailed Look at the Most Effective Way to Conquer Clock Jitter with Samia Rashid

Video EP2: A Detailed Look at the Most Effective Way to Conquer Clock Jitter with Samia Rashid
by Daniel Nenni on 03-14-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is joined by Samia Rashid, co-founder and president of Infinisim. Samia provides detailed background on clock jitter – what it is, what causes it and the various methods to address the problem. Samia describes the unique clock analysis technology developed by Infinisim and the benefits of addressing clock jitter with these tools. The benefits include more competitive products and a more profitable company.

The views, thoughts, and opinions expressed in these videos belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Contact Infinisim

March 14, 2025March 20, 2025

Cutting Through the Fog: Hype versus Reality in Emerging Technologies

Cutting Through the Fog: Hype versus Reality in Emerging Technologies
by Kalar Rajendiran on 03-14-2025 at 8:00 am
Categories: AI, Quantum Computing, Semiconductor Services, Silicon Catalyst

Silicon Catalyst is an organization that supports early-stage semiconductor startups with an ecosystem that provides tools and resources needed to design, create, and market semiconductor solutions. It is the only incubator + accelerator focused on the Global Semiconductor Industry and operates with the motto “It’s about what’s next.” In an era of rapid technological evolution, distinguishing between hype and genuinely transformative innovations is crucial for investors and entrepreneurs alike. Understanding how modern physics informs emerging technologies, identifying the key attributes of successful companies, and recognizing the hallmarks of sound investment opportunities can provide a roadmap for success.

Silicon Catalyst held its Spring 2025 Advisor & Investor meeting and invited Dr. Armand Niederberger to share his views and provoke discussions on how to cut through the fog and separate reality from hype in emerging technologies. Dr. Niederberger is the Executive Director at the Stanford Photonics Research Center and Founder of ExNada – He is also a Silicon Catalyst Advisor, with a focus on quantum technology, photonics and AI – https://photonics.stanford.edu/ and https://www.linkedin.com/in/armand-niederberger-703a146/

Dr. Niederberger’s talk addressed three emerging technologies: Artificial Intelligence (AI), Photonics, and Quantum Computing. He shared his personal viewpoints and not of any of the organizations that he is associated with. The following is a synthesis of his talk.

Modern Physics: The Foundation of Emerging Tech

Modern physics—whether quantum, optical, or atomic—resolves nature at a higher resolution than classical physics. It provides the foundational science behind many transformative technologies, from lasers and GPS to MRI machines, quantum dots, and atomic clocks. However, translating cutting-edge science into practical applications requires more than just theoretical breakthroughs; it demands scalable, reliable, and economically viable solutions. A key distinction to keep in mind is that while science provides the equivalent of cameras—allowing us to observe and understand nature more precisely—companies need tools, akin to wrenches, that allow them to build real-world solutions. Pure quantum effects, for instance, are often fickle, necessitating careful engineering to create robust, commercially viable technologies.

The Three Pillars of Success

Investment success in emerging technologies hinges on three critical factors: team, technology, and timing. The best teams are those that focus on solving specific customer and market needs rather than being enamored with their own technological prowess. Historical cautionary tales like MySpace and Quibi illustrate the perils of poor leadership and misguided strategy. A promising technology must be scalable, reliable, and offer a compelling reason for adoption. If switching to the new technology is too costly or complex, market resistance will stymie growth. Even the best technology can fail if the market isn’t ready. Apple’s Newton and Google Glass were ahead of their time, leading to commercial failure despite their technical ambition and excellent implementation (considering the state of technology at the time).

A fundamental truth remains: Nobody cares about the technology itself—it’s the economic benefit to clients that matters. The most successful companies exhibit three hallmarks: hungry teams solving specific problems, scalable and transparent technology with multiple paths to success, and solutions that enable clients to realize significant economic benefits.

What to Avoid in Emerging Tech

Teams that claim to know and solve everything without specificity should raise concerns. Hyper-complex lab technologies that lack consumer viability are another warning sign. Additionally, hype-driven over-allocation of funds can lead to unsustainable growth and market disillusionment. All too often, pitches overflow with buzzwords, attempting to ride a wave of hype with no underlying value proposition. Your warning lights should go off each time people claim to be smarter than you, or that the need for providing specific value to their customers does not apply to them because they are so brilliant, technologically advanced or ahead of the curve. The same applies when gigantic future markets are being pitched, particularly when they are nebulous.

AI: A Revolution or Just Curve Fitting?

Artificial Intelligence (AI) is one of the most discussed emerging technologies, yet at its core, it is often just sophisticated curve fitting. However, we should remember that a steam engine is basically a boiler, cylinder and piston – yet it powered the industrial revolution. Thus, just like people needed to understand how to utilize the possibilities brought about by the steam engine, we, today, need to understand what AI can and cannot do. Dr. Niederberger expects that AI will have transformative impacts comparable to the industrial revolution, but on a much shorter timescale. To test the founders’ understanding of their technology and to avoid oversellers, Investors should ask key questions such as: What can the AI system not do? How is result accuracy verified? How does the company handle feature engineering?

Current opportunities in AI span various sectors, including task automation in areas like analysis, image recognition, design, and production. Robotics applications are also on the rise, focusing on support, co-habitation, and autonomy. Several companies are leading the way in AI infrastructure, such as Nvidia, TSMC, ARM, Microsoft, AWS, and Google. Additionally, notable AI startups like trykintsugi.com, Distyl.ai, and Quantifind are contributing innovative solutions in the field. These developments highlight the growing impact of AI across industries and its expanding commercial potential.

Photonics: The Future of Speed and Efficiency

Photonics, which leverages light to solve problems, offers advantages in speed, energy efficiency, and computing power. Key questions for investors include: How mature is the manufacturing process? How does the technology integrate with existing copper-based systems?

Opportunities in photonics are growing across several areas, including faster data centers and communications, which enhance the speed and efficiency of data transfer. Photonics also plays a crucial role in enabling applications for AI and quantum computing. Innovations in design automation and analog computing are driving advancements in this field, while manufacturing progresses with integrated photonics and metamaterials. Notable companies leading the charge in photonics include Ayar Labs (a Silicon Catalyst Portfolio Company) , Mixxtech, PumpkinSeed, and Ligentec, highlighting the rapid evolution and potential of this technology across various industries.

Quantum Technologies: The Promise of the Quantum-Classical Interface

Quantum technologies hold significant promise, particularly in the quantum-classical interface. Key questions for investors include: How scalable is the technology? How do customers scale with it? What are the coherence times?

Opportunities in quantum technologies are expanding in several key areas, including high-precision measurement and sensing, as well as quantum-secure communications, which ensure secure data transmission. There is also a growing market for infrastructure components like detectors, sensors, control software, and materials essential to quantum systems. Notable companies leading advancements in quantum technologies include AOSense, Quantum Machines, and IDQuantique, highlighting the significant potential and innovation within the field.

Evaluating Emerging Technologies

The best investment opportunities lie in companies that offer robust solutions to specific problems, operate in growing and enabling markets, and make deliberate strategic decisions.

By adhering to these principles, investors can navigate the ever-evolving landscape of emerging technologies with confidence, ensuring that their capital is deployed in ventures poised for real-world success rather than speculative hype.

Summary

For any entrepreneur with a groundbreaking idea in semiconductor technology, Silicon Catalyst offers the ideal environment to turn that idea into reality. Through its extensive network of partners, advisors, mentors, and industry resources, it provides startups with a unique advantage in navigating the complexities of semiconductor development. By joining Silicon Catalyst, startups not only gain access to essential tools and expertise but also become part of a global network that is driving the future of technology.

To learn more, visit SiliconCatalyst.com.

Also Read:

CEO Interview: John Chang of Jmem Technology Co., Ltd.

CEO Interview: Dr. Zeynep Bayram of 35ELEMENTS

Navigating Frontier Technology Trends in 2024

March 14, 2025March 16, 2025

CEO Interview with Fabrizio Del Maffeo of Axelera AI

CEO Interview with Fabrizio Del Maffeo of Axelera AI
by Daniel Nenni on 03-14-2025 at 6:00 am
Categories: CEO Interviews

Fabrizio Del Maffeo is the CEO and co-founder of Axelera AI, the Netherlands-based startup building game-changing, scalable hardware for AI at the edge. Axelera AI was incubated by the Bitfury Group, a globally recognized emerging technologies company, where Fabrizio previously served as Head of AI. In his role at Axelera AI, Fabriozo leads a world-class executive team, board of directors and advisors from top AI Fortune 500 companies.

Prior to joining Bitfury, Fabrizio was Vice President and Managing Director of AAEON Technology Europe, the AI and internet of things (IoT) computing company within the ASUS Group. During his time at AAEON, Fabrizio founded “UP Bridge the Gap,” a product line for professionals and innovators, now regarded as a leading reference solution in AI and IoT for Intel. In 2018, Fabrizio, alongside Intel, launched AAEON’s “AI in Production” program. He also previously served as the Country Manager for France and Sales Director for Northern, Southern and Eastern Europe at Advantech, the largest industrial IoT computing company. In this role, he also led the intelligent retail division. Fabrizio graduated with a master’s degree in telecommunication engineering from Milan Politecnico University.

Tell us about your company?

Axelera AI was founded in July 2021 with Evangelos Eleftheriou, emeritus IBM Fellow, myself and a core team from Bitfury AI, IMEC, researchers from IBM Zurich Lab, ETH Zurich, Google and Qualcomm.

Our mission is to rapidly provide access to advanced Edge AI-native hardware and software solutions for companies of all sizes across a range of market verticals and place AI in the hands of those who could not otherwise afford it. We do this by delivering faster, more efficient and easy-to-use inference acceleration while minimizing power and cost. To do this, our platform is purpose-built to support AI strategies across a wide-range of industries while seamlessly integrating with existing technologies.

With our team of brilliant engineers, developers and business experts, we are focused on building our solutions and ecosystem that together will drive the democratization of AI, enabling a green, fair and safe world.

In three years, Axelera AI has raised USD 120 million, built a world-class team of 190+ employees (including 60+ PhD’s with 40,000+ citations), launched its Metis™ AI Platform and is the largest AI semiconductor company in Europe.

The company is backed by major institutional investors, including Samsung Catalyst Fund, the European Innovation Council Fund, Innovation Industries Strategic Partnership Fund (backed by MN/Pension Fund for Metal and Technique), Invest-NL Deep-Tech Fund , along long-standing investors Verve Ventures, Innovation Industries, Fractionelera,the Italian sovereign fund CDP Venture Capital SGR, the Dutch Enterprise Agency (RVO), Bitfury, Federal Holding and Investment Company of Belgium (SFPIM), imec andimec.xpand.

What problems are you solving?

Current iterations of AI technology have leveraged more general purpose acceleration and have delivered expensive, power-hungry solutions that prove to be inefficient for many use cases. In the cloud, with access to water-cooling and large power supplies, this architecture suffices, but it is poorly suited for the edge.

At Axelera AI, we are revolutionizing the field of artificial intelligence by developing an industry-defining hardware and software platform for accelerating computer vision and generative AI on edge devices. Our platform, built using proprietary in-memory computing technology and RISC-V dataflow architecture, delivers industry-leading performance and usability at a fraction of the cost and energy consumption of current solutions.

Power consumption is a critical factor both on devices and in data centers. Axelera AI offers leading compute density with exceptional core efficiency which means systems can easily crunch data without draining power or running hot, with a typical use case requiring just a few watts.

One of the biggest challenges for Edge AI is optimizing neural networks to run efficiently when ported onto a mixed-precision accelerator solution. Our platform includes advanced quantization techniques and mapping tools that significantly reduce the inference computational load and increase energy efficiency. By creating integrated solutions that are powerful, cost effective and efficient, Axelera is bringing inference to the edge with accuracy.

What application areas are your strongest?

Axelera AI is primarily focused on providing powerful AI inference solutions for edge computing and high-performance applications. The first generation of AI processing unit, Metis, focuses on primarily on computer vision and some of the strongest application areas include:

Security and Surveillance Axelera AI excels in real-time image and video processing for applications like campus management, safety, surveillance, access control
Automotive: autonomous vehicles and infotainment
Industrial automation: real-time high speed quality control, pick-and-place and general purpose robotics
IoT Devices: Their technology is well-suited for IoT applications, enabling smart devices to process data locally with minimal latency.
Smart Cities: AI-powered analytics for traffic management, public safety, and resource optimization can benefit from Axelera’s capabilities.
Retail: Providing a frictionless experience for customers with personalized recommendations, queue management, fast and efficient checkouts, and smart mirrors.
Healthcare: With nearly 10 million fewer health workers[1] than the world needs, bringing AI inference to the healthcare system will allow doctors to more quickly understand and diagnose patients.

We have been working on broadening our future product offerings from the edge to the enterprise servers to address the growing computing needs for generative AI, large language models and large multi-modal models.

What keeps your customers up at night?

Neural networks are getting bigger and they require more computations. Scaling performance using CPUs and GPUs are inefficient and extremely expensive. We are fully focused on tailoring our technology around the new emerging needs, efficiently offloading completely the AI acceleration from the CPU inside our AI processing unit.

We must also contend with the realities of the current chip market. These realities include the high cost of hardware, as well as ongoing shortages in the industry. A discrepancy in the demand and supply of chips, fueled by supply chain delays, the pandemic, natural disasters and labor market changes, is heavily impacting the global semiconductor space.

There is also the question of Moore’s Law and energy usage. Moore’s Law suggests that the number of transistors in an integrated circuit would double every two years, which played a driving role in modern tech development like computers. However, modern semiconductors are far more technologically complex and require significant energy to produce and progress. With our Metis AI Platform, we aim to overcome these challenges by delivering a product that packs the power of an entire AI server – all at a fraction of power consumption and cost of other solutions.

What does the competitive landscape look like and how do you differentiate?

Until now, AI systems and applications have relied on the computational performance of large, power hungry and expensive hardware. However, fully unlocking the potential of AI, especially at the Edge, requires a dramatic increase in FPS/$ which will enable complex AI applications to run on-device at the Edge. Running the industry-standard benchmark of ResNet, YoloSSD-Mobilenet families, the Metis PCI delivers high performance at a fraction of power consumption and price of today solutions. Furthermore, Metis excel in real application pipelines thanks to the possibility to run in parallel on different core multiple networks, delivering 5-10x higher throughput than existing solutions.

A major advantage of our SRAM-based D-IMC technology is that it has been implemented in standard CMOS technology. Our design uses proven, cost-effective and standard manufacturing processes, readily available in any silicon foundry which brings supply chain resiliency to system builders. Memory technologies are also a key driver for lower lithography nodes. So, Axelera AI will be able to easily scale performance as the semiconductor industry brings advanced lithography nodes into volume production.

We are also going beyond just the accelerator technology and chip development, building a fully interconnected ecosystem of support powered by a versatile and easy-to-use software stack: our Voyager^TM SDK.

What new features/technology are you working on?

The full production-ready Metis AI platform is now in production delivering high performance and preserving 99% of the original model’s precision, indistinguishable from GPU-based inference models, while offering 4-5 times throughput, energy efficiency and cost savings.

We have a complete product portfolio including standard form factors like an M.2 card to PCI-E cards capable of handling the most demanding vision applications. We have a complete roadmap that scales from single digit watt usage to enterprise grade server usage.

Our platform includes advanced quantization techniques that enable customers to run out of the box state of arts neural networks and mapping tools that significantly reduce AI computational load and increase energy efficiency,

Finally, our software tool chain allows customers to build up a complete application pipeline in a matter of minutes, simplifying the deployment of artificial intelligence in any device and opening up unprecedented opportunities for mass deployment of AI solutions.

Nowadays we are working on expanding the neural networks zoo to support Large Language Models on Metis. We are also in advanced design with the new AI processing unit, complementary to Metis and more focused on generative AI workload. The product line will be announced later next year.

How do customers normally engage with your company?

Whether you are a computer vision system developer or integrator, software vendor or OEM, our AI acceleration hardware has been built to meet your needs. Delivering leading AI acceleration hardware in a range of industry accepted form factors supported by our easy-to-use software stack, Metis simplifies development, integration and deployment of AI inference acceleration.

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We are working on creating a frictionless experience for our customers who soon will be able to buy online our products and get supported by an online developer community.

Contact Alexera AI

[1] World Health organization: Health workforce

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March 13, 2025April 6, 2025

A Realistic Electron Blur Function Shape for EUV Resist Modeling

A Realistic Electron Blur Function Shape for EUV Resist Modeling
by Fred Chen on 03-13-2025 at 10:00 am
Categories: Lithography

Peak probability at zero distance actually makes no sense

In lithography, it is often stated that the best resolution that can be achieved depends on wavelength and numerical aperture (NA), but this actually only applies to the so-called “aerial” image. When the image is actually formed in the resist layer, it also depends on an additional factor, known as blur.

What blur does is reduced the image contrast, i.e., the difference between the maximum and minimum doses delivered for an image pattern. The range of doses delivered to the wafer is clustered closer to the threshold dose for printing. This inherently worsens the sensitivity to the stochastic effect of photon shot noise and random secondary electron yield per photon.

Blur can have multiple origins: flare [1], image fading [2], stage desynchronization [3], and photoelectrons and secondary electrons [4]. The EUV-induced plasma [5] provides further sources of unwanted remote exposure.

In order to quantitatively assess the impact of blur on contrast, it needs to be described mathematically. It is represented as a spatial distribution function, which is convolved with the optical image to produce the net image deposited in the resist. Commonly used functions for the blur shape are Gaussian functions [1] and exponential functions [4]. However, these functions peak at zero distance, which would indicate that ~80 eV EUV photoelectrons hardly move any distance. This is clearly a nonphysical representation. On the other hand, it is well-known that the 1/e attenuation length for these photoelectrons is ~ 1 nm [4]. Experimental data are consistent with probability of no reaction or scattering of electrons fitting an exponential decay function with decay constant of ~ 2 nm [4] for distances >1 nm. Such a function can be obtained by taking a difference of two exponential functions, as shown in Figure 1. There is a peak at ~ 1 nm, which reflects the scenario that most photoelectrons quickly move 1 nm distance in less than 0.2 fs before any scattering or reacting.

Figure 1. The exponential function (orange) has an unrealistic peak probability at zero distance. Subtracting an exponential function preserves the long-distance behavior but gives a more accurate representation of the photoelectron mean free path ~ 1 nm. Here the difference of exponential functions is shown in black. The orange exponential function is 0.25/nm exp(-x/2 nm), while the subtracted exponential function is 0.05/nm exp(-x/0.4 nm).

With this function, the next step is to convolve it with the sinusoidal optical image.

Some Necessary Math…

As a kind of lemma, we first derive the formula for integration of the product of an exponential function and a cosine function:

Then, we use this to get our formula for the convolution of an exponential function with a cosine function:

Basically, it states that the effect of convolving the exponential function with a sinusoidal function is to effectively reduce the amplitude of that sinusoidal function by a factor of 1/(1+(2 pi lambda/pitch)^2), where lambda is the decay distance of the exponential function. The convolution for the difference of two exponential functions is simply the difference of the separate convolutions of the individual exponential functions.

Example One: 15 nm Half-Pitch

First, we consider the impact of the new blur shape on a simple 15 nm half-pitch image, typically expected for the 5nm node family (including 4nm node).

Figure 2. The electron blur function of Figure 1 reduces the NILS for 15 nm half-pitch (0.33 NA system). The stochastic image of electrons/nm2 (right) assumes a 20 mJ/cm2 absorbed dose with a nominal electron/photon ratio of 8 (can vary from 7 to 9).

The first effect to note is the reduction of image contrast mentioned earlier. The normalized image log-slope (NILS) is consequently reduced from 2.84 to 1.85. The reduced contrast also worsened the stochastic influences on the electron density, compared to no blur. The main effect is degradation of the edge definition. There is also increased defectivity in the nominally exposed region, which can lead to shorts between metal lines when negative-tone metal oxide resists are used. This suggests insufficient dose.

The absorbed dose of 20 mJ/cm2 corresponds to 60 mJ/cm2 in 20 nm thick metal oxide resist. A higher dose would lead to increased exposure to the EUV-induced plasma, reducing the resist thickness [7]. This would in turn reduced the absorbed dose used to define the resist pattern, aggravating the stochastic effects.

Example Two: 8 nm Linewidth (16 nm and 32 nm Pitches)

Looking at post-2nm nodes, 8 nm metal half-pitch is specified by the IRDS 2022 edition [6]. A smaller pitch increases the flattening of the sinusoidal optical image, which reduces the contrast further. Figure 3 shows the 8 nm half-pitch, with a larger NILS reduction, and hence, substantially more stochastic defectivity, even affecting the nominally unexposed areas.

Figure 3. The electron blur function of Figure 1 reduces the NILS for 8 nm half-pitch (0.55 NA system). The stochastic image of electrons/nm2 (right) assumes a 20 mJ/cm2 absorbed dose with a nominal electron/photon ratio of 8 (can vary from 7 to 9). Note that two 16 nm pitches are shown here in the stochastic image.

A smaller linewidth is also naturally more sensitive to stochastic fluctuations of electron and photon density because NILS is reduced when the linewidth is reduced relative to the pitch. Figure 4 shows this for a 32 nm pitch with the same 8 nm linewidth.

Figure 4. The electron blur function of Figure 1 reduces the NILS for 8 nm linewidth on 32 nm pitch. Note that a two-beam image is used assuming maximal depth of focus. The stochastic image of electrons/nm2 (right) assumes a 20 mJ/cm2 absorbed dose with a nominal electron/photon ratio of 8 (can vary from 7 to 9).

The severe blur-aggravated stochasticity for both 8 nm half-pitch and linewidth means High-NA (0.55 NA) EUV systems cannot support either direct printing or double patterning for the 16 nm pitch, respectively. This goes back to the earlier point that electron blur, not NA, becomes the effective resolution limiter in EUV lithography [8].

References

[1] L. Sun et al., “Review of resist-based flare measurement methods for extreme ultraviolet lithography,” J. Micro/Nanolith. MEMS MOEMS 12, 042001 (2013).

[2] T. A. Brunner et al., “Image contrast metrology for EUV lithography,” Proc. SPIE 12292, 122920A (2022).

[3] D. Schmidt et al., “Characterization of EUV image fading induced by overlay corrections using pattern shift response metrology,” Proc. SPIE 11147, 1114713 (2019).

[4] O. Kostko et al., “Evaluation of Electron Blur for Different Electron Energies,” J. Photopolymer Sci. & Tech. 37, 315 (2024).

[5] Y-H. Huang et al., “A study of hydrogen plasma‑induced charging effect in EUV lithography systems,” Discover Nano 18:22 (2023).

[6] https://irds.ieee.org/editions/2022/irds%E2%84%A2-2022-lithography

[7] F. Chen, Resist Loss Model for the EUV Stochastic Defectivity Cliffs.

[8] F. Chen, Why NA is Not Relevant to Resolution in EUV Lithography.

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March 13, 2025April 6, 2025

Siemens Fleshes out More of their AI in Verification Story

Siemens Fleshes out More of their AI in Verification Story
by Bernard Murphy on 03-13-2025 at 6:00 am
Categories: AI, EDA, Siemens EDA

AI maximizing verification productivity min

While Cadence and Synopsys were sharing a lot of detail over the past few years about what they were doing in AI, Siemens EDA seemed content to offer a very general picture about their intentions without getting into a lot of detail. At DVCon 2025 they finally pulled back the curtain. Why wait until now to announce?

Darron May (Director of AI Product Management at Siemens Digital Industries) hosted the session and pointed to the depth Siemens can already boast in AI – 1400 AI experts, nearly 4000 patents – developed over many years working with large enterprises. Also note Darron’s title – he stressed that Siemens is now one tech company, not Siemens plus Siemens EDA. The Siemens centralized AI team have been building a platform for the EDA guys, who have been integrating with and building on this broader expertise to develop and roll out their broader AI gameplan. Makes sense to me. Takes a little longer to get to announcement but ensures they can start from a proven base.

A quick recap on why AI in EDA

Darron opened with the obligatory marketing nod to chips becoming more complex (in part thanks to AI content), together with projections that the industry is going to be short 27,000 expert designers by the end of the decade. All true but I’d like to add my own thoughts. The highly visible part of this growth, around AI accelerators from Nvidia, AMD, and the hyperscalers, is the tip of the iceberg. The real volume is in AI applications: wearables, smart homes, transportation, smart offices, medical, industrial, utilities, etc. IoT applications alone are expected to top 6 billion units by 2030. Those are going to be built on embedded designs customized with sensing, AI, and communications components to differentiate and be super cost and power effective.

These “applications” companies/business units have design and AI expertise, but they can’t build giant teams of experts because there aren’t enough experts. They must rely even more heavily on EDA, IP, even packaging technologies to meet their goals. You start to see why the industry needs to spin up more designers, including AI-assisted designers, to keep pace with demand.

Siemens advances in AI for verification

Siemens are broadly leveraging three types of AI in this domain: analytical based on unsupervised learning (ML), predictive based on ML and statistical analysis to predict future behaviors, and generative/agentic support based on LLMs. This is quite in-line with similar effort from big EDA companies.

The announcements aren’t groundbreaking in this industry but bear in mind that Siemens are catching up. I’ll start with their ViQ (Questa verification IQ) platform. The Coverage Analyzer already offers (in production) analysis to predict patterns and holes in coverage, provide root cause analysis and suggest solutions. For Debug, they have early adopter engagements in bad commit prediction, root cause prediction and signature prediction. And in regression navigation they have early adopters in smoke test prediction.

QCX (coverage acceleration), PSS Assist (GenAI for PSS) and Doc Assist (auto-generating docs) are all in early adopter engagements.

For creation, they are promoting Property Assist (GenAI assertion generation with extensive checking through static and formal tools to validate correctness) – this is the early adopter stage, whereas CDC Assist and RDC Assist (massively distilling crossing violations) are already in production.

There are multiple other capabilities planned but in the interests of avoiding future-looking statements I will leave those out 😀.

In summary, several capabilities in production and more on the way through early deployment. One thing that stuck with me – Siemens has that central AI team as a potential differentiator over others in the design and verification world. Worth watching. You can explore Siemens capabilities in EDA HERE.

March 12, 2025March 12, 2025

CEO Interview with Dinesh Bettadapur of Irresistible Materials

CEO Interview with Dinesh Bettadapur of Irresistible Materials
by Daniel Nenni on 03-12-2025 at 10:00 am
Categories: CEO Interviews

Dinesh Bettadapur serves as the Chief Executive Officer of Irresistible Materials Ltd. Dinesh has over 20 years of executive management experience in the semiconductor industries and has held significant leadership roles encompassing general management, P&L management, sales, business development, strategic alliances, and operations. He has worked at industry leaders such as ASML, Intel, and Lam Research as well as multiple Silicon Valley startups and led them toward a significant degree of business growth including 3 successful exits.

Tell us about your company?

Irresistible Materials is an innovative electronic materials company that has developed a novel EUV resist material to help meet the unique and significant challenges of EUV lithography. It was founded in 2010 as a spinoff from the University of Birmingham and has developed other production worthy materials such as spin-on carbon for hardmasks and e-beam resists. But we are now purely focused on the development and commercialization of our high-performance EUV resist, which is called Multi-Trigger Resist (MTR™) and represents a new class of resist material.

Our MTR platform has been designed from the ground up specifically for EUV lithography, and addresses the limitations of legacy resist materials. It is up to two times faster than competing resists, which has the potential to result in annual cost-of-ownership (CoO) savings of approximately US$10-15 million per EUV scanner operating in a production fab.

Our team is a multi-disciplinary team comprised of world-class technologists with significant industry experience and strong academic background in multiple disciplines, including chemical engineering, lithography, material science, and synthetic chemistry.

What is the vision and strategy for the company?

Our vision is to be the pre-eminent supplier of EUV resist materials to the semiconductor industry through the market adoption of our innovative MTR photoresist platform. Our strategy is to collaborate closely with our customers across the industry’s leading integrated device manufacturers (IDMs) and foundries and offer customized resist materials to address their unique needs. In addition, we intend to strengthen our existing partnerships with key players in the ecosystem while also establishing a set of new partnerships. We are also taking a solution-oriented approach to ensure that our resist material becomes a plug-play material within the overall EUV lithography process.

What problems are you solving?

We are addressing the unique challenges and requirements of EUV lithography (both low NA and High NA). Traditional photoresists like chemically amplified resists (CAR) and metal oxide resists (MOR) cannot fully meet the requirements for higher resolution, low defectivity, and improved throughput. The need for specialized EUV photoresists will only become greater as chip manufacturers push the limits of EUV lithography to further reduce the size of chip feature sizes. Specifically, we are developing novel formulations of our resist material that can meet the key requirements of absorbance, defectivity, etch resistance, line width roughness (LWR), resolution, and sensitivity. There are multiple tradeoffs that have to be made in order to balance all of these requirements in order to generate optimum resist formulation.

What application areas are your strongest?

Our EUV resist material is highly applicable across both logic and memory devices as well as patterned layers corresponding to FEOL and BEOL processes (lines & spaces, contact holes, pillars, etc.).

What does the competitive landscape look like and how do you differentiate?

Our main competitors are those offering CAR and MOR resists. Our MTR technology is a new approach that combines the best of both worlds with additional unique features, which has the potential to offer the highest levels of performance. It uses a catalytic mechanism based on a photoacid generator similar to a CAR and is an organic compound, which makes it compatible with existing track solutions. But unlike a CAR, it is a controlled catalytic reaction based on unique proprietary molecules, which significantly limits or eliminates the acid diffusion resulting in high sensitivity and low LWR. Similar to MOR, it is a small molecule with high opacity, which delivers high resolution. But unlike a MOR, it is non-metallic and avoids metal contamination issues in the fab. Above and beyond all of this, it is a faster resist compared to both CAR and MOR and therefore offers the potential for significant CoO savings in a production fab. Finally, it is PFAS/PFOS-free, which makes it very environmentally friendly.

What new features/technology are you working on?

Broadly speaking, there are two categories of features and capabilities we are working on. The first category is related to improved formulations that can meet the specific short-term needs of customers. Examples of these are higher resolution (tighter pitches), lower linewidth roughness (LWR), and minimizing defectivity.

The other category is related to developing brand new formulations that can address medium-term and long-term industry needs. Examples of these are better delay tolerance, improved process compatibility, and higher absorption/depth of focus (particularly for high-NA EUV).

How do customers normally engage with your company?

Customers will typically ask us to provide a resist sample for testing based on a set of target performance requirements (e.g., resolution, LWR, sensitivity), operating conditions (e.g., bake temperature, post exposure delay) and the target pattern (e.g., lines and spaces, contact holes, pillars). We will then come up with an appropriate custom formulation, which is aimed at meeting their target requirements and perform internal testing before delivering it to the customer. Based on their testing, the customer may ask us to tweak the formulation for further optimization of one or more parameters. Once the customer is satisfied that our formulation meets their key requirements, they will move on to the next phase of material qualification which can eventually lead to a specific material becoming selected as a process of record (POR) material in preparation for high volume manufacturing (HVM).

Contact Irresistible Materials

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March 12, 2025March 12, 2025

RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs

RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs
by Jonah McLeod on 03-12-2025 at 6:00 am
Categories: IP, RISC-V

Because of its open and modular nature, RISC-V has faced recognizable security challenges stemming from fragmentation, performance inefficiencies, and inherent vulnerabilities. Fragmentation across implementations leads to inconsistencies, making it difficult to enforce uniform security measures. Performance inefficiencies can introduce timing side-channel attacks, where attackers exploit execution time variations to extract sensitive data. Additionally, security vulnerabilities such as Jump-Oriented Programming (JOP) attacks and buffer overflow exploits have demonstrated RISC-V-based systems weaknesses. Addressing these risks has been a crucial focus in the ongoing development of the RISC-V Privileged Specification and supporting architectural innovations.

Recent Architectural Innovations

RISC-V’s privileged specification has faced challenges related to fragmentation, performance inefficiencies, and security vulnerabilities—factors that impact OS support, virtualization, and memory protection. However, recent progress in the RISC-V Privileged Specification has addressed many of these issues, bringing it closer to the robustness of proprietary ISAs like ARM and x86. In parallel, new architectural innovations are further strengthening RISC-V’s capabilities by introducing improvements in memory management, scheduling, and execution efficiency.

As of March 6, 2025, the RISC-V Privileged Architecture Specification version 1.13 has successfully completed its public review process and has been ratified. The 30-day public review period, which started on September 3, 2024, and concluded on October 1, 2024, allowed stakeholders to provide feedback and suggest improvements. Following this review, the specification underwent necessary revisions and was officially ratified. This ratification marks a significant milestone in addressing previous challenges related to fragmentation and security vulnerabilities within the RISC-V ecosystem. With a more stable foundation for operating system support, virtualization, and memory protection, the updated specification enhances RISC-V’s position in modern computing.

Connections Between v1.13 and Recent Patented Innovations

The RISC-V Privileged Architecture Specification v1.13 introduces refinements to privilege levels, memory protection, hypervisor support, and exception handling to strengthen security and performance. One of the most significant refinements in v1.13 is improvements to Hypervisor Mode (H-Mode), which enables more efficient virtual machine (VM) scheduling and reduces execution delays in privileged mode. A related patented innovation, Time-Based Scheduling for Extended Instructions, enhances this feature by optimizing how privileged instructions are scheduled, ultimately reducing context-switch latency. The direct connection between these two advancements is clear: while v1.13 provides the foundation for better hypervisor management; time-based scheduling ensures that hypervisor instructions execute more efficiently. A hypervisor running on a v1.13-compliant RISC-V processor would benefit from reduced instruction stalls and improved VM performance, allowing for smoother virtualization workloads.

Another area where v1.13 and recent innovations align is in memory protection. The specification expands Physical Memory Protection (PMP) and refines virtual memory management to improve access security. Together, these improvements ensure that while v1.13 enforces stricter security policies for memory access, load prediction ensures that privileged memory operations execute efficiently within those constraints. This is particularly important for real-time operating system (OS) environments and security-sensitive applications, where low-latency memory access is crucial to performance and stability.

Additionally, v1.13 introduces refinements to Machine Mode (M-Mode) and Supervisor Mode (S-Mode) execution, making privileged execution more predictable and structured. These updates align with another patented innovation, Out-of-Order Execution for Loop Instructions, which allows the CPU to process system-critical loops more efficiently. The v1.13 spec defines the rules for privileged execution, while out-of-order execution enhances performance within those guidelines. A v1.13-compliant OS kernel running on a CPU that implements out-of-order execution will experience faster privilege mode loops, reducing interrupt handling delays and improving overall system efficiency.

Enhancing RISC-V Performance with Architectural Innovations

Beyond the advancements in the privileged specification, recent patented innovations are further strengthening the RISC-V ecosystem. These enhancements improve memory efficiency, scheduling, and overall execution performance, providing the level of system protection currently enjoyed by proprietary ISA offerings. One such advancement is Time-Based Scheduling for Extended Instructions, which optimizes execution timing for complex privileged instructions. This mechanism ensures smoother operating system performance and reduces bottlenecks in system-level task execution. By lowering the latency in context switching between guest virtual machines, hypervisors can operate more efficiently, leading to better virtualization performance.

The RISC-V Privileged Specification defines a hierarchical privilege model that supports different execution environments. The figure below illustrates the layering of these privilege levels, including OS, SBI, and hypervisor support.

The introduction of Out-of-Order Execution for Loop Instructions has also significantly improved OS-level and hypervisor performance. This enhancement allows loop instructions to execute non-sequentially, making privileged task handling more efficient. Context switching and interrupt processing benefit greatly from this approach, as it minimizes execution stalls and increases hypervisor responsiveness.

Conclusion

By combining the ratification of the RISC-V Privileged Specification version 1.13 with architectural innovations in memory management and execution efficiency, RISC-V is making significant strides in overcoming past limitations. These advancements position it as a more competitive alternative to proprietary ISAs, paving the way for wider adoption in high-performance computing, cloud infrastructure, and secure enterprise environments.

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