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Democratizing the Ultimate Audio Experience

Democratizing the Ultimate Audio Experience
by Bernard Murphy on 06-08-2023 at 6:00 am

3D Audio

I enjoy talking with CEVA because they work on such interesting consumer products (among other product lines). My most recent discussion was with Seth Sternberg (Sensors and Audio software at CEVA), on spatial or 3D audio. The first steps to a somewhat immersive audio experience were stereo and surround sound, placing sound sources around the listener. A little better than mono audio, but your brain interprets the sound as coming from inside and fixed to your head, because it’s missing important cues like reverb, reflection, and timing differences at each ear. 3D audio recreates those cues, allowing the brain to feel the sound source is outside your head but still fixed to your head; move your head to the left and the band moves to the left, move to the right and the band moves to the right Connecting head movements to the audio corrects this last problem, fixing the sound source in place. When you move your head you hear a change in the same way you would in the real world. This might seem like a nice-to-have but it has major implications in user experience and in reducing fatigue induced by lesser implementations.

Why should we care?

Advances in this domain leverage large markets, especially in gaming (~$300B), which doesn’t just drive game sales. If you doubt gaming is important, remember that last year gaming led NVIDIA revenues and is still a major contributor. As a further indicator the headphones/earphones market is already above $34B and expected to grow to $126B by 2030. Apple and Android 13 provide proprietary spatial audio solutions for music and video services and are already attracting significant attention. According to one reviewer there are already thousands of Apple Music songs encoded for 3D. Samsung calls their equivalent 360 Audio, working with their Galaxy Buds Pro and content encoded for Dolby Atmos (also supported by Apple’s Spatial Audio). Differentiating on the user audio experience is a big deal.

The music option is interesting but I want to pay special attention to gaming. Given an appealing game, the more immersive the experience the more gamers will be drawn to that title. This depends in part on video action of course, but it also depends on audio well synchronized both in time and in player pose with the video. You want to know the difference between footsteps behind you or in front. When you turn your head to confirm, you expect the audio to track with your movement. If you look up at a helicopter flying overhead, the audio should track. Anything less will be unsatisfying.

Though you may not notice at first, poor synchronization in timing and pose can also become tiring. Your brain tries to make sense of what should be correlated visual and audible stimuli. If these don’t correspond, it must work harder to make them align. An immersive experience should enhance excitement, not fatigue, and game makers know it. Incidentally, long latencies and position mismatch between visual and audio stimuli are also thought to be a contributing factor in Zoom fatigue. Hearing aid wearers watch a speaker’s lips for clues to reinforce what they are hearing; they also report fatigue after extended conversation.

In other words, 3D audio is not a nice-to-have. Product makers who get this right will crush those who ignore the differentiation it offers.

To encode or not to encode

In the early days of surround sound, audio from multiple microphones was encoded in separate channels, ultimately decoded to separate speakers in your living room. Then “up-mixing” was introduced using cues from the audio to infer a reasonable assignment of source directions to support 5.1 or 7.1 surround sound. This turns out to be a pretty decent proxy for pre-encoding and certainly is much cheaper than re-recording and encoding original content in multiple channels. If there is more information like stereo, a true 5.1, 7.1 or ambisonics, 3D audio should start with that. Otherwise up-mixing provides a way for 3D audio to deliver a good facsimile of the real thing.

The second consideration is where to render the audio, on the phone/game station or in the headset. This is relevant to head tracking and latency. Detecting head movements obviously must happen in the headset but most commonly the audio rendering is handled in the phone/gaming device. Sending head movement information back from the headset to the renderer adds latency on top of rendering. This roundtrip over Bluetooth can add up to 200-400 milliseconds, a very noticeable delay between visual and audible streams. Apple has some proprietary tricks to work around this issue but these are locked into an Apple exclusive ecosystem.

The ideal and open solution is to do the audio rendering and motion detection in the headset for minimal total latency.

The RealSpace solution

In May of this year, CEVA acquired the VisiSonics spatial audio business. They have integrated this together with the CEVA MotionEngine software for dynamic head tracking, providing precisely the solution defined above. They also provide plugins for game developers who want to go all the way to delivering content fully optimized to 3D audio. The product is already integrated in chips from a couple of Chinese semis and a recently released line of hearables in India. Similar announcements are expected in other regions.

Very cool technology. You can read about the acquisition HERE, and learn more about the RealSpace product HERE.

Also Read:

DSP Innovation Promises to Boost Virtual RAN Efficiency

All-In-One Edge Surveillance Gains Traction

CEVA’s LE Audio/Auracast Solution


Nominations for Phil Kaufman Award, Phil Kaufman Hall of Fame Close June 30

Nominations for Phil Kaufman Award, Phil Kaufman Hall of Fame Close June 30
by Paul Cohen on 06-07-2023 at 10:00 am

PK Generic

Plan ahead now because Friday, June 30, is the deadline to submit nominations for the Phil Kaufman Award and the Phil Kaufman Hall of Fame for anyone you think is deserving of these honors. If you haven’t given it any thought, please consider nominating someone.

Before we look at both and the nomination requirements, here’s a thumbnail sketch of Phil Kaufman (1942-1992) and the reasons why we continue to honor his memory. Phil Kaufman was an industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. At the time of his death, he was president and CEO of Quickturn System, developer of hardware emulators. Quickturn’s products helped designers to speed the verification of complex designs. Previously, he headed Silicon Compiler Systems, an early provider of high-level EDA tools that enabled designers to efficiently develop chips.

The annual Phil Kaufman Award for Distinguished Contributions to Electronic System Design was first presented in 1994 to Dr. Herman Gummel (1923-2022) of Bell Labs (now Nokia Bell Labs). Since then, an impressive list of notables from across the spectrum of our ecosystem have received the award.

Sponsored by the Electronic System Design Alliance (ESD Alliance) and the IEEE Council on Electronic Design Automation (CEDA), it honors individuals who have made a visible and lasting impact on electronic design. Their influence could be as a C-level executive or someone setting industry direction or promoting the industry, a technologist or engineering leader or a professional in education and mentorship. Dr. Gummel, for example, was honored for his fundamental contributions to central EDA areas including the integral charge control model for bipolar junction transistors known as the Gummel-Poon model.

Per a policy set with the IEEE, only living contributors are eligible to receive awards. Thus, the Phil Kaufman Hall of Fame was introduced in 2021 by the ESD Alliance and the IEEE CEDA to honor deceased individuals who made significant and noteworthy creative, entrepreneurial and innovative contributions and helped our community’s growth. As Bob Smith, executive director of the ESD Alliance, said at the time: “Many contributors to our success died before being recognized for their efforts shaping our community. The Phil Kaufman Hall of Fame changes that.”

Our first recipients in 2021 were Jim Hogan (1951–2021) and Ed McCluskey (1929-2016). Jim Hogan was managing partner of Vista Ventures, LLC., and an experienced senior executive who worked in the semiconductor design and manufacturing industry for more than 40 years. Ed McCluskey, a professor at Stanford University, sustained a relentless pace of fundamental contributions for efficient and robust design, high-quality testing and reliable operation of digital systems. Mark Templeton (1958-2016) was the 2022 recipient. Artisan Components (now Arm), where he served as CEO, catalyzed the increasing use of IP as major components in chip designs. At the time of his death, he was managing director of investment firm Scientific Ventures, and a Lanza techVentures investment partner and board member.

How to Nominate
Selections for the Phil Kaufman Award and the Phil Kaufman Hall of Fame are determined through a nomination process reviewed by the ESD Alliance and IEEE CEDA Kaufman Award selection committees. To download a nomination form, go to: Phil Kaufman Award or Phil Kaufman Hall of Fame.

About the ESD Alliance
The ESD Alliance, a SEMI Technology Community, acts as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. With a variety of programs for member companies, it represents the electronic system and semiconductor design ecosystem for technical, marketing, economic and legislative issues affecting the entire industry.

Follow SEMI ESD Alliance

www.esd-alliance.org

ESD Alliance Bridging the Frontier blog

Twitter: @ESDAlliance

LinkedIn

Facebook

Also Read:

SEMI ESD Alliance CEO Outlook Sponsored by Keysight Promises Industry Perspectives, Insights

Cadence Hosts ESD Alliance Seminar on New Export Regulations Affecting EDA and SIP March 28

2022 Phil Kaufman Award Ceremony and Banquet Honoring Dr. Giovanni De Micheli


Applied Materials Announces “EPIC” Development Center

Applied Materials Announces “EPIC” Development Center
by Scotten Jones on 06-07-2023 at 8:00 am

Applied Materials EPIC briefing under embargo Page 10

On May 22nd Applied Materials announced a new development center, Equipment and Process Innovation and Commercialization Center (EPIC).

Applied Materials already operates the Maydan Technology Center (MTC), a billion-dollar development facility with over 120 advanced process tools and 80 metrology and inspection tools located in Santa Clara, California. Applied Materials also has the Material Engineering Technology Accelerator (META) for materials research and innovation located at Albany Nanotech in Albany New York. For META Applied materials buys capacity at the Albany Nanotech fab and has their own space.

All of this leads to the question of why build a new development center and what is unique about EPIC.

The key differentiator around EPIC is the focus on collaboration.

“Goal is to change the way equipment companies work with chipmaker, universities and other partners to optimize time to market, R&D cost and overall success rate. Potentially 30% faster than current baseline”

Currently between university foundational research, equipment company equipment and process development, and chipmaker module/integration, pilot and introduction to high volume manufacturing a new process can take 10 to 16 years, see figure 1.

Figure 1. Current Development Path.

Foundational research for new technologies takes place at universities and Applied Materials has identified this as a key bottleneck. EPIC will provide universities with access to state-of-the-art hardware and labs to accelerate this work. There will be space available at EPIC for universities and Applied Materials is also going to establish collaborative labs at universities where they will run/maintain equipment as an extension of this lab.

Another key bottleneck is the transfer of new processes and hardware from equipment companies to chipmakers.

By overlapping foundational research with equipment and process development, and overlapping equipment and process development with module/integration by the chipmaker the overall development process can be 30% faster, see figure 2.

Figure 2. Accelerated Development Path.

The new EPIC center will provide 180,000 square feet of cleanroom and supporting space to Applied Materials, Customers, Universities, and Partners with operations due to begin in Q1 of 2026, see figure 3.

Figure 3. EPIC Facility.

The EPIC center will have a common tool set of state-of-the-art tools, dedicated private customer space, partners/peers and universities/star ups space as well as private space for Applied Materials, see figure 4.

Figure 4. EPIC Center Implementation.

Applied Materials will invest up to $4 billion dollars over the next 7 years to establish the center. There will also be 5 to 7 satellite labs with 2 up and running and 4 more in the discussion phase.

By locating EPIC in Silicon Valley Applied Materials be in close proximity to the leading technology companies with $10 trillion dollars of market capitalization located within a 50-mile radius. There are also nearby world class universities.

The new EPIC center represents a large investment in rearchitecting how new semiconductor processes are developed to accelerate new developments and the semiconductor roadmap.

Also Read:

SPIE 2023 – imec Preparing for High-NA EUV

TSMC has spent a lot more money on 300mm than you think

SPIE Advanced Lithography Conference 2023 – AMAT Sculpta® Announcement

IEDM 2023 – 2D Materials – Intel and TSMC

 


PCI-SIG DevCon and Where Samtec Fits

PCI-SIG DevCon and Where Samtec Fits
by Mike Gianfagna on 06-07-2023 at 6:00 am

PCI SIG DevCon and Where Samtec Fits

PCIe (peripheral component interconnect express) is an interface standard for connecting high-speed components contained in PCs, MACs and other types of processors. Think graphics, storage arrays, Wi-Fi and the like. This communication standard has become incredibly popular. The first version of the standard was released in 2004 by Intel. Like many parts of computing architectures, newer generations delivered ever faster and more efficient performance. Gen 7 of the standard is currently in development. There is a key conference coming up on June 13 for all things PCIe. Just like DesignCON and MemCON, Samtec will be a force at this event. Read on to learn about PCIe, the PCI-SIG DevCon and where Samtec fits.

PCIe – Where Samtec Fits

Any communication standard requires hardware and software to implement the communication protocol, electronics to drive the communication channel and an interface to the communication channel and the physical medium. These last two parts are critical to completing the channel, and this is where Samtec provides a variety of solutions to get the job done.

Both the electrical and mechanical parts of the specification must be adhered to if the interface is to be robust and reliable. Samtec offers both connector and cable solutions that meet PCI Express® electrical and mechanical specifications. The high-level summary includes:

  • High-speed edge card sockets that support one, four, eight and sixteen PCI Express links and mate with PCI Express cable assemblies
  • PCI Express-Over-FireFly™ copper and optical cable assemblies for low latency, power savings and guaranteed transmission
  • An optical adaptor card is available with PCIe x16 edge card connector

For increased design flexibility, additional solutions are available that meet PCI Express electrical specifications with potential cost savings, including mezzanine board-to-board solutions and signal/power routing flexibility.

PCI-SIG DevCon – Where Samtec Fits

First, the vital stats for this important event:

PCI-SIG Developers Conference 2023

June 13-14

Santa Clara Convention Center

​Santa Clara, CA

You can register for the conference here. If you are developing any kind of computing device, PCIe is very likely to be part of the architecture, so this is key show to attend. What makes it even more compelling is registration is free if your company is involved in the standard, and over 900 companies are. Samtec is a Platinum Sponsor for the event. Here are some of the ways they are supporting the technical sessions:

Samtec and its partners will be participating in two technical sessions. Resident PCI Express technology expert Steve Krooswyk will detail exceptions of excursion compliance in cables and connectors. 

Martin Stumpf Rohde & Schwarz will detail the challenge of PCIe 5.0/PCIe 6.0 compliance in interconnect. He will discuss the partnership between Samtec, Rohde & Schwarz and Allion Labs.

The details for these two presentations are as follows:

Cable and Connector Compliance with Integrated Return Loss

Steve Krooswyk – Tuesday, June 13 | 3:30 PM – 4:30 PM PT

Upcoming PCIe 5.0 and 6.0 Cable and 6.0 CEM specifications are considering Integrated Return Loss (IRL) for excursion compliance.  Excursions may occur as compliance further reduces noise requirements and suppliers optimize high volume manufacturing practices.  Excursions up to a limit have minimal system impact.  IRL is not new, it’s history and process are reviewed, followed by simulation and measurement examples.

Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0

Martin Stumpf – Wednesday, June 14 | 9:00 AM – 10:0 AM PT

With 32 GT/s in PCIe 5.0 and 64 GT/s in PCIe 6.0, channel characteristics like loss, reflections and crosstalk are increasingly critical for the overall system performance. We will discuss performance requirements and implementations of PCIe 5.0 / 6.0 connectors and cable assemblies and the corresponding test setups and measurement methods to characterize and verify these interconnects. New metrics of ICN and IRL are included, as well as the related measurements. 

As the PCIe specifications define the performance requirements without the test fixtures, optimized test fixture design and accurate test fixture modelling and de-embedding is key for good measurement results. We will preview modern de-embedding techniques with accurate impedance modelling of lead-ins and lead-outs.

To Learn More

Register for this event now, you won’t want to miss it. And check out Samtec’s PCI Express® Interconnect Solutions brochure to learn more about how to a bring PCIe implementation to life. And that’s the story of PCI-SIG DevCon and where Samtec fits.

 

 

 

 

 


TSMC Clarified CAPEX and Revenue for 2023!

TSMC Clarified CAPEX and Revenue for 2023!
by Daniel Nenni on 06-06-2023 at 2:00 pm

TSMC HQ Taiwan

TSMC clarified CAPEX and revenue for 2023 last night at the Annual Shareholders Meeting. Last year TSMC guided up during this meeting but this year they guided down. CAPEX was guided down to the lower end of $36B-$32B.  Revenue was guided down from low-single to mid-single digit so maybe down another percent or two. The TSMC Jan – May 2023 revenue report indicates a decrease of 1.9 percent compared to the same period in 2022 so I think TSMC is being very conservative here.

Other foundries may not be as fortunate. Globalfoundries is already -5% in Q1 and UMC is -17% Jan-May 2023. In contrast TSMC started the year strong with +16% in January and +11% in February. Things turned bad in March with -15% and April -14%. At the TSMC Symposium CC Wei joked about his horrible forecasting but coming off the strongest year in the history of TSMC it was not a surprise.

“The year 2022 was a landmark year for TSMC. Supported by our strong technology leadership and differentiation, we delivered a thirteenth-consecutive year of record revenue, with strong profitable growth. Our 2022 annual revenue increased 33.5% year-over-year in U.S. dollar terms, while our EPS rose to NT$39.20, nearly tripling over the past three years.”

A landmark year indeed. TSMC manufactured 12,698 products for 532 customers in 2022. Hopefully we can all recognize this incredible achievement. Unfortunately, 2023 will also be a landmark year for a YoY decline and the pandemic is still to blame.

TSMC predicts that the second half of 2023 will improve so we may be at the bottom. 2024 also looks very promising but of course it is too soon to tell. According to the  World Semiconductor Trade Statistics, the global semiconductor industry is forecasted to grow 11.8% to $576B in 2024 with a major rebound expected in the memory segment, a surge of about 40% from last year.

The other news from the meeting echoed the Symposium which is good news:

 “In Taiwan, our N3 has just entered volume production in Tainan Science Park. We are also preparing for N2 volume production starting in 2025, which will be located in Hsinchu and Taichung Science Parks. In the U.S., we are in the process of building two advanced semiconductor fabs in Arizona, with N4 and N3 process technology, respectively. We are also building a 12-inch specialty technology fab in Kumamoto, Japan.”

TSMC was crystal clear in the reasoning for building fabs around the world. TSMC’s business model has always been customer centric and customers want fabs near their customers. This customer demand is not just for semiconductor manufacturing, other manufacturing is localizing as well, and again it is a direct result of the pandemic which broke supply chains around the world.

“N2 technology development is on track, with risk production scheduled in 2024 and volume production in 2025. Our 2-nanometer technology will be the most advanced semiconductor technology in the industry in both density and energy efficiency when it is introduced.”

Interesting wording here and I do agree N2 will be denser and more power efficient than Intel 20A or Samsung 3nm. I would also add more cost effective as no one in the foundry business has the economies of scale to match TSMC.

One thing you have to remember is that when TSMC says volume N2 production in 2025 that means Apple which is a multi-billion transistor SoC shipped by the millions. TSMC is not talking about internal product, engineering samples or chiplets. The mainstream media misses this point every time. Either they are ignorant or they are intentionally besmirching TSMC to get clicks. Either way it is unethical, my opinion.

“To help customers unleash their product innovations with fast time-to-market, TSMC provides customers with comprehensive infrastructure needed to optimize design productivity and cycle times. TSMC continues to expand our Open Innovation Platform® (OIP), providing over 55,000 items of libraries and silicon IP portfolio, more than 43,000 technology files, and over 2,900 process design kits, from 0.5-micron to 3-nanometer in 2022.”

As most people know I have been part of this ecosystem since it started so I know it better than most. The one thing that I would add here is that with the overwhelming success of TSMC N3, the ecosystem has never been stronger for TSMC so there is significant momentum for the N2 transition, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5


Arm 2023 Mobile Solutions Continue Gaming Focus

Arm 2023 Mobile Solutions Continue Gaming Focus
by Bernard Murphy on 06-06-2023 at 6:00 am

TCS23

Arm recently announced an update for mobile under the Arm Total Compute Solutions (TCS) label, led by Chris Bergey (Sr. VP/GM for the Client line of business). You’ll remember that Chris headed the infrastructure line of business impressively through the Neoverse brand, as demonstrated by Arm-based servers appearing in multiple hyperscalars and penetration in multiple wireless infrastructure platforms. Now we get to see what he can do with mobile.

How do you grow in a saturated market?

That’s the challenge for Arm. The engine that boosted them to fame and fortune, the smartphone business, now sees declining unit shipments and projections for revenue growth anywhere between 2.5% and 7% CAGR depending on who you believe. The spread reflecting, I’m sure, uncertainty in what might stick among future product features.

Arm sees mobile gaming as an important TAM growth driver, consistent with their view last year. They commissioned a report a couple of years ago showing that mobile gaming is by far the most popular platform for gaming worldwide. Given that gaming is even now a significant contributor to NVIDIA revenue, I can believe mobile gaming presents an opportunity for Arm.

Arguably today the mobile gaming trend is strongest in China where consumers are very active in online multi-player games. Chris sees folding phones accelerating the trend as these offer a larger screen size. I also remember that at least last year the majority of phones in China were still on 3G. I expect need to upgrade to 4G/5G would also push growth, especially for Chinese phone suppliers (Xioami, Oppo, Vivo, etc). RISC-V could in theory compete for CPU slots, but without a top-of-the-line GPU offering and NVIDIA blocking RISC-V support for their GPUs that threat seems limited for now.

Gaming is also popular outside China mostly in puzzle-oriented games rather than hard-core player-competition titles. Arm sees this changing already in Korea and expects growth in the West as content adapts and as larger screen options (especially foldables) become more popular. Seems reasonable – we’re already starting to see Galaxy-S23 commercials in the US for competitive gaming; the seed is being planted 😊. Arm’s point here is that mobile competitive gaming demands a high level of performance in a smartphone, in CPUs and GPUs, features that will only be possible in premium models.

What’s new in TCS23?

There are 4 new cores covered under the announcement. Given the gaming focus of this release, Chris led with the new Immortalis G720 GPU, developed in partnership with MediaTek. Arm have upgraded the graphics pipeline to support the more complex real-time 3D imaging already standard on console and PC applications. This comes with a 15% uplift in performance and efficiency and a boost in system-level efficiency. They also introduced Mali-G720 and Mali-G620, presumably targeted to entry-level gaming handsets.

Next up is the Armv9 Cortex CPU compute cluster, starting with the Cortex-X4, delivering 15% more performance than Cortex-X3 at 40% less power and expected to serve AI/ML applications. There are new big and LITTLE cores – Cortex-A720 for “big” and Cortex-A520 for “LITTLE”, both delivering 20% power efficiency improvements over earlier generations. There is also a DSU update. Chris notes that there is now a tighter coupling between process nodes and these performance metrics, enabled by close collaboration with TSMC. That may account for these cores being 20% more area efficient than the nearest competitor, per Chris.

All of these cores are now 64-bit and complemented by Arm Memory Tagging Extension (MTE) to eliminate memory safety bugs. 70% of security issues detected in Microsoft products and 75% of vulnerabilities detected by Google in Android have been attributed to memory safety problems, leading Google to adopt MTE for Android. Nice – I’m impressed by the work Arm is putting into security, here and in the Cheri collaboration.

Deployment

The platform is built into the MediaTek Dimensity 9200, which in turn is inside top of the line phones from Oppo and Vivo and is already delivering results in games from Genshin Impact to Fortnite. Chris didn’t want to share more details but seems optimistic that more deployments will be announced.

In summary, growing in a saturated market will be an uphill climb, but Arm seems to know how it wants to get there and continues to work on ensuring it will stay on top of the game through continued technology advances. You can read the press release HERE.


Automotive IP Certification

Automotive IP Certification
by Daniel Payne on 06-05-2023 at 10:00 am

SLM min

The electrification of cars and the growth of EVs means that more semiconductor content is being added with every new vehicle model from suppliers around the globe. There are unique concerns for automotive IP in terms of reliability, security and safety over the lifetime of the vehicle. I had the pleasure to speak with Pawini Mahajan, Head of Product for Silicon Automotive Solutions at Synopsys over a Zoom call this month to hear what they see happening in the industry.

Automotive OEM Challenges

I was surprised to learn that it can take 8 years to go from concept to showroom floor for a new model of car, while remodels are completed in a much shorter time span. New entrants like Tesla are certainly challenging the status quo for the speed of development and adding features. Chip shortages have plagued new car delivers over the past 2 years, as supply chains became disrupted. Zonal architectures are being used to place electronics in clusters, and ADAS features automate more of the driving for us as Level 3+ emerges. Our phones have frequent Over The Air (OTA) updates, and that trend continues in automotive as the idea of a Software Defined Vehicle (SDV) grows more popular. Hackers are active in efforts to break into auto systems, making security a new burden.

With added automotive IP there are concerns about the lifespan of semiconductor components as issues like electromigration can cause early failures. Increased temperatures actual speed up the aging process in chips. Even the constant vibration present in automotive vehicles adds to mechanically induced failures in wire bonding or even die fracturing. The current flow across transistor channels degrades the Vt and mobility values over time, another aging effect.

Larger chips fabricated at smaller nodes used in automotive IP are prone to analog circuit failures, per the bi-annual Wilson Research Group survey. It’s projected that by 2030 the percentage of total car cost will be 50% attributed to electronics, while in 2010 it was 33%.

Silicon Health Monitoring

The idea to meet these challenges of safety, security and reliability is to have monitoring inside of each chip to measure what’s going on and be able to predict a failure before it occurs. At Synopsys they use the phrase Silicon Lifecycle Management (SLM) to encompass the sequence of monitoring, gathering data, analyzing then acting on the analysis.

Silicon Lifecycle Management

The functional safety for hardware is defined in ISO 26262-5, and there’s a classic “Bathtub Curve” showing the failure rate of electronics as a function of time.

Bathtub Curve

Automotive grade requirements to reduce risks and quicken qualification for automotive SoCs are to follow the ISO 26262 functional safety assessments, meet the reliability standards of AEC-Q100, and pass the quality checks from ISO9001 and ITAF 16949.

PVT IP

Synopsys acquired Moortec back in 2020, adding on-chip IP for Process, Voltage and Temperature (PVT) monitoring. The processor detector measures speed of the silicon, the voltage monitor detects IR drop, and the thermal sensors reveal the precise temperature across multiple locations on the die. Synopsys has included these PVT IP blocks on several popular process nodes, including the N7A node from TSMC for silicon validation, and they are qualified to AECQ-100 Grade 2.

Automotive-specific documents are delivered with this PVT IP from Design FMEA to an ISO 26262 assessment report.

Systematic failures are caused during the design, development and manufacturing while specifying or implementing, and random hardware failures show up from random defects or aging effects. ISOS 26262 covers both systematic and random hardware faults. There are four Automotive Safety Integrity Levels (ASIL):

ASIL

The strictest ASIL-D requires that components have <1% single points of failure, and <10% latent faults.

For reliability standards of SoCs the AEC-Q100 specifies stress testing of automotive ICs across various temperature ranges, and this corresponds to a number of hours testing at a high temperature for electromigration reliability.

AEC-Q100 Grades

IP at Synopsys is characterized under three product classes:

  • Automotive Grade (AG), used for hard-IP only, automotive reliability but no functional safety work products
  • ASIL Random (AP), ISO 26262 Random Hardware Fault Metrics only
  • ASIL Compliant (AC), ISO 26262 full compliancy Systematic + Random

Summary

As an automotive driver and passenger I really want my trips to be safe, secure and reliable. The automotive industry has the same goals and has established working groups and standards over many years now. EDA and IP vendors like Synopsys have served the automotive segment well by creating the SLM applied to automotive IP certification.

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WEBINAR: UCIe PHY Modeling and Simulation with XMODEL

WEBINAR: UCIe PHY Modeling and Simulation with XMODEL
by Daniel Nenni on 06-05-2023 at 6:00 am

UCIe image2

Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog, using Scientific Analog’s XMODEL.

WEBINAR: UCIe PHY Modeling and Simulation with XMODEL
DATE: June 29, 2023
TIME: 14:00-15:30 Pacific Time

Registration Link 

Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog, using Scientific Analog’s XMODEL.

This webinar is organized in two parts. The first part gives a brief overview of the UCIe standard and explains why XMODEL is the best way to model and verify UCIe PHY, especially considering the close interactions between its electrical layer and logical layer. It will show how to model various analog circuits in the electrical layer, including the phase-locked loop (PLL), delay-locked loop (DLL), duty-cycle corrector, phase interpolator, and transmitter / receiver circuits. Each circuit block is modeled using XMODEL primitives, which enable fast and accurate simulation of their analog behaviors in SystemVerilog.

The second part shows how you can design the finite-state machines (FSMs) in the logical layer, performing digital training and calibrations on the reference voltage levels, clock-to-data timing, lane-to-lane skews, and link data rate via a series of data transmission tests with pseudo-random bit sequences. All the FSMs are described in SystemVerilog, and with XMODEL, you can simulate this logical layer model interacting with the electrical layer model entirely in SystemVerilog. It implies that you can also use various features of SystemVerilog to check the thoroughness of your simulation, such as checking the FSM state coverage.

This webinar will be beneficial to everyone who is interested in the design and verification of UCIe PHY. For analog circuit designers, the presented models will help understand the requirements posed on each circuit block, such as the scaling of bandwidth to support a wide range of data rates from 4GT/s to 32GT/s. For digital verification engineers, the presented testbenches will show how to perform SystemVerilog-based verification on the systems containing analog circuits. And most importantly, by running the simulations with the provided models, you can gain a hands-on understanding on how the various components of a UCIe PHY work to realize a high-bandwidth interconnect between chiplets.

Registration Link 

Speaker’s Bio:

Jaeha Kim is CEO and founder of Scientific Analog, Inc., Palo Alto, CA and Professor at Seoul National University (SNU), Seoul, Korea. With a flagship product called XMODEL, he is pursuing ways to make analog design and verification as efficient as digital. Dr. Kim received the B.S. degree from SNU in 1997, and the M.S. and Ph.D. degrees from Stanford University in 1999 and 2003, respectively. Prior to joining SNU, Dr. Kim was with Stanford University as Acting Assistant Professor and with Rambus, Inc. as Principal Engineer. Prof. Kim is a recipient of the Takuo Sugano award for Outstanding Far-East Paper at 2005 ISSCC and is cited as Top 100 Technology Leader of Korea by the National Academy of Engineering of Korea in 2020.

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Podcast EP165: The Impact of Mobiveil Across the Industry with Ravi Thummarukudy

Podcast EP165: The Impact of Mobiveil Across the Industry with Ravi Thummarukudy
by Daniel Nenni on 06-02-2023 at 10:00 am

Dan is joined by Ravi Thummarukudy. Ravi is CEO of Mobiveil, a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services with designs deployed in millions of units of silicon embedded in communications and consumer products worldwide.

Dan explores the silicon IP products, platforms and design services offered by Mobiveil with Ravi. It turns out the company is involved in a broad range of product development services and its IP unlocks many markets for its customers. Ravi explores the trends in the industry and the impact Mobiveil is having across a wide range of markets and applications.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


A Primer on EUV Lithography

A Primer on EUV Lithography
by Fred Chen on 06-02-2023 at 6:00 am

Litho historical trend Fig 1

Extreme ultraviolet (EUV) lithography systems are the most advanced lithography systems in use today. This article is a basic primer on this important yet complex technology.

The Goal: A Smaller Wavelength

The introduction of 13.5 nm wavelength continues a trend the semiconductor industry had been following a wavelength reduction since the use of blue light (436 nm “g-line” wavelength) for feature sizes >1 micron. The light is projected through a mask (or “reticle”) which has the circuit pattern printed on it. The transmitted image is then demagnified when finally projected onto the wafer. The minimum pitch is half the wavelength divided by the numerical aperture (NA) of the system. The NA of an optical system is a dimensionless number that indicates the range of angles over which the final lens can focus light. Wavelength reduction is not trivial, as it means the energy of the photons is increased in inverse proportion. Consequently, there is high absorption in all materials. Thus, all-reflective off-axis optical systems are needed. This has led to the development of so-called “ring-field” projection systems, which lead to rotating the illumination across the exposure field [1]. Pre-EUV optical systems could rely on on-axis transmissive optics, which simplified the illumination setup by having no rotation.

A Different Mask

The use of the EUV wavelength also led to an overhaul of the mask structure. The mask is also a reflecting element. The reflection is achieved with a multilayer consisting of at least 40 molybdenum/silicon bilayers. The mask pattern uses an absorbing layer, currently based on tantalum, which is several wavelengths thick. With the off-axis illumination scattering through the absorber pattern and propagating and reflecting through the multilayer, 3D effects are inevitable in affecting the final image on the wafer [2].

The mask is also protected by a thin membrane called the pellicle, which stands off a certain distance from the mask surface. Developing a pellicle for EUV was a big deal, as light has to pass through it twice as a non-reflecting transmitting element.

Changing the Numerical Aperture

The numerical aperture in current EUV systems is 0.33. In a future generation of EUV systems, the numerical aperture will be increased to 0.55. This is expected to enable 0.6x smaller feature sizes, from the wavelength/NA proportionality. However, the depth of focus is expected to suffer by being reduced faster than the resolution, as it is roughly proportional to wavelength/(NA)^2 (Figure 1) [3]. For 0.55 NA EUV, this has led to concerns with the use of resist (the absorbing image layer on the wafer) as thin as 20 nm [4].

Figure 1. Historical trend of depth of focus vs minimum pitch [3].
A 0.55 NA system has additional complications. First, it is a half-field system, which means two mask scans are needed to fill the same area as a single mask scan in an earlier system [5]. Secondly, there is a central obscuration projected by the last two optical elements. This constrains the illumination as well as certain combinations of pitches [6]. Finally, polarization becomes important for pitches which may make use of 0.55 NA [7].

The obscuration is the fundamental systematic difference that affects projected scaling from the current 0.33 NA systems. There will be light loss just before reaching the final focusing element. In addition, the image quality will be fundamentally changed. Key components of the image diffraction spectrum. Figure 2 shows a 68 nm pitch bright line under illumination tailored for 28 nm pitch. The appearance is normal without obscuration, but with the obscuration in place, the central peak is diminished and the sidelobes beside it are enhanced, since the first diffraction order is removed. These sidelobes can print stochastically [8].

Figure 2. (Left) 68 nm pitch line under 28 nm pitch illumination, with vs. without obscuration. (Right) Stochastic sidelobe printing (top view) for the obscured case (40 mJ/cm2 absorbed) [8].

It’s Not Only the EUV Light…

EUV lithography is unfortunately plagued by a number of factors which are not obvious from the classical optical treatment so far considered. The EUV light is a form of ionizing radiation, meaning it releases electrons in the resist upon absorption. The photoelectrons (~80 eV) are from the direct ionization, and the secondary electrons are from the ionization caused by these and subsequently released electrons. The energy deposited by the electron scattering will obviously heat the resist, leading to outgassing, which will contaminate the optical elements in the EUV system. For this reason, EUV systems now contain a minimally absorbing hydrogen ambient that will keep the surfaces of the optical elements clean without oxidizing them. However, hydrogen has been known to also cause blistering [9].

Figure 3. Electron release processes following EUV photon absorption in the resist.

The electrons also spread out from the original photon absorption site, leading to the originally defined image being blurred. The effects of this blur are easily felt several nanometers away. Aggravating the spreading effect further is the inherent randomness of the entire chain of events.

EUV Reveals the Stochastic Nature of Lithography

Photon absorption and electron scattering are all inherently random events. These lead to CD non-uniformity and edge roughness, and even placement errors and serious defects. Stochastic effects are more serious with lower absorbed photon density. Thinner resists reduce absorption, enhancing this effect. However, increased photon density leads to increased electron number density and increased electron blur, whose randomness leads to stochastic defects [10]. DUV lithography had not dealt with stochastic issues mainly because the feature sizes were large enough to secure enough photons, but EUV could not exploit this benefit.

References
  1. Antoni et al., Proc. SPIE 4146, 25 (2000).
  2. Tanabe, Proc. SPIE 11854, 1185416 (2021).
  3. J. Lin, J. Micro/Nanolith., MEMS, and MOEMS 1, (2002).
  4. https://www.imec-int.com/en/articles/high-na-euvl-next-major-step-lithography
  5. Davydova et al., Proc. SPIE 12494, 124940Q (2023).
  6. https://www.youtube.com/watch?v=1HV2UYABh4E
  7. https://www.youtube.com/watch?v=agMx-nuL_Qg
  8. https://www.youtube.com/watch?v=sb46abCx5ZY
  9. https://www.youtube.com/watch?v=FZxzwhBR5Bk&t=3s
  10. https://www.linkedin.com/pulse/secondary-electron-blur-randomness-origin-euv-stochastic-chen

Also Read:

SPIE 2023 – imec Preparing for High-NA EUV

Curvilinear Mask Patterning for Maximizing Lithography Capability

Reality Checks for High-NA EUV for 1.x nm Nodes