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Podcast EP172: RISC-V International, Today and Tomorrow with Calista Redmond

Podcast EP172: RISC-V International, Today and Tomorrow with Calista Redmond
by Daniel Nenni on 07-14-2023 at 10:00 am

Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry.

Dan explores the momentum RISC-V International has achieved in the market with Calista. Current developments to facilitate the standard are discussed, along with the impact of key strategic relationships. Calista reviews the organization’s significant presence at DAC, as well as substantial events elsewhere around the world.

Calista clarifies the question of whether RISC-V is open source or an open standard. She also discusses what lies ahead.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interview: Rob Gwynne of QPT

CEO Interview: Rob Gwynne of QPT
by Daniel Nenni on 07-14-2023 at 6:00 am

Rob Gwynne

I am joined today by Rob Gwynne, Founder and CEO of QPT. He is a genuine polymath as his technical experience spans digital, analogue, mixed signal and RF electronics, EMC, radar, DSP, FPGA, software development (embedded, drivers, application level), advanced PCB layout and simulation, optics, precision instrumentation, motion control, power systems and plasma physics!

Rob, I read on your website that you are going to change the world of electric motors for the better and help the planet. How are you going to do that?

Cutting the use of fossil fuels is vital to fight climate change. We are a clean tech company dedicated to improving electrical efficiency. We have focused on electrical motors as they consume 45% of the world’s energy according to the International Energy Agency (Energy-Efficiency Policy Opportunities for Electric Motor-Driven Systems). The trouble is that, rather like a car engine is tuned for efficiency in the middle speed range being an average of usage conditions, motor drives are also fine-tuned. However, this sweet spot is at maximum load and electric motor VFD (Variable Frequency Drive) manufacturers quote circa 97% efficiency. The efficiency actually drops off by up to 50% as the load decreases so, in real world condition where the load can vary considerably, there is a lot of power being wasted because the motor drive is not operating efficiently.

So, it is rather like the difference between the fuel consumption of a car running at a steady 50 MPH which is optimal for the engine and a car running a real world, urban cycle of different speeds and starts and stops?

Exactly. It is never questioned that 97% efficiency figure does not apply in lower load conditions. Not only have we found that it drops significantly but we have also found and patented a solution. Excitingly this enables electric motor drives to deliver 99.5% efficiency at full load range but, more importantly, the efficiency at lower loads is significantly higher than any current solutions.

That could have a phenomenal effect in reducing power usage if widely adopted. Why has this not been investigated before and what are the causes of the inefficiencies?

The controls for electric motors have hardly changed for many years. If you believe that you have achieved 97% efficiency, why would power engineers waste time and money trying to improve near perfection?

The inefficacies arise when the voltage is chopped to create the changing in frequency that is used to drive the motor. This is called a Variable Frequency Drive (VFD). Traditionally, normal silicon or Silicon Carbide (SiC) transistors are used but these are slow to switch resulting in high, switching energy losses.

The key to the losses is that Si and SiC transistors have body diodes that need to be charged and discharged on every switching cycle of the power converter, wasting energy on every cycle which is why there is low efficiency of these converters at low output power. Try and drive them faster and these losses become greater.  This, together with the switching loss due to slow switching, forces engineers using Si and SiC transistors to run the converters at low frequency as the charging/discharging losses become unacceptable at higher frequencies.

People have tried to use Gallium Nitride (GaN) transistors at MHz switching speeds compared to the usual 10-100 KHz to try and create smaller, more efficient and reliable drives. But, at these much higher frequencies, RF emissions become a problem and the designs would not pass EMI compliance testing unless you throttle back the speed which negates the benefits of using GaN.

So how do you solve that?

That’s where my broad skill set comes into play. Power engineers are focused on being an expert in one field and have developed skills and design approaches that work at 10-100Khz switching which is where Si and SiC transistors operate. However, I was also able to look at the problem as an RF engineer and create a solution that enables the GaN transistors to be run at their full potential of up 20 MHz with nanosecond switching with no heat or EMI issues.

As a result, our VFD module enables motors to be driven at up to 99.7% efficiency at peak load and to save significant power at lower loads compared to existing solutions. In real world operating conditions with variable loads, we estimated that this could provide savings in power consumption of 10% or more compared to current products. This comes from the faster switching speeds of GaN transistors and that they do not have the body diodes inherent in Si and SiC transistors that are a major energy loss as they charge and discharge.

I have done a number of videos that go into all the different aspects of this technology that are available on the website www.q-p-t.com

Do you have products?

Yes, we have modules available for evaluation. They form a drop-in replacement for existing 20 KW motor control modules. These are used in so many industries such as heat pumps, industrial motors and electric vehicles. Widespread adoption of our technology by them could significantly reduce energy costs and CO2 production and its impact on climate change. This will be helped by there not being any significant difference in the cost of using our technology over the existing, plus we provide up to 10% reduction in energy running costs! I passionately believe that this is an effective way to reduce climate change.

Also Read:

Defacto Celebrates 20th Anniversary @ DAC 2023!

Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges

CEO Interview: Dr. Sean Wei of Easy-Logic


400 GbE SmartNIC IP sets up FPGA-based traffic management

400 GbE SmartNIC IP sets up FPGA-based traffic management
by Don Dingee on 07-13-2023 at 10:00 am

Achronix ANIC

Sustaining wire-speed 400 GbE transfers is only a first step in managing enterprise traffic. Adding rules-based filtering to sift packets in real time can stress most networking hardware to a breaking point, slowing down an entire network. Architects are trying to spread these loads, distributing intelligent traffic management away from high-end firewalls and other appliances toward endpoints where traffic originates – but 400 GbE hardware with an integrated rules engine hasn’t scaled down easily. Achronix has a solution building on its Speedster7t FPGA integrating a 400 GbE packet interface, PCIe Gen 5, a flow processor with a rules engine, and room left for customer logic to differentiate 400 GbE SmartNIC designs.

All the pieces needed for a 400 GbE SmartNIC in one FPGA

Transceivers capable of 400 GbE are popping up on more than one high-end FPGA. But the problem of creating suitable “plumbing” in an FPGA for 400 GbE is often left as an exercise for the reader. Two projects within Achronix, with help from its acquisition of Accolade IP and expertise in September 2022, have thought through the entire IP chain and are coming together for a complete solution under the Achronix Network Infrastructure Code (ANIC) banner.

“We don’t think anyone has 400 GbE with this type of flow processing and rules engine for an endpoint right now,” says Scott Schweitzer, CISSP, Director of SmartNIC Product Planning at Achronix. It starts with enabling technology – the ANIC Shell, an Ethernet packet-flow pipeline in RTL. This project dates back to 100 GbE and PCIe Gen 3 technology, concentrating on FIFOs, parsing, and DMA elements needed to keep packets moving smoothly. In a Speedster 7t, over half of the logic remains available for customers.

 

 

Next came moving from the shell to the complete ANIC for a 400 GbE SmartNIC with the flow processor and rules engine, still with around 50% of the Speedster7t logic left.

 

 

Bumping ANIC up to 400 GbE might look easy from this diagram, but Schweitzer points out two points in the chain needing specific attention. “To get to a host at 400 Gb, we needed every bit of PCIe performance we could get – 16 lanes of PCIe 5 keeps the DMA engine fed,” says Schweitzer. “We also needed faster memory for the DMA and FIFO, and four channels of GDDR6 on each side got us there.

Visualized in the Speedster7t footprint, the ANIC looks like this. Note these are all optimized IP blocks with verified closed timing at speed.

 

Opening new possibilities for intelligent traffic management

ANIC forms a foundation for SmartNIC development, allowing customers to define packet shaping and traffic management capabilities in endpoint-scale hardware running at 400 GbE SmartNIC speeds. Customers gain faster time-to-market and control over customization of the ANIC IP and their value-add logic. Duplicating or de-duplicating packets, running local key-value stores, and other operations are possible on packet streams using SmartNICs.

Network security improves with intelligent traffic management for both receive and transmit, but SmartNICs have traditionally applied policies only on  receive. ANIC enables policies to be applied to both received and transmitted data. “Let’s say one night, there’s an application server suddenly generating unusual volumes of traffic at 2 am when nobody should be working,” Schweitzer begins an anecdote. “In a conventional enterprise networking architecture, the increased traffic would reach an appliance like a high-performance firewall, and it would have to have the proper rules to stop the packets. By moving those same rules out to a 400 GbE SmartNIC with ANIC IP installed in the application server, the suspicious traffic never leaves it, preventing propagation and reducing the load on the network.”

Artificial intelligence (AI) also looms large on the scale of ANIC possibilities. Machine learning processors (MLPs) in the Speedster7t could learn and deploy ANIC rules by observing SmartNIC traffic patterns before network security teams notice a vulnerability. Endpoint-native learning could also drive a virtual, distributed, intelligent load balancer, offloading traffic to other platforms if concentrated traffic patterns emerge.

Achronix is putting a solid effort into ensuring its high-performance Speedster7t FPGA is ready for advanced real-world applications. A 400 GbE SmartNIC is just one possible use case for the Speedster7t – and it’s a good one since few other approaches can achieve the same results. We’d expect customer innovation to take over with a range of differentiated solutions built on 400 GbE ANIC IP.

Learn more in the Achronix press release:
Achronix Pushes the Boundaries of Networking with 400 GbE and PCIe Gen 5.0 for SmartNICs

Also Read:

eFPGA Enabled Chiplets!

The Rise of the Chiplet

Achronix on Platform Selection for AI at the Edge


The Siemens Digital Industries Software View of AI and its Impact on System Design

The Siemens Digital Industries Software View of AI and its Impact on System Design
by Mike Gianfagna on 07-13-2023 at 6:00 am

The Siemens Digital Industries Software View of AI and its Impact on System Design

The impact of AI seems to be everywhere. Products are smarter, doing more of what used to be done by the humans. Complex tasks can be completed quicker and with greater accuracy and failures can now be predicted more reliably and repaired before they even occur. The AI technologies used to make all this happen and how those technologies are applied to tasks familiar to SemiWiki readers is the subject of a new white paper from Siemens Digital Industries Software. The white paper presents a comprehensive view of our changing world; this is required reading for those doing electronic system design. A link is coming, but first let’s examine the Siemens Digital Industries view of AI and its impact on system design.

The AI Tools of the Trade

The term AI, or artificial intelligence has a very broad meaning. It represents a collection of algorithms and information processing strategies. Many of these concepts have been around for quite a while, some dating back to the 1940’s. A combination of new application strategies enabled by vast processing power has created the revolution we are witnessing now. According to the white paper:

During the last ten years, artificial intelligence (AI) has progressed from a visionary concept to a mainstream reality in many large companies.

The white paper provides a very useful overview of the technologies at play in this revolution and how they fit together to address real-world problems. I recommend you get the first-hand view of all this from the white paper. These technologies are woven together using mathematics, computer science, statistics, and psychology. They include machine learning and deep learning. The goals of AI application discussed are broad and include:

  • Make informed decisions, increasing efficiency
  • Complete routine tasks with minimal effort, improving productivity
  • Improve expertise by recommending next tasks

AI Applied to PCB Design

PCB design is used as an example in the white paper to illustrate the impact of AI. PCB design challenges engineers to generate designs that have adequate power and cooling for complex and fast ICs while maintaining signal and thermal integrity for every high-speed signal between the various ICs on a board. The complexity of the problem can explode quickly. This application provides a great backdrop to see the various ways AI can revolutionize design. 

Many aspects of AI’s impact on the design process are discussed in the white paper. Here is a brief summary to whet your appetite:

Learning curve: Experienced engineers develop an intuition about how to optimally apply tools and set options. This is the main reason the productivity of a senior engineer is so much higher than that of a junior engineer. What if AI could capture this intuition, allowing junior engineers to perform like senior engineers?

Component selection: Engineers spend a lot of time researching the selection of components to optimally address system requirements. What if a model could be developed based on historical information to cut this problem down substantially?

Component model creation: Generating models to represent the components (e.g., symbols, 2D/3D physical geometries, and simulation models) takes a lot of time and demands many different skillsets. What if natural language processing, image recognition, and ML could be applied here?

Schematic connectivity: Optimal component placement and connection requires a broad perspective of the design. Here is another opportunity for AI assistance.

Dynamic reuse: The knowledge applied to one design is often lost once the design is completed. What if institutional knowledge could be saved and curated?

Constraints: Again, prior knowledge can make this task much easier with higher quality results.

Layout: These tasks use heuristics to optimally automate the process. What if AI can target those heuristics to be more specific and more accurate?

Analysis and verification: Design sensitivity to factors such as material properties, physical layout and temperature/voltage all conspire to make this process challenging. What if AI can refine the interdependencies to a more predictable model?

Design synthesis: Pulling it all together, generative AI approaches can have a big impact.

The Big Picture

Siemens Digital Industries Software has a very broad footprint. Its customers span many markets, industries and applications. The white paper discusses some of the investments being made to deploy AI across this broad footprint.

Examples discussed include:

  • AI/ ML-based accelerators for edge applications get to market faster
  • Genetic algorithm-based optimization to build an efficient decoupling capacitor set for a power delivery network
  • An adaptive UI to improve user productivity by predicting the commands that users will most likely want to use
  • Delivery of 90 percent accuracy on next-step suggestions in microflows
Siemens Xcelerator portfolio

This is an incredibly broad set of AI applications across design, manufacturing, and production. As part of the Siemens Xcelerator portfolio, these tools help electronic systems design companies leverage AI technologies to deliver futuristic products to market today.

To Learn More

Here is a link to the new white paper, Reducing Electronic Systems Design Complexity with AI. AI will change the face of design and manufacturing. I highly recommend you download this white paper to learn more. It will help you to understand the Siemens Digital Industries view of AI and its impact on system design.


Transforming RF design with curated EDA experiences

Transforming RF design with curated EDA experiences
by Don Dingee on 07-12-2023 at 10:00 am

How to Design an RF Power Amplifier course screenshot

Access to sophisticated RF EDA tools is one thing. Effectively harnessing their capability in real-world use is another. Digital EDA and test & measurement providers have long recognized ongoing customer education needs for their solutions. Keysight is embarking on an initiative to develop curated EDA experiences with a wide range of free learning for RF EDA solutions.

Curation brings users better information

Keysight teams already produce a massive quantity of information online, most of which lives a very long life somewhere tied to an asset. “If you go and search Keysight.com for ‘oscilloscopes’ today, you’re going to come up with thousands of documents, videos, applications, notes, and white papers,” says Linas Dauksa, Senior Digital Marketing Manager for Keysight. “Much of this material we’ve developed as vendor-neutral for learning to do something with any oscilloscope – we’re teaching users, not selling gear.”

Still, an unaided search can produce many results – some new, some old, some on target, some not maintained. Curation can pull better results to the top, but it takes skilled resources. For the last four years, Keysight has quietly assembled an experienced digital learning team to begin the process, creating a portal called Keysight University as a first step and collecting RF EDA content in pages like this one focused on RF circuit designers.

 

 

 

 

 

 

 

 

 

 

 

 

 

“We originally thought of Keysight University as a pre-sales tool,” says Julie Pildner, Digital Learning Marketing Manager. “Soon, we discovered people were using the information in many different ways at all points in their journey – and the journey didn’t necessarily take them through the portal for everything they found useful.”

Formatting for smoother consumption in short or long form

A funny thing happens when asking people to pay for anything: expectations jump. There’s always a freemium model, where introductory information is openly available, and higher-value content is behind a paid subscription wall. The hope is free material demonstrates enough value to convince a user to subscribe and get more access for a fee. That approach can leave a lot of users behind, however.

“If I’ve paid for a subscription, and I launch into a 45-minute webinar without well-designed sections, there’s a risk I lose interest before I get the information I was looking for,” says Richard Duvall, RF EDA Portfolio Marketing Manager. “To solve that, we’re converting many of our longer content hits into easier-to-find, easier-to-navigate lessons.”

Rather than locking the entire content behind a paywall, a user journey might take them directly to a lesson section and deliver the curated EDA experiences with minimal time and no fees invested. Duvall and others have been busy converting webinars on various topics into lesson modules that look more like this one on How to Design an RF Power Amplifier. Note how users can go hands-on with downloadable workspaces reinforcing lessons.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pildner quickly points out that learners sometimes look for full-length, deep-dive webinar content on a complex topic – or maybe long-form insight, like a boot camp, from a particular expert. She sees free Keysight content in both formats moving forward, saying, “We want to be the trusted source, the first place people think of for test and measurement and RF EDA ideas.”

Learning via curated EDA experiences sets a new tone

Starting in August, Keysight learning teams plan on moving away from the hierarchical portal and toward a smoother experience integrated with search, where users can guide their journey faster from more places in Keysight.com and other environments.

These curated EDA experiences with user access to Keysight experts are a big part of the digital transformation in enterprise RF EDA solutions. Users can see how Keysight approaches real-world RF design challenges with broader access to experts and their ideas.

To support your continuous learning effort, visit the extensive EDA course library covering RF Circuit Design, RF System Design, High-Speed Digital Circuit Design, and Device Modeling and Characterization on Keysight University.


Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US

Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US
by Bernard Murphy on 07-12-2023 at 6:00 am

Sondrel scaling

It’s no secret that system companies are driving a lot of new silicon. Google, AWS, Tesla and others have well-established design teams delivering differentiated servers, AI engines and other technologies. I’m sure NVIDIA suspects sub rosa projects are already underway in many of these hyperscalers to design out their GPUs.

Below those dizzy heights, there is plenty of demand among midlevel system suppliers to build the essential brick-and-mortar silicon underlying modern electronic systems. Advances in edge AI, automotive networking and support for zonal architectures, and fixed wireless access devices for industrial and building automation are all very active domains. System builders here must also differentiate in their silicon platform to meet affordability and low-power objectives but span a spectrum from zero chip expertise, to logic design only, to an in-principle full design team not yet proven on a high-risk project.

Sondrel, a UK ASIC design services company, has provided an answer for many years to such clients, growing to be the biggest digital Design and Supply and ASIC design services organization in Europe.

About Sondrel

The company was established in the UK in 2002. Starting in back-end design services where demand is commonly highest, they have grown steadily, acquiring the ST Morocco design center and the Imagination Technologies IMG Works team, the latter adding architectural and front-end design expertise. Sondrel now has design centers in the UK, India and Morocco, with sales offices in Europe, the US and Israel (Redtree Solutions).

These are not simple designs. Even in the midrange, systems builders want video interfaces, machine learning, automotive compliance, networking, AR/VR, low-power IoT and even blockchain expertise. Design sizes are significant, one recently reported at 500 sq mils with over 30 billion transistors. They are also regularly pushing leading-edge technologies with large chip designs on 7nm and 5nm. Markets served include AI at the edge, automotive, 8K video, smart homes and cities, wearables and consumer devices.

Even more interesting, Sondrel offers a full turnkey service, from concept to delivered packaged and tested parts. They have established relationships with the principal EDA and IP suppliers, foundry relationships with TSMC, Samsung and GlobalFoundries and with leading Test and OSAT companies. Naturally, they provide supply chain management throughout this cycle. Ian Walsh (VP of Biz Dev and VP of North America Operations) makes the point that TSMC and others will only work directly with extremely high-volume customers. The only way anyone but the giants can get access to their technologies is through accredited ASIC services like Sondrel. Sondrel calls their full-service solution Design and Supply, which starts at the design concept and extends to supply chain management and delivery, distinguishing them from other lesser ASIC offerings.

Ian also adds that another key strength is their design team which has worked on over 100 designs over the last 20 years and is tightly integrated. They operate not so differently from established teams in a big semiconductor house, working on platforms they already understand (more on that next). There is plenty of opportunity to keep pushing frontiers, yet with lots of accumulated experience in managing risk. An intriguing option for a wide range of design and supply needs.

The Sondrel SFA platform

Sondrel starts with well-proven reference designs. The SFA 200 reference is architected for single-channel video and data processing, targeted at fixed and mobile (battery-powered) applications, such as Smart Home, Smart Metering, Sensor Fusion and other applications where a compact chip can provide local intelligence for end-point data processing. The SFA 250A variant adds ISO 26262 compliance, including an independent functional safety island as a basis for ASIL D compliance if requested.

The SFA 300 reference has four CPU clusters enabling powerful, scalable signal and data processing SoCs to be created faster at lower costs. This is targeted at signal and data processing applications such as 8K video, facial recognition for surveillance, smart factories, blockchain servers and medical data analysis. In a similar way, the SFA 350A reference is extended to support automotive applications.

The SFA 100 platform is designed for small-footprint IoT applications supporting features such as voice activation, image classification, gesture recognition, filtering, inference and tracking.

I think this is interesting. Turnkey ASIC Design and Supply service, load-balancing the business across the mid-tier of system companies with options to serve monster projects without overbalancing the revenue mix. You can learn more HERE.


WEBINAR: Leap Ahead of the Competition with AI-Driven EDA Technology

WEBINAR: Leap Ahead of the Competition with AI-Driven EDA Technology
by Rob vanBlommestein on 07-11-2023 at 10:00 am

Synopsys.ai

The demands on today’s designs are relentless. Each generation of devices needs to be faster, smaller, more functional, more connected and more secure than the previous generation. In the face of all this, the time required for next-generation devices to hit the market is dramatically shrinking. That means the competitive landscape is fierce.

Complexities are making it impossible for companies and engineers to keep pace and deliver high-quality results. Too much time is spent optimizing, verifying, and testing the design without any guarantee that desired targets are being met. In the wake of all this increased complexity, the semiconductor industry is encountering a shortage of talent making it difficult to innovate.

The picture being painted seems very bleak, but we are at an inflection point. The demands are outpacing the resources to deliver, and that means the technology and tools to help must change. This is where artificial intelligence plays a critical role. AI is like the industrial revolution of our generation. It is essential to make what is imagined possible.

For the semiconductor industry, AI-driven electronic design automation solutions will not only help in this highly competitive market but also will allow companies to spend time innovating.

Synopsys is hosting a seminar series that explores how companies can leverage AI-driven EDA technology to deliver significant quality of results and productivity improvements across the development flow. The series will discuss how Synopsys.ai™, the industry’s first full-stack, AI-driven EDA suite, can help tackle the PPA (power, performance, and area), verification, and test challenges associated with today’s complex designs.

The first presentation of this three-part series targets design engineers looking to optimize PPA targets using Synopsys Design Space Optimization solution, DSO.ai™. The second webcast focuses on the verification engineer and how to achieve higher quality verification coverage faster with Synopsys Verification Space Optimization solution, VSO.ai™. The third webcast addresses the challenges faced by test engineers to reduce the number of test patterns while optimizing defect coverage with Synopsys Test Space Optimization solution, TSO.ai™. All three presentations will illustrate how to eliminate redundant and repetitive tasks using the respective sophisticated Synopsys.ai technology.

The future of innovation rests on the adoption of critical AI technologies. We can no longer burden ourselves with traditional manual tasks if we are to beat the competition. AI-driven EDA technology will allow companies to focus on chip quality and differentiation and empowers engineers to get the right chip with the right specs to market faster.

Register for the Synopsys.ai webinar series today!

Also Read:

Computational Imaging Craves System-Level Design and Simulation Tools to Leverage AI in Embedded Vision

Is Your RTL and Netlist Ready for DFT?

Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint

Requirements for Multi-Die System Success


Siemens Enhances Supply Chain Visibility with Real-Time Intelligence for its Xcelerator Platform

Siemens Enhances Supply Chain Visibility with Real-Time Intelligence for its Xcelerator Platform
by Kalar Rajendiran on 07-11-2023 at 6:00 am

siemens xpedition supplyframe opengraph 1200x630

 

Next generation electronic systems require an engineering approach incorporating a digital twin methodology for early verification with digital prototypes. Over the course of a design project, the digital twin model evolves to allow more complex interactions including analysis, simulations and validations earlier in the design cycle. This enables teams to detect problems much earlier when they are easier and cheaper to fix with very little product launch schedule impact.

Siemens Xcelerator is a powerful digital platform that offers a comprehensive suite of software and services built for the digital twin methodology. The platform encompasses various domains, including product lifecycle management, computer-aided design, simulation, and manufacturing operations management. It enables organizations to optimize their entire product development process, from ideation to production, by providing a unified environment for collaboration, data management, and analysis. With its advanced capabilities, Siemens Xcelerator empowers businesses to accelerate time-to-market, enhance product quality, and drive digital transformation.

Xpedition software is a specific component of the Siemens Xcelerator platform and focuses on PCB (printed circuit board) and electronic systems design. It offers a range of advanced tools and features for system design definition, electronics design, electro-mechanical co-design, analysis, verification, and PCB manufacturing. This software provides engineers with the capabilities to create complex, high-performance PCB designs and streamline the design process. The software is widely recognized in the industry as one of the most innovative and comprehensive solutions for electronic systems design.

Recently, Siemens announced a significant enhancement to its Xcelerator platform with the integration of the Supplyframe™ Design-to-Source Intelligence (DSI) capability. By incorporating this capability into Siemens Xcelerator, the company aims to offer comprehensive component technical data and real-time supply chain intelligence to its customers. This integration is a significant addition and brings high-value to Siemens EDA’s customer base.

What is Supplyframe DSI?

Siemens Supplyframe DSI platform is an advanced solution that provides comprehensive intelligence and insights throughout the design and sourcing stages of product development. It offers real-time data and analytics related to global component availability, demand, cost, compliance, and parametric information. The solution aggregates and analyzes vast amounts of data signals from the global electronics value chain, capturing information on part supply, demand, risk, and commercial intent.

Benefits of Supplyframe DSI Integration

With the Supplyframe DSI capability integrated into Siemens’ Xcelerator, the platform empowers businesses to make informed decisions during the design phase. The solution enables seamless collaboration and data sharing, leading to better coordination, improved resource management, and increased efficiency in the digital enterprise.

Cost Reduction

The real-time supply chain intelligence provided by the integrated solution enables engineers to make better component decisions during the design phase, resulting in cost savings and improved agility. With access to detailed component intelligence on over 600 million manufacturer part numbers, engineers can make informed tradeoffs when the cost of change is lowest, optimizing the design and sourcing strategies.

Streamlined Workflows and Risk Assessments

The integration eliminates manual data entry and library maintenance tasks, streamlining the design process. Engineers can benefit from detailed part comparison views, “what-if” part selection analysis, and digitally managed workflows. Real-time part-level audits facilitate streamlined risk assessments during design capture, enabling businesses to mitigate potential supply chain risks early in the process.

Supply Chain Resilience

In today’s dynamic business landscape, supply chain resilience is crucial for organizations. The integrated solution extends Siemens’ supply chain resilience leadership by providing comprehensive real-time data and decision support to engineering, new production introduction (NPI) management, and sourcing teams. It empowers businesses to adapt their design and sourcing strategies quickly, keeping pace with industry evolution.

Summary

Siemens’ integration of the Supplyframe DSI platform with Siemens Xcelerator represents a significant advancement in real-time supply chain intelligence. By providing access to global component availability, demand, cost, and compliance data during the design phase, Siemens empowers businesses to optimize their supply chain management, reduce costs, and improve agility. The integrated solution streamlines workflows, facilitates risk assessments, and enhances collaboration among teams, enabling organizations to thrive in the face of dynamic supply chain changes.

Also Read:

Transforming the electronics ecosystem with the component digital thread

DDR5 Design Approach with Clocked Receivers

Getting the most out of a shift-left IC physical verification flow with the Calibre nmPlatform


Podcast EP170: An Overview of the New Calibre Shift-Left Methodology with Jeff Wilson

Podcast EP170: An Overview of the New Calibre Shift-Left Methodology with Jeff Wilson
by Daniel Nenni on 07-10-2023 at 10:00 am

Dan is joined by Jeff Wilson, the DFM director of product management for Calibre Design Solutions at Siemens EDA. Jeff is responsible for the development of products and design flows that address the challenges of DFM and increasing the robustness of designs.

Dan explores the capabilities of the new Calibre Design Enhancer product from Siemens EDA with Jeff. This product delivers a shift-left methodology for design implementation using proven Calibre layout modification technology. Jeff explains the use model and impact of Design Enhancer VIA, PGE and PVR.

Jeff discusses in detail how these three capabilities are deployed during design to enhance the resulting layout and reduce design time. The broad foundry and technology support of Calibre are also discussed.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Podcast EP171: A Discussion of an EDA Revenue Milestone and the Upcoming DAC with Wally Rhines

Podcast EP171: A Discussion of an EDA Revenue Milestone and the Upcoming DAC with Wally Rhines
by Daniel Nenni on 07-10-2023 at 8:00 am

Dan is joined by Dr. Walden Rhines to discuss the Q1 2023 Electronic Design Market Data report that was just released. SEMI and the Electronic System Design Alliance collect data from almost all of the electronic design automation companies in the world and compile it by product category and region of the world where the sales occurred. It’s the most reliable data for the EDA industry and provides insight into what design tools and IP are in highest demand around the world.

In this spirited and far-reaching discussion, Dan explores the anatomy of the Electronic Design Market Data report with Wally. An all-time quarterly revenue record of $4B was posted for Q1 2023. Almost all product categories saw a healthy 15 – 25 percent increase, with PCB leading the pack. Oddly, there is one category that posted flat revenue for the quarter. In terms of regional performance, Europe led the way. Asia Pac showed very mixed results. All these points are discussed by Wally.

The upcoming DAC was also touched on. Wally will be on a panel with Joe Costello – all questions fair game. Wally will also deliver the main keynote on Wednesday to discuss taking AI to the next level. These are must-see events.

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