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Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose

Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose
by Eric Esteve on 08-15-2011 at 10:42 am
Categories: Cadence, EDA

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If you did not have the chance to attend the famous Denali party at DAC 2011, you may want to go to Cadence VIP seminar to be held on Thursday, August 25, 2011, from 1:00 – 4:15pm at Cadence Headquarters: 2655 Seely Avenue, San Jose, Building 10. To register, click here. The atmosphere could be slightly different, as during Denali party the VIP from Cadence were the stars of the show, when for the seminar the stars will be the VIP for AMBA4 ACE, PCI Express gen-3, USB 3.0 and DDR4, to mention a few. In this seminar Cadence will propose case studies from experts in the field addressing the most challenging issues when it comes to verifying today’s most important interfaces such as the four above listed.

I have blogged about Cadence VIP, or VIP in general, in the past:

Yalta in EDA: Cadence stronger in VIP territory…

Interface IP: VIP wiki

IP would be nothing without VIP…but what is the weight of VIP market?

If you can make it (and you live in the Silicon Valley…), and you need to know more about VIP or need to be updated about the latest product, as Cadence is leading the VIP market and has built a wide port-folio, covering most of the existing Interfaces, you will certainly make a wise investment! To register to this VIP seminar, just go here.

Or, if you cannot make it, have a look at Cadence impressive VIP port-folio (just click and see the product from Cadence web site):

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OPC Model Accuracy and Predictability – Evolution of Lithography Process Models, Part III

OPC Model Accuracy and Predictability – Evolution of Lithography Process Models, Part III
by Beth Martin on 08-15-2011 at 7:00 am
Categories: EDA, Siemens EDA

Wyatt Earp probably wasn’t thinking of OPC when he said, “Fast is fine, but accuracy is everything,” but I’ll adopt that motto for this discussion of full-chip OPC and post-OPC verification models.

Accuracy is the difference between the calibrated model prediction and the calibration wafer result. Accuracy depends on several factors, principally the intrinsic ability to represent the patterning trends through target size, pitch, and pattern shape for 1D and 2D structures at a given process condition. Calibration test pattern design coverage is important whenever model accuracy is in question.

Additionally, because you judge OPC model prediction against experimental data, you must consider the experimental errors associated with the metrology data. For an ensemble of different test patterns, a model’s accuracy is limited by the experimental noise “floor.” Multiple repeat measurements (across wafer, across field) provide a better statistical representation and lower this noise contribution to the model. It is interesting to note that the standard error in the determination of the mean for typical OPC calibration structures is 0.5 nm for 1D and 1.5 nm for 2D.

The degrees of freedom in the model will interact with the metrology noise such that it is possible to “over fit” the physical phenomena and start fitting the experimental noise.How can you quantitatively express the accuracy of a model? Metrics include maximum error, error range, chi-squared goodness of fit, and others. But one of the most useful is the “root mean square error value,” or errRMS (Equation 1) associated with the test pattern ensemble. This weighting (w) allows users to assign more importance to certain known critical design pitches. CDs may be used instead of EPE as well.

[INDENT=2]Equation 1. CDsim[SUB]i[/SUB] is the model mean for each point i (measurement location); CDmeas[SUB]i[/SUB] is the data mean for each point i ; w is the user-specified weighting for each point i

An interesting variant of RMS error (see Schunn and Wallach 2005), which accounts for sample metrology error directly, is the scaled RMS deviation (Equation 2). This objective function more heavily penalizes errors associated with precisely known data points than for data points with CDs having larger uncertainties.

[INDENT=2]Equation 2. s[SUB]i[/SUB] is the standard deviation for each data mean i; n[SUB]i[/SUB] is the number of data values contributing to each measured mean; k is the number points i

A related, but ultimately more important characteristic is model predictability. The duty of the OPC or post-OPC verification model is to correctly predict the patterning for every possible layout configuration that can appear per the design rules in the full chip. The number of unique design constructs for low k[SUB]1[/SUB] lithography is tremendous; several orders of magnitude more than could ever be reasonably used to train the model. If you divide a master set of patterns into two sets–use one half to train the model, and the other half to verify–the errRMS fitness should be as low on both sets.

Another method involves including the complex 2D structures of the verification patterns, and then comparing the simulated contour with the experimental contour. If verification fitness is significantly worse than calibration fitness, the model is not sufficiently predictive. In addition, the model must account for CD variability arising from manufacturing process variability. Principle among these are focus, exposure, and mask CD variations (Figure 1).

[INDENT=2] Figure 1. Example plot of model error RMS for various focus and exposure conditions. Model was calibrated at dose = Nom and focus = 0. Model fitness was then characterized for various defocus and exposure conditions.

As will be outlined in a future installment of this series, the ability of a model to faithfully predict various pattern failure modes is also important. These failures typically manifest more severely as these manufacturing process parameters vary. A final consideration related to predictability is model portability. Of course, if an entirely new photoresist material, PEB temperature, or etch recipe is implemented for manufacturing, you will need a new model calibration. But if some aspect of the exposure step is slightly altered, such as NA or illumination source intensity / polarization, you should be able to “port” the same resist model and change only specific optical parameters. This is particularly helpful in early process development, when an existing process model is used to simulate next node printing with whatever new RET capabilities may become available. The degree to which the model can decouple optical exposure from resist processing is related not only to the details of the resist model, but also to the nature of the approximations “upstream” in representing the mask and optical system. The details of these mask and optical models will be the topic of my next installment in this series of articles. Stay tuned.

–John Sturtevant, Mentor Graphics

P.S. In case you missed them, go readPart 1 and Part 2 of this series. Then continue with Part 4.

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Will AMD Crash Intel’s $300M Ultrabook Party?

Will AMD Crash Intel’s $300M Ultrabook Party?
by Ed McKernan on 08-14-2011 at 7:00 am
Categories: Arm, Foundries, Intel Foundry, IP

Let’s face it, the ships are burning in the harbor and there is only one way out of here for AMD. It needs to crash Intel’s exclusive $300M Ultrabook Party in order to grab a slice of the future, more profitable PC market.

Intel Capital Creates $300 Million Ultrabook Fund
Continue reading “Will AMD Crash Intel’s $300M Ultrabook Party?”

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ANSYS/Apache

ANSYS/Apache
by Paul McLellan on 08-13-2011 at 2:43 pm
Categories: Ansys, Inc., EDA

Last week I met with Andrew Yang, erstwhile CEO of Apache Design Systems and now formally President of Apache Design Inc, a wholly owned subsidiary of ANSYS. The merger formally closed at the start of the month. Within ANSYS Apache is positioned as Chip-aware System-level Engineering Simulation. ANSYS is pretty much completely focused on different kinds of simulation and on simulation-driven product development.

ANSYS will keep Apache as a subsidiary and, in particular, the Apache name (and presumably the names of its products) will not be going away. The system design challenges that Apache is addressing fall into four main areas: power integrity, signal integrity, thermal/mechanical-stress integrity and electro-magnetic interference integrity. Most of these are dominated by various aspects of switching power.

Anyone who has been through many mergers knows just how much time can be burned up in dealing with overlapping products, so this merger has it easy. There is no overlap at all. However, there is plenty of customer overlap.

ANSYS is a very different company from even a big EDA company. It makes about 1/3 of its money on mechanical, 1/3 on fluid dynamics and 1/3 on electronics (now including Apache of course). Andrew was rightly proud that all 20 of the top 20 semiconductor companies used Apache, with over 100 total customers. ANSYS has over 40,000 customers (including 97 of the Fortune 100).

In some ways, EDA is an easy industry: look at the semiconductor roadmap, find some effect that is currently second or third order but which will become important, and produce a solution that is ready just when designers need it. However, getting the timing right is very difficult and more companies/products fail from being too early than being too late. Apache has done a superb job of getting this timing just right so that as power and noise became more important they had the best (or sometimes only) products to perform the analysis.

For example, a few years ago they decided that it was no longer possible to just look at the chip, they needed simultaneous analysis of chip, package and board. They acquired Optimum to jump start the package and board side of things and built a whole infrastructure for creating power models for chips and being able to analyze what came to be called chip-package-system (CPS). With the coming of 3D chips and through-silicon vias (TSVs) there are even more challenges in this area, especially the thermal issues once many die are stacked and it is hard to get the heat out.

Based on that track record, I asked Andrew what is next. What second order effects are we going to have to start to worry about. He reckons that it is quantum effects and the impact on reliability. The margin on transistor thresholds is going away as voltages continue to decrease. Leakage will get even more out of control (and since leakage also increases with temperature there are very real possibilities of thermal runaway). It is going to get very hard to guarantee that a chip will work correctly in the system and that it will be possible to manufacture.

ANSYS (with Apache) is extending chip-package-system to include other parts of the system such as multi-physics simulation. In many areas, most obviously automotive and aerospace, electronics is intimately tied in with mechanical and simulation-driven product development needs to combine these previously independent areas.

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Current State of Tablet Products

Current State of Tablet Products
by Daniel Nenni on 08-12-2011 at 12:57 pm
Categories: General

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Tablets are hot items these days. There is exuberance about the speed of application processors, size of the internal memory, capabilities of the operating systems, WiFi or 3G/4G connectivity, quality of the display, cameras megapixels, battery life, tablet weight, etc. All of these features are very important, no question about that; how else could one compare one product to the other? But let us step back for a moment and look at the bigger picture and see if there are some common threads.

I believe several trends deserve our attention and should be spelled out. These are: the proliferation of the operating systems, proliferation of the form factors, and price point.

The proliferation of the operating systems, as shown in Table 1, is evident. This is not exactly a testament to a harmonization effort; it looks more like the Wild West, where everyone is trying individually to position themselves as a serious contender by getting consumer attention in this newly created market segment without much consideration for standardization. There are currently six major operating systems (Android, iOS, WP7, QNX OS, WebOS, and MeeGo) jogging for the front position, and a few more in the works, recently announced by several companies; and every single one is creating its own ecosystem and applications.

The proliferation of different form factors (anything from 5” to 10” displays), as shown in Table 2, is another characteristic of the current products, suggesting that the entire tablet market segment is in a state of ‘soul searching,’ trying to find out what the customers prefer. This is not necessarily a bad thing, but it suggests that tablets as products are indeed in their infancy and significant transformations of these products should be expected in the next couple of years before consumers cast their final judgment.

Finally, here is the third important point related to the current tablet products. The selling price of the tablets from all major manufacturers is still high – clustering around $500. Thus, it should not come as a surprise that the second highest selling product after the iPad2 tablet in the first quarter of 2011 was Barnes and Noble’s 7 inch Nook Color priced at $250, according to the report from DigiTimes. This trend is expected to continue for the rest of the year. A price point of $250 is half that of the rest of the crowd, and certainly represents one of the best values.

Here is the interesting part. Nook Color is not the most capable tablet but it is a solid performer. It runs the Froyo (Android 2.2) operating system tuned by Barnes and Nobel for selling books and magazines. The application processor is TI’s OMAP 3621 (the same line of OMAP 3 processors that is found in Motorola’s smartphones Droid X and Droid2). This is a single core application processor, not exactly the top of the line as is the dual core Tegra 2 from nVidia (which is found in the top tier tablets). And yet, Nook Color, the modest performer that it is, still outsells all other feature-rich android tablets.

Table 1: Operating Systems for Tablets and Smartphones

Company Operating Systems Product Top Tier OEMs
(manufacturers of smartphones and tablets)
1. Google Android 2.2/2.3 (Froyo/Gingerbread) smartphones, tablets Google, MOT, Samsung, HTC, LG, Sony Ericsson, Dell, ZTE, Huawei, Lenovo, Asus, NEC, Sanyo, Sharp
Android 3.1 (Honeycomb) tablets MOT, Samsung, HTC, LG, Sony, Dell, ZTE, Huawei, Lenovo, Asus, Sharp
Android 2.4 (or 4x) (Ice Cream Sandwich) smartphones, tablets Expected: Google, MOT, Samsung, HTC, LG, Sony, Dell, ZTE, Huawei, Lenovo, Acer, Asus, NEC, Sanyo, Sharp
2. Apple Apple iOS 4 iPhone, iPad Apple
Apple iOS 5 iPhone, iPad Apple
3. BlackBerry QNX Neutrino OS tablets RIM
BlackBerry OS 6 smartphones RIM
BlackBerry OS 7 smartphones RIM
Blackberry Colt smartphones, tablets RIM
4. MSFT Windows WP7.1 (Mango) smartphones, tablets Nokia, Samsung, HTC, LG, Sony Ericsson, Dell, ZTE, Huawei, Lenovo, Asus, MSI
WP8 smartphones, tablets Expected: Nokia, MOT, Samsung, HTC, LG, Sony Ericsson, Dell, ZTE, Huawei, Lenovo, Asus, MSI
5. HP webOS 2.0 smartphones, tablets HP
webOS 3.0 tablets HP
6. Intel MeeGo 1.1 smartphones, tablets Intel, Acer, Lenovo. MSI
7. Nokia Symbian smartphones Nokia

Note: Symbian is listed here since there still will be a number of legacy smartphones from Nokia

But there is an additional reason for the popularity of Nook Color. Once launched, it got help from the Android cell phone and tablet community of developers that developed the modded version of Google Android called CM7 specifically for Nook Color, all in an attempt to enrich this product. In collaboration with another group, XDA Developers, together they created stable software. This software is basically Android 2.3.4 (Gingerbread) that can be booted to Nook Color via a micro SD card loaded with the software. The end result is that, Nook Color can operate in dual mode, either using Froyo that came with the original device from Barnes & Nobel, or the advanced Gingerbread operating system loaded on a micro SD card. One can purchase a preloaded 8, 16, or 32 GB micro SD card from n2a SD Cards via Amazon. In essence, all together you can get a full blown 7” tablet with the same capabilities as Samsung’s Galaxy Tab for under $300. And that is a real deal! This is a fine example of the importance that open source projects can play in shaping a product and a market.

Table 2: Tablet Form Factor

Screen Size Major OEMs Note
5 Inch Dell, Archos, Samsung, Sony Sony-5.5 ” dual screen tablet
7 Inch Samsung, Barnes & Noble, Dell, HTC, RIM, Acer, ViewSonic, Huawei, HP, Sharp, MSI, Mot Nook Color at $250; ViewSonic at $250
8 Inch Vizio, Archos Vizio at $299
9 Inch LG, Pandigital, Archos, Samsung, Amazon Includes 8.9″ size
10 Inch iPad, Mot, Samsung, Dell, HP, MSI, Acer, Archos, HTC, Sony Size from 9.7″ to 10.1″

Note: Listed OEMs are shown as examples only

The market success of the Nook Color has not gone unnoticed. Other tablet manufacturers are getting the message about the critical role of tablet price for market penetration. ViewSonic has announced a new lower $250 price for its 7” tablet, and so did Vizio for its 8” tablet, dropping the price to $299. The latest company to follow the trend is HP, dropping the price for its 16 GB 10” TouchPad that runs webOS 3.0 to $399. Consumers will certainly love this trend.

Lj. Ristic, Managing Director, Mobile Markets, Petrov Group, Palo Alto, CA

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nVidia: "30 Days From Going Out of Business"

nVidia: "30 Days From Going Out of Business"
by Ed McKernan on 08-11-2011 at 9:36 pm
Categories: Uncategorized
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Jen Hsun Huang, the CEO of nVidia, has a phrase he often repeats to his employees: “We are 30 days from going out of business.” With product cycles as short as 6 months, the troops are on a constant march to revenue. The earnings conference call on August 11th highlighted two critical pieces of information. First, is the success that they are having in growing their PC graphics revenue despite the Sandy Bridge onslaught. Second, and more important, there is an internal and now a publicly articulated goal that they will reach a $1B revenue run rate for Tegra in 2012.

As outlined in an earlier Semiwiki blog titled “Intel’s Barbed Wire Fence Strategy”
http://www.semiwiki.com/forum/content/651-intel-s-barbed-wire-strategy.html Intel is in the business of expanding its fence lines. Their current target is nVidia’s graphics business. It represents not only additional revenue but also the ability to deny nVidia the funds to develop Tegra chips that will be used competitively in Smartphones and Tablets using Android as well as some Windows 8 mobiles.

All this may sound like Intel is the one to be most at risk to market share loss in 2012, especially with the launch of Windows 8 but, as a matter of fact, it is the other way around. First recognize that nVidia has finally returned to its peak run rate of $1B a quarter that they reached in 2007. Meanwhile, Intel is on track to do $55B in revenue this year or nearly 50% higher than 2007. Intel has the additional profits to crank out more designs targeting more segments. But there are clouds of uncertainty.

Windows 8, as understood by most people, unlocks the whole PC market to ARM based processors. Untrue! To get Win 8 to be light on its feet – meaning small memory footprint and fast boot/resume – Microsoft had to make compromises. First and foremost, Microsoft had to limit the hardware ecosystem. A closed system with support for fewer I/O devices makes life easier. No more Swiss Army Knife. How well will the Win 8 mobile run? We won’t know until it ships. The reduced hardware ecosystem should be fine for tablet – but a “clamshell” design is open to interpretation. Are they reduced netbooks?

Intel’s challenge is much different than nVidia’s but still attainable. Back in May, at their Analyst Meeting, Paul Otellini announced they were dropping their Thermal Design Point (TDP) for processors from 35W to 17W. We now know what drove them to this decision, or better yet, who drove them to this decision.

A story broke yesterday in the Wall St. Journal where it was noted that Apple informed Intel that it better drastically slash its power consumption or risk losing Apple’s business. As an Intel exec said, “It was a real wake up call to us.” For more on the story – follow the link:

http://blogs.wsj.com/digits/2011/08/10/intel-sets-300-million-fund-to-spur-ultrabooks/

As I mentioned in an earlier blog, the MAC Air is driving the mobile market. It uses Intel ULV processors that have a TDP of 17W (50% lower than regular Intel mobile Sandy Bridge CPUs) and sells for a minimum of $220. The price of the CPU is based on the yield they get per wafer. In this case <50%. Intel needs to get to 7W ideally to make Apple happy in the near term. And they need to offer an entry-level price closer to $75 – so Apple can take MAC Air to $799 thereby sucking the oxygen out of the notebook PC market. This is where I believe Intel will be one year from now with the 22nm Ivy Bridge ULV (A straight die shrink of Sandy Bridge at a similar MHz to today’s ULV). If this still seems high relative to ARM, it is, and Apple has probably informed Intel that they need a 3-5W TDP with Haswell as they go even more aggressive on a future MAC Air. Sound confusing? Consider this like two great armies rushing to the same spot at the front. Each has their own unique strengths and weaknesses. In the end – it is the market that lies just a tad above Apple’s entry level $499 iPAD. Call it $499+1. Note: You must be logged in to read/write comments

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Altera and Xilinx Eyeing 28nm FPGA Dominance

Altera and Xilinx Eyeing 28nm FPGA Dominance
by Ed McKernan on 08-11-2011 at 7:00 am
Categories: FPGA, Xilinx

28nm FPGAs are finally hitting the market and the next round in the battle between Altera and Xilinx is heating up. At 40nm, Altera beat Xilinx out the door by a year and as a consequence won a lot of new sockets in the high end Communications market. In the past year, Altera has closed the revenue and market share gap with Xilinx. This new round at 28nm looks to be much closer. However, the winner of the contest may come down to whom has the better eye – as in eye diagram.

Previously, I was a co-founder of Cswitch, a packet based FPGA startup that built the fastest FPGA in 90nm. It featured a new interconnect that could route 400Gb around the chip to be manipulated in special packet processing engines. It was an awesome chip that was suitable for 40G and 100G routers that would normally require 2 or 3 high end FPGAs. We were going after the 45% of the FPGA market tied to high $$$ wired and wireless communications. Alas we ran out of money after samples were delivered but before production started.

In the old days it was all about the tools – whoever has the best tools wins. More recently IP is playing a huge factor in who wins sockets as the engineers are looking to get their design done quickly and accurately. However, as you go up in performance and capability, it is the speed, number and quality of the Serdes that determines if you are even in the game to begin with. We were running 40 Serdes at 6.3G+ at Cswitch – today Xilinx and Altera are running up to 28G to support 100G/400G designs – Amazingly Fast. Altera and Xilinx want to get out of the gates quickly because they are first with the fastest Serdes (beating Broadcom and the NPU vendors). The prototype revenue alone is large as chips sell for $6K, $8K or $10K each. But Cisco, Alcatel, Huawei, Juniper, and others are looking to get product out quick with the latest 100G and 400G routers and switches to show their customers and perhaps do field trials.

Lately Xilinx and Altera are out promoting their Serdes heavily to convince engineers that they are ready.

Here’s Altera’s 28G Serdes Demo:

http://www.altera.com/education/webcasts/videos/videos-industry-first-28gbps-fpga.html?contactID=177581473&gwkey=EGIRI8TNBL

Here’s the Xilinx Serdes 28G Demo:

http://www.xilinx.com/technology/roadmap/28g-serial-transceiver-technology.htm

I am not an expert on Serdes but I am sure a few of our readers are and would be willing to share their thoughts on whether Xilinx and Altera have nailed it at 28nm. Who has the better eye and the least jitter? Let us know.

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How Tektronix uses Hardware Configuration Management tools in an IC flow

How Tektronix uses Hardware Configuration Management tools in an IC flow
by Daniel Payne on 08-10-2011 at 5:49 pm
Categories: Cliosoft, EDA

Last Monday I sat down with Grego Sanguinetti in Beaverton, Oregon at the campus of Tektronix to hear about how they design their ICs using EDA tools from multiple vendors.


Continue reading “How Tektronix uses Hardware Configuration Management tools in an IC flow”

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Reducing SoC Power Consumption using Integrated Voltage Regulators

Reducing SoC Power Consumption using Integrated Voltage Regulators
by Daniel Nenni on 08-10-2011 at 5:00 pm
Categories: IP

Last month I had the pleasure of meeting Mr Wonyoung Kim, a PhD candidate from Harvard University. Like many candidates, Wonyoung is shopping his thesis for capital in hopes of starting a semiconductor IP company. Here is a brief summary of the technology, please provide appropriate feedback and let’s see if we can get him some seed money:
Continue reading “Reducing SoC Power Consumption using Integrated Voltage Regulators”

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Best EDA company for work life balance?

Best EDA company for work life balance?
by Daniel Payne on 08-10-2011 at 1:25 pm
Categories: EDA, Siemens EDA

What was the first EDA company name that came to your mind after reading that title?

At Forbes magazine they rated both Mentor Graphics and Synopsys in the top 25 best companies for work life balance.

That’s quite an honor for both Mentor and Synopsys so I can say that EDA dominated the list this year.

Here are some of the factors that give Mentor such an honor:

  • Corporate headquarters in Wilsonville, Oregon an affordable place to live (compared to Silicon Valley)
  • Five weeks of paid vacation per year (Flexible Time Off)
  • Medical benefits
  • Dental benefits
  • 401K plan with matching funds
  • Annual company picnic
  • Annual company party
  • Child care in Wilsonville from newborn thru Kindergarden
  • Gym with basketball court in Wilsonville
  • Perks for top employees (tickets to NBA, NHL, etc.)
  • Employee stock purchase plan with guaranteed 15% discount
  • Adoption program
  • Women can nurse their infants
  • Prepaid legal program

Here’s the list of the top 25 companies for work-life balance:
[LIST=1]

  • Nestle Purina PetCare
  • Mitre
  • SAS Institute
  • FactSet
  • United Space Alliance
  • Slalom Consulting
  • Facebook
  • Morningstar
  • Susquehanna International Group
  • Colgate-Palmolive
  • Mentor Graphics
  • Autodesk
  • Sheetz
  • Agilent Technologies
  • Turner Broadcasting
  • DuPont
  • Southwest Airlines
  • General Mills
  • Biogen Idec
  • Scottrade
  • Chevron
  • Synopsys
  • MTV Networks
  • Intuit
  • National Instruments