This blog is a follow-up to my second most viewed page Moore’s Law and 40nm Yield, with a strong recommendation of how to design for yield at the advanced nodes (32/28/22nm) with Verify High-Sigma design technology.
Case in point: Circuit blocks such as complex standard cells or memory bit cells are repeated thousands or even millions of times on a die. For the overall chip to have good yield, the repeated block must have extremely high yield. Calculating yield in this context is very important due to increasing process variations at each new technology node.
One approach would be to use Monte Carlo sampling. Unfortunately, this would require far too many simulations: a circuit with 99.9999% yield would need, on average, 1 million samples from the true distribution just to observe a single failure against circuit specifications.
Compared to a plain Monte Carlo simulation, Verify High-Sigma design is orders of magnitude faster for estimating yields of high sigma circuits.
With a normal Monte Carlo run, process points are drawn directly from the process variation distribution. The problem, as noted earlier, is that far too many samples are needed in order to get failures in the design. Verify High-Sigma Design changes this by sampling from a different distribution, in which a greater proportion of samples are failures. This approach is a variant of importance sampling. Verify High-Sigma Design estimates the yield of high-sigma circuits by:
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- Creating a new sampling distribution such that a greater proportion of samples are failures.
- Drawing samples from the new distribution, simulating them, and seeing if they meet specifications.
- Estimating yield by mathematically unbiasing the samples, according to importance sampling formula.
- Computing yield accuracy, using a statistical technique called bootstrapping.To illustrate that Verify High-Sigma (VHS) design returns yield estimates as accurate as a standard Monte Carlo (MC) run, the following table compares MC and VHS yield estimation results across 6 different circuits on moderate-yield circuits (moderate yield so that MC only needs a moderate number of samples to make a good yield estimate). For all 6 cases, the yield estimates for VHS and MC agree because their yield confidence bounds overlap.
[TABLE] style=”width: 528px”
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| style=”width: 107px” | Circuit
| style=”width: 209px” | MC Yield (up to 10K samples)
| style=”width: 213px” | VHS Yield (250 samples)
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| style=”width: 107px” | Current mirror
| style=”width: 209px” | 99.580% (99.433% – 99.689%)
| style=”width: 213px” | 99.709% (99.569% – 99.808%)
|-
| style=”width: 107px” | GMC
| width=”209″ | 99.836% (99.519% – 99.944%)
| width=”213″ | 99.831% (99.752% – 99.885%)
|-
| width=”107″ | LNA
| width=”209″ | 99.950% (99.883% – 99.979%)
| width=”213″ | 99.888% (99.760% – 99.9662%)
|-
| width=”107″ | Folded opamp
| width=”209″ | 99.221% (98.027% – 99.699%)
| width=”213″ | 99.490% (98.639% – 99.370%)
|-
| width=”107″ | CP
| width=”209″ | 99.597% (99.410% – 99.725%)
| width=”213″ | 99.522% (99.291% – 99.682%)
|-When design teams and managers consider which advanced technologies to incorporate in their flows, their metrics include quality of results (QoR), use model, ease of adoption, and cost. Verify High-Sigma design technology addresses each of these metrics. Designers can improve the quality of their results by changing their designs using High-Sigma extracted corners. They can statistically verify their designs with SPICE accuracy in a relatively short amount of time.
