One of the challenges with verifying today’s large chips is deciding which signals to record during simulation so that you can work out the root cause when you detect something anomalous in the results. If you record too few signals, then you risk having to re-run the entire simulation when you omitted to record a signal that turns out to be important. If you record too many, or simply record all the signals to be on the safe side, then the simulation time can get prohibitively long. In either case, re-running the simulation or running it very slowly, the time taken for verification increases unacceptably.

The solution to this paradox is to record the minimal essential set of data needed from the logic simulation to achieve full visibility. This guarantees that it will not be necessary to re-run the simulation without slowing down the simulation unnecessarily. A trivial example: it is obviously not necessary to record both a signal and its inverse since one value can easily be re-created from the other. Working out which signals form the essential set is not feasible to do by hand for anything except the smallest designs (where it doesn’t really matter since the overhead of recording everything is not high).

SpringSoft’s Siloti automates this process, minimizing simulation overhead while ensuring that the necessary data is available for the Verdi system for debug and analysis.

There are two basic parts to the Siloti process. Before simulation is a visibility analysis phase in which the essential signals are determined. These are the signals that will be recorded during the simulation. Then, after the simulation, is a data expansion phase when the signals that were not recorded are calculated. This is done on-demand, so that values are only determined if and when they are needed. Additionally, the signals recorded can be used to re-initialize a simulation and re-run any particular simulation window without requiring the whole simulation to be restarted from the beginning.

Using this approach results in dump file sizes of around 25% of what results when recording all signals, and simulation turnround times around 20% of the original. With verification taking up to 80% of design effort these are big savings.

More information:

• Siloti product page
• Verdi product page

I was recently talking to a friend who works for a semiconductor company (I can’t tell you which one or how big it is. I am not even sure I can tell you that he/she works for a semiconductor company.) I was describing Semiwiki.com to him/her and this person thought it was a great concept but wondered how much of the site would be focused on custom design. He/she wished there was more open discussion about techniques and tools used in custom design. Here is the problem and he/she described it:

1. There are relatively few companies that do custom IC design as a result, compared to the number of ASIC design teams there are only a small number of custom design teams. Finally this means that there are relatively few custom designers.

2. Custom designers and design teams typically work on the most important, most secretive, most costly and potentially the most profitable parts of a chip or system, in other words the crown jewels of the company.

3. In an effort to protect these highly competitive pieces of technology, almost universally, the companies that do custom designs have a complete embargo, on sharing any information about their designs and even their design flows.

4. Typically these information embargoes are so restrictive that even mentioning that the company uses a given tool or technique becomes a firing offense.

I find myself thinking this is secrecy gone amok.

There is no question that technology area is fiercely competitive; that the stakes run into billions of dollars; That being first to market with something like an iphone, or ipad can be worth billions of dollars and needs to be protected. Yet the question still remains, do those companies really gain when they refuse to share basic information about the nuts and bolts of their design flows, their design bottlenecks and their design tools?

I would argue that the competitive advantage comes not from these flow “secrets” but rather from pure differentiated technology, which is a combination of hardware, software and concept or idea, plus brilliant demand creation marketing. What ends up happening is that these companies end up wasting millions of dollars recreating, reinventing the basics. It means that every single time there is a fundamental/foundational problem each company spends hundreds to thousands of man hours figuring out how to solve what are really basic problems, that ultimately everyone solves in one fashion or another. That each company evaluates multiple tools that solve the same problem without a clue as to whether or not it has worked or failed for other companies.

What I find so puzzling is that given the enormous expense of building up a flow, evaluating and selecting tools, direct and indirect engineering costs, plus the inherent risk of producing a new product or device, how little interest there is in sharing the basics. Do have this right or wrong?

And probably more protocols, like: Firewire, eSATA, HDMI …
Some of you probably know it as Light Peak, as it was the code name for the just announced (last week) Thunderbolt Intel proprietary interface, supporting copper (or optical) interconnect when Light Peak was optical only. This will make Thunderbolt easier to implement, and more dangerous for USB 3.0 and the other Interface in competition.

Thunderbolt is a High Speed Serial, Differential, Bi-directional offering 10 Gbps per port and per direction. Each Thunderbolt port on a computer is capable of providing the full bandwidth of the link in both directions with no sharing of bandwidth between ports or between upstream and downstream direction. See: http://www.intel.com/technology/io/thunderbolt/index.htm
Intel will provide the technology (protocol)and the silicon, the Thunderbolt controller. So far, Intel was providing the protocol controller on the Host (PC) side, through the Chipset, to support the PCIe, USB, eSATA etc… and other chip makers the controller on the peripheral side, sourcing the related protocol IP (PHY or Controller) to IP vendors, when necessary. Now, Intel will be present on both side of the link.

Thunderbolt Controller supports natively two protocols: PCIe and DisplayPort. Intel claims that “Users can always connect to their other non-Thunderbolt products at the end of a daisy chain by using Thunderbolt technology adapters (e.g., to connect to native PCI Express devices like eSata, Firewire). These adapters can be easily built using a Thunderbolt controller with off-the-shelf PCI Express-to-“other technology” controllers.” What does this means? That the BOM for peripheral will increase, as you add Intel device to it, but you still need a PCI Express to other technology controller (when there was a unique controller before)!

What does this means for the IP vendors? On the PC side, on mature technology (like USB 2.0), they were not present as the PC Chipset was supporting the protocol (please note that this was not true for USB 3.0, not supported from now by Intel). So, no big change. But, on the peripheral side, the number of protocol previously supported will reduce to PCI Express (in term of PHY IP sales) and to a PCIe to “other protocol” bridge on the controller side. In other word, it will probably kill the USB 2.0, yet to come USB 3.0 and eSATA IP sales.

The other protocol natively supported by Thunderbolt is DisplayPort. Here the target competitor seems to be Silicon Image with HDMI. This makes sense on the PC side, supporting only one connector will be cheaper. Which is unclear is the willingness of Intel to be present in the HDTV type of product. If this is the case, we can expect these products to support both HDMI and DisplayPort, at least until the market decide to reject one of these. If Thunderbolt finally win in the Consumer Electronics (which is far to be certain), this will increase Intel sales for chips and kill any IP sales for HDMI, USB 3.0… and DisplayPort in the Consumer Electronic segment.

Another big unknown is Thunderbolt penetration into the Mobile Internet Devices segments (Smartphones, Media Tablets). So far, in the mobile handset segment, you find HDMI and USB 3.0 protocols supported in the high end products. Thunderbolt could kick out these two, at two minimum conditions: the controller price and power consumption. If you look at the Application processor for Smartphone market, you see that the chip makers tend to integrate IP (internal or sourced to IP vendors) and leaving Intel catch a part of the BOM is probably not their first priority!

From an IP market point of view, Thunderbolt does not look great, except maybe for the PCI Express PHY IP vendor, as well as the PCI Express to “other protocol” bridge controller IP developers, at the condition that this market is not cannibalized by off-the-shelf (ASSP) solutions. From an OEM point of view, this means that the PC peripheral manufacturer will have to pay a tribute to Intel (that they did not do before).as well as the Consumer Electronic and Cell phone manufacturers. Will Thunderbolt be Intel Trojan horse into the other than PC segments?
Eric Esteve
www.ip-nest.com