Semiconductor IP Becomes A Critical Element in ASIC Design

Semiconductor IP Becomes A Critical Element in ASIC Design
by Daniel Nenni on 02-19-2012 at 4:05 pm

 Clearly one of the market trends proving troublesome in the traditional ASIC value chain is the lack of silicon correlated custom IP. And make no mistake, semiconductor IP is a critical decision since it drives both chip level and system level technology differentiation.

Under the traditional ASIC model, vendors had their own IP, silicon-proven and tuned to their own fabs. This was a good thing as it assured a fast ramp to volume and more predictable yield curves. The downside was that IP catalogs were somewhat limited which constrained product differentiation. And now a staggering 49 fabs were shut down in 2009-11 as traditional ASIC vendors and IDMs continue to go fabless.

Fortunately there is a new value chain model in play today that provides all of the silicon-proven IP benefits of the classic ASIC value chain model and provides a broader portfolio of in house-developed and third party IP. As a long time IP guy I can tell you that this is of great importance! The semiconductor ecosystem revolves around IP, it is the lifeblood of our industry!

The new model, now being promoted by Global Unichip Corporation (GUC), is called the Flexible ASIC Model[SUP]TM[/SUP]. It’s built on the premise that a company should not be constrained by its own assets such as manufacturing, IP, test or assembly, but rather should be able to focus on providing the most efficient design and the fastest time-to-market. This is a critical component that makes the Flexible ASIC Model work.

Make no mistake, while GUC provides streamlined and robust integration of third-party IP, it has not overlooked, and has in fact invested heavily in, its own IP development capability. As I blogged in Semiconductor IP Dilemma, four years ago GUC was an IP baron design services provider. Now GUC has a full lP portfolio with custom IP design groups in Taiwan, China, and Silicon Valley.
 Much of GUC’s in-house developed IP covers SerDes, Data Converters and DDRs. The rationale for developing these particular blocks in-house is that these are the micros with the greatest demand and differentiation for the SoC ASIC marketplace, and I agree completely.

The main advantages of using in-house developed IP is the ability to know the precise effects of packaging and boards on the signal because the company has end-to-end supply chain capabilities and often end-to-end responsibilities.

By integrating IP development and implementation with package design, board design, and chip design, a Flexible ASIC Provider can simulate the complete system performance before sending the device to the manufacturing. The real key in this whole process is the capability to test for board effects and signal integrity then to be able to predict those impacts on the system and on the IP.

The secret to achieving superior performance, low power, and area balance lies in the hybrid analog/digital IP architecture that GUC uses to design its IP. This plus the access to advanced technology nodes, thanks to its very close working relationship with manufacturing partner TSMC, creates key differences that have proved critical to ASIC developers. Remember, GUC is directly across the street from TSMC Fab 12.

IP availability is absolutely becoming a critical differentiation and a much discussed option in the design community. Which raises the question of the day:

What are some of the hardest to find critical IP that you need to fit your current and future designs?



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