Xilinx in an ARM-fueled post-Altera world

Xilinx in an ARM-fueled post-Altera world
by Don Dingee on 06-29-2015 at 5:30 pm

When the news broke about the on, off, and on-again Intel-Altera merger a few weeks ago, I checked off another box on my Six Degrees of Kevin Bacon scorecard. That plus a $5 bill gets me a Happy Meal at McDonalds, but in a post-Altera world, it might be worth more.

On January 16, 2008, I’m sitting in a meeting with some Intel strategic marketing… Read More


High Level Synthesis. Are We There Yet?

High Level Synthesis. Are We There Yet?
by Paul McLellan on 06-16-2015 at 7:00 am

High level synthesis (HLS) seems to have been part of the backdrop of design automation for so long that it seems to be one of those things that nobody notices any more. But it has also crept up on people and gone from interesting technology to keep an eye on to getting genuine adoption. The first commercial product in the space was behavioral… Read More


Aldec packs 6 UltraScale parts on HES-7

Aldec packs 6 UltraScale parts on HES-7
by Don Dingee on 06-01-2015 at 12:00 pm

A few months ago, when the Xilinx UltraScale VU440 FPGA began shipping, one of the immediate claims was a quad-FPGA-based prototyping board touted as “Godzilla’s Butcher on Steroids”. That was a refreshing and creative PR approach, frankly. I’m always careful with less creative terms like “world’s biggest” or “world’s fastest”,… Read More


Will Dark Silicon Dictate Server Blade Architecture?

Will Dark Silicon Dictate Server Blade Architecture?
by Tom Simon on 05-27-2015 at 7:00 pm

Does the evil sounding phenomenon known as Dark Silicon create a big opportunity for FPGA vendors as was predicted recently by Pacific Crest Securities? John Vinh posits that using multiple cores as a method of scaling throughput is flattening out, and the use of FPGA’s to perform computation can help off-load and thus overcome… Read More


Taking a Leap Forward to Prototype Billion Gate Designs

Taking a Leap Forward to Prototype Billion Gate Designs
by Pawan Fangaria on 05-26-2015 at 12:00 pm

It’s very common these days to hear about a billion gates SoC, but not without a huge design and verification effort and investment of resources. A complete verification of such an SoC needs several verification steps including software and hardware based methodologies that often are not sufficient to cover the whole SoC. In order… Read More


New Vivado release goes from Lab to UltraScale

New Vivado release goes from Lab to UltraScale
by Don Dingee on 05-06-2015 at 1:00 am

Xilinx users will welcome the brand-new release of Vivado Design Suite 2015.1. For openers, device support for the latest FPGAs in the UltraScale family – XCVU440, XCVU190, and XCVU125 – has been added in the release, and early access code for the XCVU160 is available from a local Xilinx FAE. Installation has been streamlined, … Read More


Xilinx at NAB: Any Media Over Any Network

Xilinx at NAB: Any Media Over Any Network
by Paul McLellan on 04-11-2015 at 7:00 am

The NAB (National Association of Broadcasters) show has just started, April 11-16th in Las Vegas. It covers a very broad range of topics:
As the premier trade association for broadcasters, NAB advances the interests of our members in federal government, industry and public affairs; improves the quality and profitability of Read More


Intel to Buy Altera?

Intel to Buy Altera?
by Paul McLellan on 03-28-2015 at 1:05 pm

You may already have heard today’s big news in the semiconductor fabless ecosystem that Intel is apparently in talks to buy Altera. I embarrassed myself predicting that Samsung were in talks to buy Freescale (which, of course, they might have been but NXP won that particular race). But this time it is definite enough that … Read More


CDC Verification: A Must for IP and SoCs

CDC Verification: A Must for IP and SoCs
by Pawan Fangaria on 03-12-2015 at 1:00 pm

In the modern SoC era, verification is no longer a post-design activity. The verification strategy must be planned much earlier in the design cycle; otherwise the verification closure can become a never ending problem. Moreover, verification which appears to be complete may actually be incomplete because of undetected issues… Read More