Webinar: Maximize Productivity with Deep Insights into PPA Trajectories

Webinar: Maximize Productivity with Deep Insights into PPA Trajectories
by Admin on 05-30-2024 at 3:18 pm

The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to 

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Webinar: Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing

Webinar: Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing
by Admin on 05-30-2024 at 3:15 pm

Today’s advanced node chip designs are faced with many new complexities which require more verification, more validation and more analysis. The resulting data from these added steps has also grown exponentially and engineers need a way to efficiently analyze this information. The result is a new paradigm shift which has led

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Synopsys Design IP for Modern SoCs and Multi-Die Systems

Synopsys Design IP for Modern SoCs and Multi-Die Systems
by Kalar Rajendiran on 04-11-2024 at 10:00 am

Synopsys IP Scale, a Sustainable Advantage

Semiconductor intellectual property (IP) plays a critical role in modern system-on-chip (SoC) designs. That’s not surprising given that modern SoCs are highly complex designs that leverage already proven building blocks such as processors, interfaces, foundational IP, on-chip bus fabrics, security IP, and others. This… Read More


Webinar: Automating the Integration Workflow with IP Centric Design

Webinar: Automating the Integration Workflow with IP Centric Design
by Admin on 04-08-2024 at 3:14 pm

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During a project, subsystem and full-chip integration plays a crucial role. Integration can be particularly challenging on large SoCs with distributed teams due to complexity of the integration process, multi-site infrastructure issues, as well as the need to collaborate … Read More


Webinar: Enabling SoC Security and Reliability for HPC, AI & IoT with NVM OTP IP in TSMC N5

Webinar: Enabling SoC Security and Reliability for HPC, AI & IoT with NVM OTP IP in TSMC N5
by Admin on 03-26-2024 at 2:23 pm

Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb of repair information to meet yield requirements. Designers are facing the challenges of creating secure,

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ISO 21434 for Cybersecurity-Aware SoC Development

ISO 21434 for Cybersecurity-Aware SoC Development
by Kalar Rajendiran on 08-31-2023 at 10:00 am

Cybersecurity agreement in supply chain

The automotive industry is undergoing a remarkable transformation, with vehicles becoming more connected, automated, and reliant on software. While these advancements promise convenience, comfort and efficiency to the consumers, the nature and complexity of the technologies also raise concerns for functional safety … Read More


Silicon Catalyst and Arm announce $150,000 Silicon Startup Contest!

Silicon Catalyst and Arm announce $150,000 Silicon Startup Contest!
by Daniel Nenni on 05-10-2023 at 6:00 am

Silicon Catalyst Arm contest 400x400

As I sift through mounds of semiconductor press releases trying to figure out the relevance (with mixed results) I consider it a learning experience even when they don’t really tell me anything. This one however tells me two very important things:

1) Arm is a much more competitive company with the new leadership. I saw a noticeable… Read More


Speeding up Chiplet-Based Design Through Hardware Emulation

Speeding up Chiplet-Based Design Through Hardware Emulation
by Kalar Rajendiran on 02-16-2023 at 10:00 am

Barriers on the Continuum to SiP

The first chiplets focused summit took place last month. So many accomplished speakers gave keynote talks on what direction should and would the Chiplets ecosystem evolution take. Corigine presented the keynote on what direction hardware emulation should and would evolve for speeding up chiplet- based designs. During a pre-conference… Read More


Achieving 400W Thermal Envelope for AI Datacenter SoCs

Achieving 400W Thermal Envelope for AI Datacenter SoCs
by Kalar Rajendiran on 12-05-2022 at 10:00 am

Alchip BlockDiagram Oct 26 2022 tsmc na oip presentation

Successful ASIC providers offer top-notch infrastructure and methodologies that can accommodate varied demands from a multitude of customers. Such ASIC providers also need access to best-in-class IP portfolio, advanced packaging and test capabilities, and heterogeneous chiplet integration capability among other things.… Read More