Webinar: Improving your in-system test quality with in-system deterministic test

Webinar: Improving your in-system test quality with in-system deterministic test
by admin on 10-02-2024 at 1:31 am

As the Semiconductor industry continues to change and evolve, requirements for test continue to extend from manufacturing into in-system as part of a growing SLM strategy. The growing need to increase the quality of in-system testing capabilities is driving a shift in technology.

Thanks to new innovation, it is now possible … Read More


Podcast EP231: Details of the New Solido Simulation Suite with Sathish Balasubramanian

Podcast EP231: Details of the New Solido Simulation Suite with Sathish Balasubramanian
by Daniel Nenni on 06-27-2024 at 8:00 am

Dan is joined by Sathishkumar Balasubramanian. Sathish currently leads the product management and marketing organization for CustomIC Verification (CICV) division at Siemens. Sathish is an experienced product leader with over 20+ years of experience in the EDA industry.

Sathish’s focus is on bringing value to the semiconductor… Read More


The True Power of the TSMC Ecosystem!

The True Power of the TSMC Ecosystem!
by Daniel Nenni on 10-02-2023 at 6:00 am

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The 15th TSMC Open Innovation Platform® (OIP) was held last week. In preparation we did a podcast with one of the original members of the TSMC OIP team Dan Kochpatcharin. Dan and I talked about the early days before OIP when we did reference flows together. Around 20 years ago I did a career pivot and focused on Strategic Foundry Relationships.… Read More


Podcast EP178: An Overview of Advanced Power Optimization at Synopsys with William Ruby

Podcast EP178: An Overview of Advanced Power Optimization at Synopsys with William Ruby
by Daniel Nenni on 08-25-2023 at 10:00 am

Dan is joined by William Ruby, director of product management for Synopsys Power Analysis products. He has extensive experience in the area of low-power IC design and design methodology, and has held senior engineering and product marketing positions with Cadence, ANSYS, Intel, and Siemens. He also has a patent in high-speed… Read More


Using Linting to Write Error-Free Testbench Code

Using Linting to Write Error-Free Testbench Code
by Daniel Nenni on 08-23-2023 at 10:00 am

AMIQ EDA Design and Verification

In my job, I have the privilege to talk to hundreds of interesting companies in many areas of semiconductor development. One of the most fun things for me is interviewing customers—hands-on users—of specific electronic design (EDA) tools and chip technologies. Cristian Amitroaie, CEO of AMIQ EDA, has been very helpful in introducing… Read More


Convergence Between EDA and MCAD and Industrial Software

Convergence Between EDA and MCAD and Industrial Software
by Bernard Murphy on 07-25-2023 at 6:00 am

convergence eda mcad etc min

Cadence hosted a panel at DAC on how EDA, MCAD and industrial software have come together, a topic I always find interesting. Many years ago, I worked on a NAVAIR contract bid team, an eye-opener for a young engineer who thought that innovation started and ended with electronic design. I remember CATIA (3D modeling) being a component… Read More


Pushing Acceleration to the Edge

Pushing Acceleration to the Edge
by Dave Bursky on 11-04-2022 at 6:00 am

performane table siemens eda

As more AI applications turn to edge computing to reduce latencies, the need for more computational performance at the edge continues to increase. However, commodity compute engines don’t have enough compute power or are too power-hungry to meet the needs of edge systems. Thus, when designing AI accelerators for the edge, Joe… Read More


The Increasing Gaps in PLM Systems with Handling Electronics

The Increasing Gaps in PLM Systems with Handling Electronics
by Rahul Razdan on 10-10-2022 at 6:00 am

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Product LifeCycle Management (PLM) systems have shown incredible value for integrating the enterprise with a single view of the product design, deployment, maintenance, and end-of-life processes.  PLM systems have traditionally grown from the mechanical design space, and this still forms their strength.

Meanwhile, due… Read More


Designing a FinFET Test Chip for Radiation Threats

Designing a FinFET Test Chip for Radiation Threats
by Tom Simon on 04-04-2022 at 10:00 am

Charged Particles

Much of the technology that goes into aerospace applications is some of the most advanced technology that exists. However, these same systems must also offer the highest level of reliability in what is arguably an extremely difficult environment. For semiconductors a major environmental risk in aerospace applications are … Read More


Balancing Test Requirements with SOC Security

Balancing Test Requirements with SOC Security
by Tom Simon on 03-17-2022 at 6:00 am

Secure Test for SOCs

Typically, there is an existential rift between the on-chip access requirements for test and the need for security in SoCs. Using traditional deterministic scan techniques has meant opening up full read and write access to the flops in a design through the scan chains. Having this kind of access easily defeats the best designed… Read More