Cadence Design Systems @ #54DAC!

Cadence Design Systems @ #54DAC!
by Daniel Nenni on 06-11-2017 at 8:00 am

This year Cadence Design Systems is showcasing system design enablement in their booth, capitalizing on the industry shift from naked chip design to system level chip design. Apple started it with making the chips inside the iProducts as part of the system and now other systems companies are looking to take more control over their… Read More


Noise, The Need for Speed, and Machine Learning

Noise, The Need for Speed, and Machine Learning
by Riko Radojcic on 05-08-2017 at 7:00 am

Technology trends make the concerns with electronic noise a primary constraint that impacts many mainstream products, driving the need for “Design-for-Noise” practices. That is, scaling, and the associated reduction in the device operating voltage and current, in effect magnifies the relative importance of non-scalableRead More


1.2 Terabit/s C2C Interface? Only with Interlaken!

1.2 Terabit/s C2C Interface? Only with Interlaken!
by Eric Esteve on 04-24-2017 at 7:00 am

If you are familiar with high bandwidth networking applications, you probably know this chip-to-chip (C2C) interface protocol. Interlaken architecture, fully flexible, configurable and scalable, is also an elegant answer to the need for very high bandwidth C2C communication. Interlaken is elegant because the protocol … Read More


Attending DAC in Austin for Free

Attending DAC in Austin for Free
by Daniel Payne on 04-23-2017 at 7:00 am

I’ve been attending DAC since the late 1980’s and can tell you that it’s an annual highlight for me and anyone else interested in the EDA, IP and semiconductor industries. Where else can you see most of the big and little vendors of EDA software, semiconductor IP and foundries in one place? I recently blogged aboutRead More


eFabless Design Challenge Results!

eFabless Design Challenge Results!
by Daniel Nenni on 03-28-2017 at 7:00 am

Will community engineering work for semiconductors? Will anyone show up? Well, the efabless design challenge is complete and the results are both interesting and encouraging, absolutely!

Efabless completed its low power voltage reference IP design challenge on Monday, March 13. This was a very interesting event that we followed… Read More


Open-Silicon Update: 125M ASICs shipped!

Open-Silicon Update: 125M ASICs shipped!
by Daniel Nenni on 02-03-2017 at 12:00 pm

As you all know I am a big fan of the ASIC business model. It was critical in the transformation of the fabless semiconductor industry and still plays a critical part in our success. In fact, the ASIC business model is leading the way for systems companies to make their own chips. Remember, Apple started with the ASIC business model … Read More


Another Interesting Thing From TSMC!

Another Interesting Thing From TSMC!
by Daniel Nenni on 01-21-2017 at 7:00 am

As I mentioned in my previous post, the TSMC investor call this month was very interesting and Morris Chang was in fine form during the Q&A. As a semiconductor professional I think some of the questions are ridiculous but maybe they have value to the financial people. This one question from Randy, who I think is very astute, is … Read More