Increasingly, a GPU is misnamed as a “graphics” processing unit. They are really specialized architecture highly parallel compute engines. You can use these compute engines for graphics, of course, but people are inventive and find ways of using GPUs for other tasks that can take advantage of the highly parallel… Read More
It is beginning to look as if 28nm transistors, which are the cheapest per million gates compared to any earlier process such as 45nm, may also be the cheapest per million gates compared to any later process such as 20nm.
What we know so far: FinFET seems to be difficult technology because of the 3D structure and so the novel manufacturing… Read More
Designing an LTE modem is an interesting case study in architectural and system level design because it is pretty much on the limit of what is possible in a current process node such as 28nm. I talked to Johannes Stahl of Synopsys about how you would accomplish this with the Synopsys suite of system level tools. He is the first to admit… Read More
At IDF Brian Krzanich gave the keynote. I won’t summarize the whole thing here but just talk about one part that was something they had actually managed to keep secret ahead of time: Quark.
Quark is a synthesizable core. It uses 1/10th power of Atom and is 1/5 size. Now I am writing this, I don’t know if this is a fair comparison… Read More
GlobalFoundries has been in Singapore for a long time. Longer than GlobalFoundries has existed in fact. Chartered Semiconductor was started in Singapore in 1987 and GF acquired them in early 2010 less than a year after they were created by spinning out the manufacturing arm of AMD. When GF was started their state of the art fab was… Read More
At TSMC’s OIP on October 1st, Mentor Graphics have 5 different presentations. Collect the whole set!
11am, EDA track. Design Reliability with Calibre Smartfill and PERC. Muni Mohan of Broadcom and Jeff Wilson of Mentor. New methodologies were invented for 28nm for smart fill meeting DFM requirements (and at 20nm me may … Read More
As more people adopt high-level synthesis (HLS) they start to worry about what is the best design flow to be using. This is especially so for verification since it forms such a large part of the effort on a modern SoC. The more people rely on HLS for producing their RTL from C, the more they realize they had better do a good job of verifying… Read More
Almost without exception these days, semiconductor products face strict power and thermal budgets. Of course there are many issues with dynamic power but one big area that has been getting increasingly problematic is static power. For various technical reasons we can no longer reduce the voltage as much as we would like from one… Read More
For decades we have used a model of faults in chips that assumes that a given signal is stuck-at-0 or stuck-at-1. And when I say decades, I mean it. The D-algorithm was invented at IBM in 1966, the year after Gordon Moore made a now very famous observation about the number of transistors on an integrated circuit. We know that stuck-at… Read More
Handsets moved away from fixed architecture DSP some time ago, driven by two main factors. Fixed architecture DSP consumed too much power to get good battery life in the smart-phone era, but the consumer air interface was changing fast: W-CDMA, HSPA, WiMax, 3G, LTE (which is actually a whole ‘spectrum’ of different… Read More
