Low Power Webinar Series

Low Power Webinar Series
by Paul McLellan on 07-08-2011 at 4:57 pm

At DAC 2011 in San Diego, Apache gave many product presentations. Of course not everyone could make DAC or could make all the presentations in which they were interested. So from mid-July until mid-August these presentations will be given as webinars. Details, and links for registration, are here on the Apache website.

The seminars… Read More


ARM and Mentor Team Up on Test

ARM and Mentor Team Up on Test
by Daniel Payne on 06-27-2011 at 2:31 pm

Introduction
Before DAC I met with Stephen Pateras, Ph.D. at Mentor Graphics, he is the Product Marketing Director in the Silicon Test Solutions group. Stephen has been at Mentor for two years and was part of the LogicVision acquisition. He was in early at LogicVision and went through their IPO, before that he was at IBM in the mainframe… Read More


TSMC Versus Intel: The Race to Semiconductors in 3D!

TSMC Versus Intel: The Race to Semiconductors in 3D!
by Daniel Nenni on 06-26-2011 at 4:00 pm

While Intel is doing victory laps in the race to a 3D transistor (FinFet) @ 22nm, TSMC is in production with 3D IC technology. A 3D IC is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The question is which 3D race is more important to the semiconductor… Read More


OpenAccess

OpenAccess
by Paul McLellan on 06-21-2011 at 1:11 pm

Probably everyone knows that openAccess is a layout database. It was originally developed at Cadence (called Genesis) but has since been transferred to Si2. Strictly speaking, openAccess is actually an API and the database is a reference implementation. The code is licensed under a sort of halfway to open-source: you can use … Read More


Can Your Router Handle 28 nm?

Can Your Router Handle 28 nm?
by Beth Martin on 06-20-2011 at 7:11 pm

attachment

With the adoption of the 32/28 nm process node, some significant new challenges in digital routing arise—including complex design rule checking (DRC) and design for manufacturing (DFM) rules, increasing rule counts, very large (1 billion transistor) designs. To meet quality, time-to-market, and cost targets, design teams… Read More


HSPICE gets Faster, better Convergence

HSPICE gets Faster, better Convergence
by Daniel Payne on 06-13-2011 at 5:53 pm

Hany El Hak – Product Marketing Manager

Frederik Iverson – AE

Scott Wetch – HSPICE Architect

HSPICE – 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.

Synopsys AMS Portfolio – wide range of tools
– Custom Designer: IC schematic and layout tools
–… Read More


Sagantec 2 Migrate iPad2s @ #48DAC

Sagantec 2 Migrate iPad2s @ #48DAC
by admin on 05-30-2011 at 2:53 pm

Sagantec is the leading EDA provider of process migration solutions for custom IC design. Sagantec’s EDA solutions enable IC designers to leverage their investment in existing physical design IP and accomplish dramatic time and effort savings in the implementation of custom, analog, mixed-signal and memory circuits… Read More


65nm to 45nm SerDes IP Migration Success Story

65nm to 45nm SerDes IP Migration Success Story
by Daniel Nenni on 05-25-2011 at 3:43 pm

The problem:To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintainedRead More


3D IC @ #48DAC

3D IC @ #48DAC
by Daniel Nenni on 05-23-2011 at 4:54 pm

A three-dimensional integrated circuit (3D IC ) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this emerging technology in many different forms, as a result the full definition is still somewhat… Read More


Analyzing and Planning Electro-static Discharge (ESD) Protection

Analyzing and Planning Electro-static Discharge (ESD) Protection
by Paul McLellan on 05-23-2011 at 5:00 am

ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.

Pathfinder is the first full-chip comprehensive ESD planning and verification solution. It is targeted to address limitations in today’s methodologies.… Read More