PCI Express in Depth – Transaction Layer

PCI Express in Depth – Transaction Layer
by Luigi Filho on 09-06-2020 at 7:00 am

PCI Express in Depth Transaction Layer

In the last article i write about the Data Link Layer, in this article i’ll write about the Transaction Layer.

This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions.… Read More


PCI Express in Depth – Data Link Layer

PCI Express in Depth – Data Link Layer
by Luigi Filho on 09-06-2020 at 6:00 am

PCI Express in Depth Data Link Layer

In the last article, i wrote about the physical layer, now let’s take a look in the next layer the data link layer.

The Data Link Layer serves as the “gatekeeper” for each individual link within a PCI Express system. It ensures that the data being sent back and forth across the link is correct and received in the same order it

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CEO Interview: Ted Tewksbury of Eta Compute

CEO Interview: Ted Tewksbury of Eta Compute
by Daniel Nenni on 08-11-2020 at 10:00 am

Ted Tewksbury President CEO Eta Compute

Tell me about Eta Compute’s vision? 
We envision a world where intelligent devices at the network edge make everyones’ lives safer, healthier, more comfortable, and convenient without sacrificing privacy and security.

How do you hope to achieve this? 
We achieve this by providing the lowest power and most energy efficient machine… Read More


Accelerating High-Performance Computing SoC Designs with Synopsys IP

Accelerating High-Performance Computing SoC Designs with Synopsys IP
by Daniel Nenni on 07-22-2020 at 6:00 am

Synopsys DesignWare IP

Semiconductor IP is one of the most talked about topics on SemiWiki. Always has been, always will be. Synopsys is also one of the most talked about topics on SemiWiki and IP is a very big part of that, absolutely.

After reading Eric Esteve’s latest IP Report I Googled around and found some interesting things. First, I found a Brief HistoryRead More


CEO Interview: Deepak Kumar Tala of SmartDV

CEO Interview: Deepak Kumar Tala of SmartDV
by Daniel Nenni on 06-22-2020 at 10:00 am

SmartDV CEO Interview 2020

SMARTDV is one of the biggest small EDA companies in the industry today in regards to products, customers and number of licenses in use, absolutely. They have a portfolio of more than 600 Design & Verification Solutions, everything from Design & Verification IP to Formal Verification IP, Post-Silicon Verification IP… Read More


Fractal CEO Update 2020

Fractal CEO Update 2020
by Daniel Nenni on 06-16-2020 at 10:00 am

Fractal Technologies SemiWiki

Rene Donkers, the company’s Co-founder and CEO, started his EDA career at Sagantec where he became responsible for world wide customer support and operations management. Ten years ago, Rene and a handful of people noticed a need in the design community for a standardized (portable) IP Validation approach to replace internal… Read More


Talking Sense With Moortec…Speak No Evil!

Talking Sense With Moortec…Speak No Evil!
by Tim Penhale-Jones on 06-08-2020 at 10:00 am

Speak no Evil Moortec

In the first of this blog trilogy, Talking Sense with Moortec…’Are you listening’,  I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time. In the second, Talking Sense with Moortec…’See no evil’, we bizarrely saw how Sir Francis Drake, Admiral Nelson and Clint… Read More


PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support

PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support
by Mike Gianfagna on 05-28-2020 at 10:00 am

Screen Shot 2020 05 07 at 7.06.36 PM

A couple of months ago I introduced PLDA, a new member of the SemiWiki community, with a post about PLDA’s switch IP and its support for PCIe and NVMe solid state disks. Working in the area of high-performance data interconnects requires support for a growing list of standards, standards that continually evolve. The trick is to stay… Read More


Filling the ASIC Void – Part 2

Filling the ASIC Void – Part 2
by Mike Gianfagna on 04-03-2020 at 6:00 am

Screen Shot 2020 03 24 at 5.00.49 PM

I concluded my last post on the topic with an inventory of the key attributes needed to fill the ASIC void created by the relentless consolidation in semiconductors. There were five items, as follows:

  1. Design and manufacturing expertise in a market that requires custom chips
  2. Differentiating IP and the skills to integrate it into
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Filling the ASIC Void – Part 1

Filling the ASIC Void – Part 1
by Mike Gianfagna on 03-27-2020 at 6:00 am

shutterstock 235025512

It started slowly at first.  Then it began picking up steam. I’m referring to consolidation in the semiconductor sector. I had a front-row seat for what consolidation did to the ASIC part of semiconductor and that is the topic of this discussion. I was the VP of marketing at eSilicon, the company that invented the fabless ASIC model.… Read More