SOCFIT, Circuit Level Soft Error Analysis

SOCFIT, Circuit Level Soft Error Analysis
by Paul McLellan on 05-13-2013 at 2:50 pm

I blogged recently about reliability testing with high energy neutron beams. This is good for getting basic reliability data but it is not really a useful tool for worrying about reliability while the chip is still being designed and something can be done about it.

That is where IROC Technologies SOCFIT tool comes in. It takes all… Read More


How to Blast Your Chip with High Energy Neutron Beams

How to Blast Your Chip with High Energy Neutron Beams
by Paul McLellan on 05-06-2013 at 3:49 pm

So you want to know how reliable your chips are and how susceptible they are to single event effects (SEEs) where a neutron or an alpha particle causes a storage element (flop or memory cell) to flip in a way that alters the behavior of the device. There are two ways a particle hitting a device might not cause a problem. Firstly, the particle… Read More


Cell Level Reliability

Cell Level Reliability
by Paul McLellan on 04-03-2013 at 6:06 pm

I blogged last month about single event effects (SEE) where a semiconductor chip behaves incorrectly due to being hit by an ion or a neutron. Since we live on a radioactive planet and are bombarded by cosmic rays from space, this is a real problem, and it is getting worse at each process node. But just how big of a problem is it?


TFIT is … Read More


Reliability is the New Power

Reliability is the New Power
by Paul McLellan on 03-09-2013 at 9:56 am

It has be come a cliche to say that “power is the new timing”, the thing that keeps designers up at night and drives the major architectural decisions in big SoCs. Nobody is saying it yet but perhaps “reliability is the new power” will be tomorrow’s received wisdom.

I talked to Adrian Evans of IROCTech… Read More


We Live on a Radioactive Planet

We Live on a Radioactive Planet
by Paul McLellan on 03-01-2013 at 1:45 pm

Often as we move down the process node treadmill, new challenges appear that we didn’t really have to worry about before. Often, these challenges require addressing at a number of different levels: the process, the cell libraries, the design, the EDA tools that we use.

One well known example is the problem of metal migration.… Read More


Power and Reliability Challenges

Power and Reliability Challenges
by Paul McLellan on 10-23-2012 at 12:38 pm

Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.

The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More


Have You Ever Heard of the Carrington Event? Will Your Chips Survive Another?

Have You Ever Heard of the Carrington Event? Will Your Chips Survive Another?
by Paul McLellan on 09-06-2012 at 9:07 pm

In one of those odd coincidences, I was having dinner with a friend last week and somehow the Carrington Event came up. Then I read a a piece in EETimesabout whether electrical storms could cause problems in the near future. Even that piece didn’t mention the Carrington Event so I guess George Leopold, the author, hasn’t… Read More


Designing for Reliability

Designing for Reliability
by Paul McLellan on 04-08-2012 at 8:06 pm

Analyzing the operation of a modern SoC, especially analyzing its power distribution network (PDN) is getting more and more complex. Today’s SoCs no longer operate on a continuous basis, instead functional blocks on the IC are only powered up to execute the operation that is required and then they go into a standby mode, … Read More


Challenges in 3D-IC and 2½D Design

Challenges in 3D-IC and 2½D Design
by Paul McLellan on 12-09-2011 at 5:18 pm

3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges

The power delivery network is a challenge… Read More


Totem webinar: Analog/Mixed-Signal Power Noise and Reliability

Totem webinar: Analog/Mixed-Signal Power Noise and Reliability
by Paul McLellan on 07-30-2011 at 5:26 pm

The Totem webinar will be at 11am on Tuesday 2nd August. This session will be conducted by Karan Sahni, Senior Applications Engineer at Apache Design Solutions. Karan has been with Apache since 2008, supporting the Redhawk, Totem, Sentinel product lines. He received his MS in Electrical Engineering from the Syracuse University… Read More