Getting to the 32nm/28nm Common Platform node with Mentor IC Tools

Getting to the 32nm/28nm Common Platform node with Mentor IC Tools
by Daniel Payne on 01-17-2011 at 6:04 pm

Last week I talked with two experts at Mentor about the challenges of getting IC designs into the 32nm/28nm node on the Common Platform (IBM, GLOBALFOUNDRIES and Samsung). Global Foundries issued a press release talking about how the four major EDA companies have worked together to qualify EDA tools for this node.

Sudhakar Jilla,… Read More


The Future of Semiconductor Design!

The Future of Semiconductor Design!
by Daniel Nenni on 12-26-2010 at 10:15 pm

Is EDA still an appropriate term for what we do? What applications will drive future semiconductor design innovation? Will further consolidation be required for EDA to thrive again? They are all good questions, questions that will hopefully be properly addressed at the EDAC CEO Forecast and Industry Vision event next week but… Read More


Mentor – Cadence Merger and the Federal Trade Commission

Mentor – Cadence Merger and the Federal Trade Commission
by Daniel Nenni on 12-12-2010 at 5:33 pm


More consolidation is coming to EDA and so is the Federal Trade Commission. Corporate raider Carl Ichan owns 15% of Mentor Graphics and now owns 1% of Cadence. Ichan buddy multi billionaire George Soros, a long time CDNS investor, just purchased more than 76 million convertible notes of MENT.You do the math…

Unfortunately the FTC… Read More


Computational Lithography, Scaling’s Best Friend

Computational Lithography, Scaling’s Best Friend
by glforte on 11-03-2010 at 11:51 pm

By Joseph Sawicki, Vice President & General Manager, Design to Silicon Division

It is one of the more amazing stories in the continued march of Moore’s Law over the past four nodes. Previously scaling was enabled solely though changes in the physical domain, whether through decreasing the wavelength of light, increasing … Read More


Critical Area Analysis and Memory Redundancy

Critical Area Analysis and Memory Redundancy
by SStalnaker on 10-08-2010 at 8:08 pm

Simon Favre, one of our Calibre Technical Marketing Engineers, presented a paper on Critical Area Analysis and Memory Redundancy at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. As Simon says…

Fishkill, New York. IBM is in Fishkill. IBM invented Critical Area Analysis in what,… Read More