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• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator?
• Do you need to size the AI accelerator for existing and future AI requirements?
• Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks?
This webinar focuses on design teams… Read More
I had the pleasure of spending time with Hiren Majmudar in preparation for the upcoming AI Accelerators webinar. As far as webinars go this will be one of the better ones we have done. Hiren has deep experience in both semiconductors and EDA during his lengthy career at Intel and now with a pure play foundry. He is intelligent, personable,… Read More
The Interface Design IP market explodes, growing by 18% in 2019, with $870 million, when CPU IP category grew by 5% at $1,460 million. In fact, Interface IP market is forecasted to sustain high growth rate for the next five years, as calculated by IPnest in the “Interface IP Survey 2015-2019 & Forecast 2020-2024”, to reach $1,800… Read More
The design of parallel interfaces is supposed to be (comparatively) easy — e.g., follow a few printed circuit board routing guidelines; pay attention to data/clock/strobe signal lengths and shielding; ensure good current return paths (avoid discontinuities); match the terminating resistances to the PCB trace impedance;… Read More
