Securing Memory Interfaces

Securing Memory Interfaces
by Kalar Rajendiran on 03-30-2023 at 10:00 am

synopsys secure ddr controller with ime

News of hackers breaking into systems is becoming common place these days. While many of the breaches reported to date may have been due to security flaws in software, vulnerabilities exist in hardware too. As a result, the topic of security is getting increased attention within the semiconductor industry around system-on-chip… Read More


Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)

Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
by Daniel Nenni on 02-18-2022 at 8:42 am

• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator?

• Do you need to size the AI accelerator for existing and future AI requirements?

• Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks?

This webinar focuses on design teams… Read More


Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions

Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions
by Daniel Nenni on 07-29-2020 at 10:00 am

Globalfoundries AI Webinar Hiren Majmudar

I had the pleasure of spending time with Hiren Majmudar in preparation for the upcoming AI Accelerators webinar. As far as webinars go this will be one of the better ones we have done. Hiren has deep experience in both semiconductors and EDA during his lengthy career at Intel and now with a pure play foundry. He is intelligent, personable,… Read More


Interface IP Category to Overtake CPU IP by 2025?

Interface IP Category to Overtake CPU IP by 2025?
by Eric Esteve on 07-09-2020 at 6:00 am

Top 5 Forecast 2020 2024

The Interface Design IP market explodes, growing by 18% in 2019, with $870 million, when CPU IP category grew by 5% at $1,460 million. In fact, Interface IP market is forecasted to sustain high growth rate for the next five years, as calculated by IPnest in the “Interface IP Survey 2015-2019 & Forecast 2020-2024”, to reach $1,800… Read More


DDR4 is a complex interface to verify — assistance needed!

DDR4 is a complex interface to verify — assistance needed!
by Tom Dillinger on 02-16-2016 at 7:00 am

The design of parallel interfaces is supposed to be (comparatively) easy — e.g., follow a few printed circuit board routing guidelines; pay attention to data/clock/strobe signal lengths and shielding; ensure good current return paths (avoid discontinuities); match the terminating resistances to the PCB trace impedance;… Read More