A Look at the Die of the 8086 Processor

A Look at the Die of the 8086 Processor
by Ken Shirriff on 07-15-2020 at 6:00 am

Intel 8086 Die

The Intel 8086 microprocessor was introduced 42 years ago last month,1 so I made some high-res die photos of the chip to celebrate. The 8086 is one of the most influential chips ever created; it started the x86 architecture that still dominates desktop and server computing today. By looking at the chip’s silicon, we can see… Read More


Intel Designs Chips to Protect from ROP Attacks

Intel Designs Chips to Protect from ROP Attacks
by Matthew Rosenquist on 06-28-2020 at 10:00 am

Intel Designs Chips to Protect from ROP Attacks

Intel comes late to the game but will be delivering an embedded defense for Return Oriented Programming (ROP) types of cyber hacks. I first blogged about this back in Sept of 2016. Yes, almost four years have passed and I had hoped it would see the light of day much earlier.

The feature, to debut in the Tiger Lake microarchitecture… Read More


Effect of Design on Transistor Density

Effect of Design on Transistor Density
by Scotten Jones on 05-26-2020 at 10:00 am

TSMC N7 Density Analysis SemiWiki

I have written a lot of articles looking at leading edge processes and comparing the process density. One comment I often get are that the process density numbers I present do not correlate with the actual transistor density on released products. A lot of people want to draw conclusions an Intel’s processes versus TSMC’s processes… Read More


Our US chip foundry comments confirmed by WSJ

Our US chip foundry comments confirmed by WSJ
by Robert Maire on 05-11-2020 at 10:00 am

Trump Intel TSMC China TAiwan

-Could GloFo come back?
-TSMC or Intel or both or neither?
-Samsung would be a long shot?
-Perhaps Apple could convince TSMC?

The Wall Street Journal put out an article that detailed what we had indicated in our newsletter 10 days ago, that the US government is looking at getting a US based foundry to protect our interests given our … Read More


Reliable Line Cutting for Spacer-based Patterning

Reliable Line Cutting for Spacer-based Patterning
by Fred Chen on 05-06-2020 at 6:00 am

Reliable Line Cutting for Spacer based Patterning

Spacer-defined patterning is an expected requirement for advanced semiconductor patterning nodes with feature sizes of 25 nm or less. As the required gaps between features go well below the lithography tool’s resolution limit, the use of cut exposures to separate features is used more often, especially in chips produced… Read More


Can TSMC Maintain Their Process Technology Lead

Can TSMC Maintain Their Process Technology Lead
by Scotten Jones on 04-29-2020 at 10:00 am

TSMC Process Lead Slides 20200427 Page 1

Recently Seeking Alpha published an article “Taiwan Semiconductor Manufacturing Company Losing Its Process Leadership To Intel” and Dan Nenni (SemiWiki founder) asked me to take a look at the article and do my own analysis. This is a subject I have followed and published on for many years.

Before I dig into specific process density… Read More


Short vs Long Term Covid19 Impact

Short vs Long Term Covid19 Impact
by Robert Maire on 04-19-2020 at 10:00 am

Covid Semiconductor

-Short term Covid19 impact is primarily logistics related
-Longer term impact is more systemic/demand driven
-Impact will wind through supply chain over several qtrs
-Other issues, such as trade, remain an overhang

Short term versus long term in the semiconductor industry
The stocks declines over the last months seem to indicate… Read More


LithoVision – Economics in the 3D Era

LithoVision – Economics in the 3D Era
by Scotten Jones on 03-04-2020 at 6:00 am

Slide3

Each year on the Sunday before the SPIE Advanced Lithography Conference, Nikon holds their LithoVision event. This year I had the privilege of being invited to speak for the third consecutive year, unfortunately, the event had to be canceled due to concerns over the COVID-19 virus but by the time the event was canceled I had already… Read More


System Level Flows for SoC Architecture Analysis and Design – DVCON 2020

System Level Flows for SoC Architecture Analysis and Design – DVCON 2020
by Daniel Nenni on 02-21-2020 at 6:00 am

CST Header FF SL

As a professional conference attendee I look for the most meaningful way to spend my time and workshops is one of the best. Especially when a customer is involved and there is no bigger EDA customer than Intel, absolutely.

System Level Flows for SoC Architecture Analysis and Design

Speakers:
Swaminathan Ramachandran – … Read More


Insights from the Next FPGA Platform Event

Insights from the Next FPGA Platform Event
by Daniel Nenni on 02-11-2020 at 10:00 am

The Next FPGA Platform SemiWiki

Unfortunately, I missed this event since I was in China. Fortunately, Manoj Roge VP Strategic Planning and Business Development at Achronix participated and did a nice write-up. Manoj has more than 20 years of experience in the programable business with Cypress Semiconductor, Xilinx, Altera, and now Achronix so you should definitely… Read More