What is Applied Materials doing in an EDA trade show?
New semiconductor market segments such as AI, automotive and connected devices are growing at an accelerated pace and placing constant increased pressures on the PPAC (power, performance, area, cost) system requirements. In the past, these growing PPAC demands were addressed… Read More
Tag: idrm
Design Rule Development Platform @ #54DAC!
While some might have expected the exponential growth in design rules number and complexity to cool down a little, it looks as if these are only heating up more. The multiplicity of technology nodes, lithography options, , fundamental technology options (Bulk, FD-SOI, FinFET), different process flavors and specific applications,… Read More
iDRM – A Complete Design Rule Development System
Design rules are at the heart of the interface between the foundry and semiconductor designers, which makes them so critical. Traditionally, design rules and DRC decks have been developed manually with no or little automation. Design rule definitions are written using WORD or other general purpose office tools, and DRC decks… Read More
How Good is Your DRC Deck?
Design Rule Check (DRC) is the #1 foundry sign-off check. Fabless companies receive the DRC deck from the foundry; it’s a file comprising thousands of commands in a proprietary checker language for a specific DRC tool. In advanced technologies such a deck executes tens of thousands of geometric operations on the physical… Read More
DRM2PDK: From design rule manual to process design kit
Exactly a year ago Sage Design Automation launched its revolutionary iDRM product, enabling for the first time to graphically capture design rules and compile them into checks automatically – no programming required. Using the graphical design rule editor, users could draw the layout topology that describes the design… Read More
SemiWiki Top 10 Must See @ #50DAC List!
This list was compiled by the SemiWiki bloggers highlighting emerging technologies that we have written about and that will be demonstrated at the Design Automation Conference next week. We highly recommend you investigate them further during your time in Austin and please let us know what you think.
Today SemiWiki has more than… Read More
Avoiding layout related variability issues
In advanced process technologies, electrical and timing problems due to variability can become a big issue. Due to various processing effects, a circuit performance (both speed and power) is dependent on specific layout attributes and can vary a lot from instance to instance. The accumulated effects can be severe to the point… Read More