Tag: esd

Semitracks Course: EOS, ESD and How to Differentiate

Semitracks Course: EOS, ESD and How to Differentiate
by Admin on 06-24-2025 at 9:13 am

Electrical Overstress (EOS) and Electrostatic Discharge (ESD) account for most of the field failures observed in the electronics industry. Although EOS and ESD damage can at times look quite similar to each other, the source each and the solution can be quite different. Therefore, it is important to be able to distinguish between… Read More

Webinar: Communications System Design and Space Environment Effects

Webinar: Communications System Design and Space Environment Effects
by Admin on 05-05-2025 at 7:47 pm

This webinar covers satellite communications, starting from a ground station link and advancing to digital engineering techniques, including phased arrays, interference, and space environment factors. In addition, it explores Space Environmental Effects including Solar Array ESD, Radiation Hardening and RFI of Rocket

… Read More
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Electrical Rule Checking in PCB Tools

Electrical Rule Checking in PCB Tools
by Daniel Payne on 12-10-2024 at 10:00 am
Categories: EDA, Siemens EDA
1 Comment

HyperLynx DRC min

I’ve known about DRC (Design Rule Checking) for IC design, and the same approach can also be applied to PCB design. The continuous evolution of electronics has led to increasingly intricate PCB designs that require Electrical Rule Checking (ERC) to ensure that performance goals are met. This complexity poses several challenges… Read More

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Aniah and Electrical Rule Checking (ERC) #61DAC

Aniah and Electrical Rule Checking (ERC) #61DAC
by Daniel Payne on 08-06-2024 at 10:00 am
Categories: Aniah, EDA

Aniah #61DAC min

Visiting a new EDA vendor at #61DAC is always a treat, because much innovation comes from the start-up companies, instead of the established big four EDA companies. I met with Vincent Bligny, Founder and CEO of Aniah on Wednesday in their booth, to hear about what they are doing differently in EDA. Mr. Bligny has a background working… Read More

EP177: The Certus Approach to Meeting the Challenges of I/O and ESD with Stephen Fairbanks

EP177: The Certus Approach to Meeting the Challenges of I/O and ESD with Stephen Fairbanks
by Daniel Nenni on 08-18-2023 at 10:00 am
Categories: Certus Semiconductor, IP

Dan is joined by Stephen Fairbanks, CEO of Certus Semiconductor. Stephen is an ESD pioneer with over 30 years of experience starting with his time at Intel, SRF Technologies, and now Certus Semiconductor.

Stephen describes the varied challenges of ESD andI/O library design presented by today’s technologies and design… Read More

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Unique IO & ESD Solutions @ DAC 2023!

Unique IO & ESD Solutions @ DAC 2023!
by Daniel Nenni on 06-29-2023 at 6:00 am
Categories: Certus Semiconductor, Events, IP

DAC photo Certus Semiconductor

The semiconductor industry continues to drive innovation and constantly seeks methods to lower costs and improve performance. The advantages of custom I/O libraries versus free libraries can be seen as cost-savings or, more importantly, new markets, new customers, and new business
opportunities.

At DAC 2023, Certus Semiconductor… Read More

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CEO Interview: Stephen Fairbanks of Certus Semiconductor

CEO Interview: Stephen Fairbanks of Certus Semiconductor
by Daniel Nenni on 01-20-2023 at 6:00 am
Categories: Certus Semiconductor, IP

Stephen Fairbanks headshot 1 1

Trained as a semiconductor Analog and RF Circuit Designer, Stephen Fairbanks has been designing and developing process-specific I/O and ESD libraries for 24 years. His foundational training began while attending Brigham Young University designing highspeed 32 GSPS data acquisition systems and RF interfaces for a time-of-flight… Read More

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Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why?

Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why?
by Maxim Ershov on 12-12-2022 at 6:00 am
Categories: Diakopto, EDA

Fig 1

Resistance checks between ESD diode cells and pads or power clamps, and current density analysis for such current flows are commonly used for ESD networks verification [1]. When such simulations use standard post-layout netlists generated by parasitic extraction tools, the calculated resistances may be dramatically higher… Read More

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Methods for Current Density and Point-to-point Resistance Calculations

Methods for Current Density and Point-to-point Resistance Calculations
by Daniel Payne on 05-26-2022 at 10:00 am
Categories: EDA, Siemens EDA
2 Comments

ESD path min

IC reliability is an issue that circuit design engineers and reliability engineers are concerned about, because physical effects like high Current Density (CD) in interconnect layers, or high point-to-point (P2P) resistance on device interconnect can impact reliability, timing or Electrostatic Discharge (ESD) robustness.… Read More

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Magwel Adds Core Device Checking for ESD Verification

Magwel Adds Core Device Checking for ESD Verification
by Tom Simon on 05-11-2021 at 10:00 am
Categories: EDA, Magwel

ESDi-XL Core checking

In the past ESD sign-off has been accomplished by a combination of techniques. Often ESD experts are asked to look at a design and assess its ESD robustness based on experience gained from prior chips. Alternatively, designers are told to work with a set of rules given to them, again based on previous experience about what usually… Read More