Stress and Aging

Stress and Aging
by Bernard Murphy on 04-05-2018 at 12:00 pm

These failings aren’t just a cross we humans bear; they’re also a concern for chips, particularly in electrical over-stress (EOS) and aging of the circuitry. Such concerns are not new, but they are taking on new urgency given the high reliability and long lifetime expectations we have for safety-critical components in cars and… Read More


Robust Reliability Verification – A Critical Addition To Baseline Checks

Robust Reliability Verification – A Critical Addition To Baseline Checks
by Alex Tan on 03-01-2018 at 12:00 pm

Design process retargeting is aImage Removedcommon recurrence based on scaling orBOM(Bill-Of-Material) cost improvement needs. This occursnot only with the availability of foundry process refresh to a more advanced node,but also to any new derivative process node tailored towards matching design complexity, power profileRead More


Stressed out about Electrostatic Discharge (ESD) or Electrical Overstress (EOS)?

Stressed out about Electrostatic Discharge (ESD) or Electrical Overstress (EOS)?
by bkeppens on 07-28-2016 at 12:00 pm

Image RemovedDo not lose sleep worrying that your integrated circuits might fail during EOS/ESD events. Join us for the 38th annual EOS/ESD Symposium in Anaheim, CA in September. Experts on the field will address the latest research on EOS and ESD in the rapidly changing world of electronics.

As electronics continue to become … Read More


How to prevent Electrical Overstress failure in NFC interfaces

How to prevent Electrical Overstress failure in NFC interfaces
by bkeppens on 06-09-2016 at 12:00 pm

Last year, about 40% of new smartphones included Near Field Communication (NFC). Analysts predict that by 2017 there will be 1 billion NFC enabled phones. Clearly, the use of NFC is ramping up because it can simplify aspects as diverse as communication, secure payments, user authentication, and retail loyalty programs for instance.… Read More


Lake Tahoe: The Center of ESD Innovation

Lake Tahoe: The Center of ESD Innovation
by glforte on 03-15-2015 at 1:00 pm

Almost anyone that is active in IC design will be “in touch” with Electrostatic Discharge (ESD) at some time (pun intended). Preventing ESD related IC failures remains something like black magic—at least it’s easy to get that feeling when you are trying to debug ESD failures. I/O and ESD layouts that resulted in excellent robustness… Read More


Know All About ESD and Save Your Chips & Systems

Know All About ESD and Save Your Chips & Systems
by Pawan Fangaria on 08-24-2014 at 7:30 pm

In this age of electronics, especially with so many different types of human held devices and more upcoming wearable devices, it’s utmost important to protect the massive circuitry inside those tiny parts in the devices from ESD related failures. The protection needs to happen at all stages – cells inside the chips, package… Read More


Robust Reliability Verification: Beyond Traditional Tools and Techniques

Robust Reliability Verification: Beyond Traditional Tools and Techniques
by SStalnaker on 05-31-2013 at 7:10 pm

Robust Reliability Verification: Beyond Traditional Tools
by Matthew Hogan, Mentor Graphics

At all process nodes, countless hours are diligently expended to ensure that our integrated circuit (IC) designs will function in the way we intended, can be manufactured with satisfactory yields, and are delivered in a timely fashion… Read More