SOITEC Pushes Substrate Advantages for Edge Inference

SOITEC Pushes Substrate Advantages for Edge Inference
by Bernard Murphy on 02-08-2024 at 6:00 am

FD SOI power min

You might not immediately see a connection between semiconductor substrate choices and inference at the edge. These technology layers seem worlds apart and yet SOITEC have a point. Edge AI has rapidly evolved from simple CNNs to now complex reinforcement learning systems and transformer based LLMs. Even when shrunk to edge footprints,… Read More


Ceva Launches New Brand Identity Reflecting its Focus on Smart Edge IP Innovation

Ceva Launches New Brand Identity Reflecting its Focus on Smart Edge IP Innovation
by Daniel Nenni on 12-18-2023 at 10:00 am

New CEVA Logo
Company sharpens its strategy of delivering silicon and software IP that makes it possible for low power Edge AI devices to connect, sense and infer data, reliably and efficiently, across multiple high-growth end markets

Ceva Inc. is an interesting company. Founded in November 2002, through the combination of the DSP IP licensing… Read More


Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing

Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing
by Kalar Rajendiran on 11-21-2023 at 10:00 am

CEVA Comprehensive Edge AI Portfolio

The surge in Edge AI applications has propelled the need for architectures that balance performance, power efficiency, and flexibility. Architectural choices play a pivotal role in determining the success of AI processing at the edge, with trade-offs often necessary to meet the unique demands of diverse workloads. There are… Read More


Quadric’s Chimera GPNPU IP Blends NPU and DSP to Create a New Category of Hybrid SoC Processor

Quadric’s Chimera GPNPU IP Blends NPU and DSP to Create a New Category of Hybrid SoC Processor
by Kalar Rajendiran on 11-01-2022 at 10:00 am

Memory Optimization Equals Power Minimization

Performance, Power and Area (PPA) are the commonly touted metrics in the semiconductor industry placing PPA among the most widely used acronyms relating to chip development. And rightly so as these three metrics greatly impact all electronic products that are developed. The degree of impact depends of course on the specific … Read More


VeriSilicon’s AI-ISP Breaks the Limits of Traditional Computer Vision Technologies

VeriSilicon’s AI-ISP Breaks the Limits of Traditional Computer Vision Technologies
by Kalar Rajendiran on 10-13-2022 at 10:00 am

VeriSilicons NPU Offerings

The tremendous growth in edge devices has focused the spotlight on Edge-AI processing for low latency, low power and low-DDR bandwidth compute needs. Many of these Edge-AI applications depend on effective and efficient processing of image and video streams which in turn relies on computer vision technology. In early September,… Read More


CEO Interview: Jay Dawani of Lemurian Labs

CEO Interview: Jay Dawani of Lemurian Labs
by Daniel Nenni on 08-19-2022 at 6:00 am

JayDawani

Jay Dawani is the co-founder & CEO at Lemurian Labs, a startup developing a novel processor to enable autonomous robots to fully leverage the capabilities of modern day AI within their current energy, space, and latency constraints.

Prior to founding Lemurian, Jay had founded two other companies in the AI space. He is also … Read More


A Flexible and Efficient Edge-AI Solution Using InferX X1 and InferX SDK

A Flexible and Efficient Edge-AI Solution Using InferX X1 and InferX SDK
by Kalar Rajendiran on 11-18-2021 at 6:00 am

15 Transformer vs Traditional CNN 2

The Linley Group held its Fall Processor Conference 2021 last week. There were several informative talks from various companies updating the audience on the latest research and development work happening in the industry. The presentations were categorized as per their focus, under eight different sessions. The sessions topics… Read More


A Packet-Based Approach for Optimal Neural Network Acceleration

A Packet-Based Approach for Optimal Neural Network Acceleration
by Kalar Rajendiran on 11-08-2021 at 10:00 am

6 Optimal Work Unit Designed for DLA

The Linley Group held its Fall Processor Conference 2021 last week. There were a number of very informative talks from various companies updating the audience on the latest research and development work happening in the industry. The presentations were categorized as per their focus, under eight different sessions. The sessions… Read More


Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads

Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads
by Kalar Rajendiran on 05-17-2021 at 10:00 am

SuperCharge ML Performance

During the week of April 19th, Linley Group held its Spring Processor Conference 2021. The Linley Group has a reputation for convening excellent conferences. And this year’s spring conference was no exception. There were a number of very informative talks from various companies updating the audience on the latest research and… Read More