Flexible ASIC Strategy!

Flexible ASIC Strategy!
by Daniel Nenni on 04-21-2012 at 9:00 pm

During my last Taiwan trip I also spent time with Global Unichip. Clearly, in order for the semiconductor industry to thrive we must enable design starts. With the rising costs and complexity of semiconductor design and manufacturing this is a much greater challenge which is why I’m so interested in GUC, for the greater good of the… Read More


Introduction to FinFET technology Part I

Introduction to FinFET technology Part I
by Tom Dillinger on 04-18-2012 at 6:00 pm

This is the first of a multi-part series, to introduce FinFET technology to SemiWiki readers. These articles will highlight the technology’s key characteristics, and describe some of the advantages, disadvantages, and challenges associated with this transition. Topics in this series will include FinFET fabrication,Read More


Soft Error Rate (SER) Prediction Software for IC Design

Soft Error Rate (SER) Prediction Software for IC Design
by Daniel Payne on 04-16-2012 at 10:00 am

My first IC design in 1978 was a 16Kb DRAM chip at Intel and our researchers discovered the strange failure of Soft Errors caused by Alpha particles in the packaging and neutron particles which are more prominent at higher altitudes like in Denver, Colorado. Before today if you wanted to know the Soft Error Rate (SER) you had to fabricate… Read More


Chip in the Clouds – "Gathering"

Chip in the Clouds – "Gathering"
by Kalar Rajendiran on 04-13-2012 at 1:29 pm


Cloud computing is the talk of the tech world nowadays. I even hear commentaries about how entrepreneurs are turned down by venture capitalists for not including a cloud component into their business plan no matter what the core business may be. The commentary goes “It’s cloudy without any clouds.” Add some clouds to your strategy… Read More


EDA Industry Talks about Smart Phones and Tablets, Yet Their Own Web Sites are Not Mobile-friendly

EDA Industry Talks about Smart Phones and Tablets, Yet Their Own Web Sites are Not Mobile-friendly
by Daniel Payne on 04-09-2012 at 12:55 pm

images?q=tbn:ANd9GcTDJsfnqTKzzfAVaUi2zjF5gvc 6daoganHmJjsILyaBWMw5qtn

As a blogger I write weekly about the EDA industry and certainly our industry enables products like Smart Phones and Tablets to even exist, however if we really believed in these mobile devices then what should our web sites look like on a mobile device?

It’s a simple question, yet I first must define mobile-friendly before… Read More


Synopsys Users Group 2012 Keynote: Dr Chenming Hu and Transistors in the Third Dimension!

Synopsys Users Group 2012 Keynote: Dr Chenming Hu and Transistors in the Third Dimension!
by Daniel Nenni on 04-08-2012 at 7:00 pm

It was an honor to see DR. Chenming Huspeak and to learn more about FinFets, a technology he has championed since 1999. Chenming is considered an expert on the subject and is currently a TSMC Distinguished Professor of Microelectronics at University of California, Berkeley. Prior to that he was the Chief Technology Officer of TSMC.… Read More


IP-SoC day in Santa Clara: prepare the future, what’s coming next after IP based design?

IP-SoC day in Santa Clara: prepare the future, what’s coming next after IP based design?
by Eric Esteve on 04-05-2012 at 10:16 am

D&R IP-SoC Days Santa Clara will be held on April 10, 2012 in Santa Clara, CA and if you plan to attend, just register here. IP market is a small world, and EDA a small market if you look at the generated revenue… but both are essential building blocks for the semiconductor industry. It was not clear back in 1995 that IP will become … Read More


DAC 2012 Technical Program Highlights

DAC 2012 Technical Program Highlights
by Daniel Nenni on 04-01-2012 at 11:00 pm

The technical program for DAC 2012 has an exceptional quality of technical papers, panels, special sessions, WACI (Wild and Crazy Ideas), WIP (Work In Progress), full day tutorials and user-track. The program is tailored for researchers and developers focused on electronic design automation (EDA) and embedded systems and … Read More


Synopsys: now in 3D

Synopsys: now in 3D
by Paul McLellan on 03-26-2012 at 8:00 am

And no red and green glasses required.

I remember the first time I heard about a Through Silicon Via (TSV), punching a hole through the entire wafer to make an electrical connection at the back, like we do all the time in printed circuit boards with through plated holes. I thought someone was trying one on and trying to make me look a fool.… Read More


EDPS Monterey

EDPS Monterey
by Paul McLellan on 03-17-2012 at 8:00 am

Every year in Monterey is a relatively small conference that looks at the design process, EDPS, the electronic design process symposium. I gave a keynote there a couple of years ago, but you don’t have to listen to me this time. The keynotes are from:

  • 1st day: Misha Buric, CTO of Altera, talking about SoC FPGAs and other things
Read More