While you’re reading the SoC manual

While you’re reading the SoC manual
by Don Dingee on 08-09-2012 at 8:30 pm

There was a day, not too long ago, when a software developer could be intimate with a processor through understanding its register set. Before coding, developers would reach for a manual, digging through pages and pages of 1s and 0s with defined functions to find how to gain control over the processor and its capability. One bit set… Read More


A Brief History of EDA

A Brief History of EDA
by Daniel Nenni on 08-05-2012 at 6:00 pm

Electronic Design Automation, or more affectionately known as EDA, is a relatively young $5B industry with a very colorful upbringing, one that I have experienced firsthand, I’m very grateful for, and is an honor to write about. Today EDA employs an estimated 27,000 people! There is a nice EDA Wikipedia page which can be found hereRead More


Synopsys Challenges with SpringSoft Acquisition

Synopsys Challenges with SpringSoft Acquisition
by Daniel Payne on 08-03-2012 at 12:41 pm

Another week in EDA and yet another acquisition by Synopsys as they buy SpringSoft this time for $406 million in cash. Paul McLellan wrote a good blog on this merger too.

Last week I blogged about the product overlap and integration challenges that Synopsys faces with the acquisition of Ciranova
.

Let’s take a look at the IC … Read More


Synopsys Aquires Springsoft

Synopsys Aquires Springsoft
by Paul McLellan on 08-03-2012 at 12:07 pm

Today it was announced that Synopsys is acquiring SpringSoft for $406 million dollars ($12.2B Taiwanese). Coincidentally, I was in SpringSoft’s US office yesterday to talk about how Laker is being used for 20nm design. More of that later. But there was certainly nothing to indicate that anyone there was expecting this.… Read More


Cadence Digital Flow

Cadence Digital Flow
by Paul McLellan on 08-01-2012 at 8:01 pm

Cadence has a series of webinars about their digital flow, focused on 28nm design. It is easy for all of us in the EDA ecosystem to assume that everyone is already doing 20/22nm design, if not 14nm already. But in fact most designs are still being done at 45nm and 65nm; 28nm is still a big challenging step.

One of the tools in the Cadence… Read More


Verdi Integrated with Synopsys Protocol Analyzer

Verdi Integrated with Synopsys Protocol Analyzer
by Paul McLellan on 08-01-2012 at 4:28 pm

Josefina Hobbs, a solutions architect at Synopsys, shows the integration of Synopsys Protocol Analyzer with SpringSoft’s Verdi using the Verdi Interoperability Apps (VIA) which gives open access to the Verdi KDB and FSDB databases. She also demonstrates protocol debug made easy using the Protocol Analyzer. This gives… Read More


SemiWiki.com Analytics Exposed 2012

SemiWiki.com Analytics Exposed 2012
by Daniel Nenni on 07-29-2012 at 7:30 pm


About 4 years ago some of my semiconductor cohorts urged me to blog. “Hey Dan, you’re a funny guy, write about EDA and IP, make us laugh!” Of course what I think is funny most people think is snarky, which is a nice word for being a smart ass. The traditional semiconductor press was crumbling, the non traditional EDA websites were outdated,… Read More


Addressing the Nanometer Digital Design Challenges! (Webinars)

Addressing the Nanometer Digital Design Challenges! (Webinars)
by Daniel Nenni on 07-27-2012 at 7:30 pm

Optimizing logical, physical, electrical, and manufacturing effects, Cadence digital implementation technology eliminates iteration without sacrificing design quality by addressing timing sensitivity, yield variation, and leakage power from the start. … Read More


Synopsys Protocol Analyzer Video

Synopsys Protocol Analyzer Video
by Paul McLellan on 07-27-2012 at 3:07 pm

Josefina Hobbs, a solutions architect at Synopsys, demonstrates protocol debug made easy using the Synopsys Protocol Analyzer. This gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. The video also shows the integration of Synopsys Protocol Analyzer with SpringSoft’s… Read More


Parasitic-Aware Design Flow with Virtuoso

Parasitic-Aware Design Flow with Virtuoso
by Daniel Payne on 07-27-2012 at 12:01 pm

I learn a lot these days through webinars and videos because IC design tools like schematic capture and custom layout are visually oriented. Today I watched a video presentation from Steve Lewis and Stacy Whiteman of Cadence that showed how Virtuoso 6.1.5 is used in a custom IC design flow:… Read More