SEMICON Taiwan 3D

SEMICON Taiwan 3D
by Paul McLellan on 08-08-2013 at 3:10 pm

SEMICON Taiwan is September 3rd to 6th in TWTC Nangang Exhibition Hall. Just as with Semicon West in July in San Francisco, there is lots going on. But one special focus is 3D IC. There is a 3DIC and substrate pavilion on the exhibit floor and an Advanced Packaging Symposium. Design tools, manufacturing, packaging and testing solutions… Read More


When Is a Good Time to Start Using High-Level Synthesis?

When Is a Good Time to Start Using High-Level Synthesis?
by Paul McLellan on 08-07-2013 at 12:42 pm

Of course if you are in the business of selling high-level synthesis (HLS) tools then the obvious answer is immediately. Start at 9am tomorrow morning. But a more realistic answer is when you are having to do something completely new. If you are working on a legacy design, perhaps with pre-existing IP, then moving the design up to … Read More


What Do Brazil and Sweden Have in Common?

What Do Brazil and Sweden Have in Common?
by Paul McLellan on 08-06-2013 at 4:55 pm

Well, Sweden is not noted for its carnivals, Brazil is not noted for it’s tall blonde blue-eyed women, Sweden’s climate is not great for growing sugar cane and Brazil’s isn’t great for reindeer. Both countries speak languages with odd-sounding vowels but they are not the same language. But, ding, Jasper… Read More


How many consortia does POWER need to succeed?

How many consortia does POWER need to succeed?
by Don Dingee on 08-06-2013 at 1:02 pm

Sometimes press releases just make me scratch my head. Today’s example comes from IBM: after tying PowerPC and Power.org in knots for almost 20 years with rules and restrictive licensing, IBM breaks ranks and sets up ANOTHER consortium with different players.… Read More


ClioSoft at GenApSys

ClioSoft at GenApSys
by Paul McLellan on 08-06-2013 at 12:51 pm

GenApSys is a biotech company developing proprietary DNA sequencing technology. As part of that they develop their own custom sequencing chips. These have an analog component and like many people they use the Cadence Virtuoso analog design environment for this.

I talked to Hamid Rategh who is GenApSys’s VP engineering.… Read More


The Funnest Bug

The Funnest Bug
by Paul McLellan on 08-06-2013 at 12:13 am

We all have a funnest bug we’ve been involved with. I don’t think ‘funnest’ is actually a word but when my kids used to use the word ‘funner’ I didn’t have a good argument as to why it wasn’t a word, it just seemed a word I’d never heard. In fact I have no idea what the rules are… Read More


New Media and the Semiconductor Ecosystem!

New Media and the Semiconductor Ecosystem!
by Daniel Nenni on 08-04-2013 at 7:30 pm

Gary Smith did a nice write-up on the current state of electronics media. It’s posted on his Gary Smith EDAwebsite. Traditional media certainly is in transition and there is more change to come, definitely. Gary lists me as one of the heroes carrying the flag which is very nice of him to say. In reality though, he missed Paul … Read More


Power and Reliability Sign-off – A must, but how?

Power and Reliability Sign-off – A must, but how?
by Pawan Fangaria on 07-29-2013 at 11:00 am

At the onset of SoCs with multiple functionalities being packed together at the helm of technologies to improve upon performance and area; power, which was earlier neglected, has become critical and needs special attention in designing SoCs. And there comes reliability considerations as well due to multiple electrical and … Read More


From Layout Sign-off to RTL Sign-off

From Layout Sign-off to RTL Sign-off
by Pawan Fangaria on 07-25-2013 at 5:00 am

This week, I had a nice opportunity meeting Charu Puri, Corporate Marketing and Sushil Gupta, V.P. & Managing Director at Atrenta, Noida. Well, I know Sushil since 1990s; in fact, he was my manager at one point of time during my job earlier than Cadence. He leads this large R&D development centre, consisting about 200 people… Read More


Metastability Starts With Standard Cells

Metastability Starts With Standard Cells
by Daniel Nenni on 07-24-2013 at 8:05 pm

Metastability is a critical SoC failure mode that occurs at the interface between clocked and clockless systems. It’s a risk that must be carefully managed as the industry moves to increasingly dense designs at 28nm and below. Blendics is an emerging technology company that I have been working with recently, their MetaACERead More