One new feature at DAC this year is that several of the keynotes are preceded by a ten minute vision of the future from one of the EDA CEOs. Today it was Wally Rhines’s turn. Wally is CEO of Mentor Graphics. He titled his talk Changing the World Through EDA. Since EDA as we know it started in the late 1970s, the number of transistors… Read More
As is now traditional, Gary Smith kicked off DAC proper (there were workshops earlier and some co-located conferences started days before). He started by dismissing the idea that it costs $170M to do an SoC design.
In fact he looked at 3 different cases. Firstly, the completely unconstrained design. Well, no design is completely… Read More
This year’s Kaufman award winner is Chenming Hu. In contrast to previous years, this was presented on the Sunday evening of DAC instead of at a separate event in San Jose. Chenming’s career was reviewed by Klaus Schuegraf, Group Vice President of EUV Product Development at Cymer, Inc (now part of ASML) and also one of… Read More
One of the other increasingly successful channels (besides Semiwiki of course) for EDA, IP and semiconductor companies to reach potential customers is John Cooley’s DeepChip. Every year he puts a lot of effort into trying to find out who is exhibiting what at DAC and which stuff seems like it is new and maybe important, and… Read More
Just in time for DAC, Carbon have announced that they have expanded their partnership with ARM to create and deliver models for the ARM Cortex-A57 processor and related IP. One piece of related IP is the Cortex-A53 which can be configured in big.LITTLE multi-core setups to achieve the sweet spot of higher performance and lower power.… Read More
Last year at DACI discovered a physical IP company called DXCorrthat competed against giant ARM. This year the company has selected a different direction, so I got caught up with Nirmalya Ghosh, the CEO to hear about the changes.
Nirmalya Ghosh, DXCorr
… Read More
Today Atrenta and Mentor announced that they were collaborating to enable accurate, signoff quality power estimation at the RTL for entire SoCs. The idea is to facilitate RTL power estimation for designs of over 50M gates running actual software loads over hundreds of millions of cycles, resulting in simulation datasets in the… Read More
The big 50th Anniversary party for DAC is on Monday night at the home of Austin City Limits. However, you can do good while enjoying yourself and also get into “The Hot Zone”, an exclusive area within the party in the penthouse Jack and Jim Gallery. The Gallery features 30 original photographs from the godfather of music… Read More
We have talked for years about RTL signoff, the idea that a design could be finalized at the RTL level and then most of the signoff would take place there. Then the design would be passed to a physical implementation team who would not expect to run into any problems (such as routing congestion, missing the power budget or similar problems).… Read More
Debugging an IC design at the transistor, Gate and RTL levels is often necessary to meet timing requirements and understand analog or digital behavior, yet the process itself can be a tedious one, filled with manual steps, therefore making it an error-prone process. EDA tools have been created to help us graphically debug transistor,… Read More
