TSMC Delivers First FinFET ARM Based SoC!

TSMC Delivers First FinFET ARM Based SoC!
by Daniel Nenni on 09-25-2014 at 9:00 am

Right on cue, TSMC announces 16nm FinFET production silicon. I believe this is the original version of FinFET versus 16FF+ which is due out in 1H 2015. I will confirm this next week at the TSMC OIP event in San Jose, absolutely. Either way this is excellent news for the fabless semiconductor ecosystem and I look forward to the first … Read More


Temperature – The Fourth Aspect to Look at in SoC Design

Temperature – The Fourth Aspect to Look at in SoC Design
by Pawan Fangaria on 07-25-2014 at 2:00 pm

In my career in semiconductor industry, I can recall, in the beginning there was emphasis on design completion with automation as fast as possible. The primary considerations were area and speed of completion of a semiconductor design. Today, with unprecedented increase in multiple functions on the same chip and density of the… Read More


Smart Strategies for Efficient Testing of 3D-ICs

Smart Strategies for Efficient Testing of 3D-ICs
by Pawan Fangaria on 02-12-2014 at 6:30 am

3D-IC has a stack of dies connected and packaged together, and therefore needs new testing strategies other than testing a single die. It’s given that a single defective die can render the whole of 3D-IC unusable, so each die in the stack must be completely and perfectly tested before its entry into that stack. Looking at it from a … Read More


TSMC: 3D, 450mm, CoWoS and More

TSMC: 3D, 450mm, CoWoS and More
by Paul McLellan on 12-18-2013 at 4:29 pm

The first keynote at the Burlingame 3D conference was by Doug Yu of TSMC. Not surprisingly he was talking about 3D. In particular, TSMC has WLSI technology that they call CoWoS, which stands for chip-on-wafer-on-substrate which pretty much describes how it is built. This is the technology that Xilinx uses for its recently announced… Read More


Xilinx and TSMC: Volume Production of 3D Parts

Xilinx and TSMC: Volume Production of 3D Parts
by Paul McLellan on 11-07-2013 at 1:23 pm

A couple of weeks ago, Xilinx and TSMC announced the production release of the Virtex-7 HT family, the industry’s first heterogeneous 3D ICs in production. With this milestone, all Xilinx 28nm 3D IC families are now in volume production. These 28nm devices were developed on TSMC’s Chip-on-Wafer-on-Substrate (CoWoS)… Read More


Double Patterning for IC Design, Extraction and Signoff

Double Patterning for IC Design, Extraction and Signoff
by Daniel Payne on 01-21-2013 at 3:27 pm

TSMC and Synopsys hosted a webinar in December on this topic of double patterning and how it impacts the IC extraction flow. The 20nm process node has IC layout geometries so closely spaced that the traditional optical-based lithography cannot be used, instead lower layers like Poly and Metal 1 require a new approach of using two… Read More


Chip On Wafer On Substrate (CoWoS)

Chip On Wafer On Substrate (CoWoS)
by Daniel Payne on 11-03-2012 at 5:19 pm

tsmc cowos test vehicle1

Our EDA industry loves three letter acronyms so credit the same industry for creating a five letter acronym CoWoS. Two weeks ago TSMC announced tape-out of their first CoWoS test chip integrating with JEDEC Wide I/O mobile DRAM interface, making me interested enough to read more about it. At the recent TSMC Open Innovation Platform… Read More


Hybrids on BeO then, 3D-IC in silicon now

Hybrids on BeO then, 3D-IC in silicon now
by Don Dingee on 10-21-2012 at 8:10 pm

Once upon a time (since every good story begins that way), I worked on 10kg, 70 mm diameter things that leapt out of tubes and chased after airplanes and helicopters. The electronics for these things were fairly marvelous, in the days when surface mount technology was in its infancy and having reliability problems in some situations.… Read More


TSMC dilemma: Cadence, Mentor or Synopsys?

TSMC dilemma: Cadence, Mentor or Synopsys?
by Eric Esteve on 10-18-2012 at 4:49 am

Looking at the Press Release (PR) flow, it was interesting to see how TSMC has solved a communication dilemma. At first, let’s precise that #1 Silicon foundry has to work with each of the big three EDA companies. As a foundry, you don’t want to lose any customer, and then you support every major design flow. Choosing another strategy… Read More


Cadence/TSMC 3D

Cadence/TSMC 3D
by Paul McLellan on 06-11-2012 at 5:16 pm

Mark Twain remarked that everyone talks about the weather but nobody does anything about it. 3D ICs seems to be a bit like that. Over the last couple of years there have been lots of people talking about 3D but very little that has actually been manufactured. In addition to the weather, everyone talks about Xilinx’s 3D Virtex… Read More