RISC-V has emerged as a cornerstone of modern computing, offering an open-source alternative to proprietary designs like ARM and x86. Free from licensing fees and highly extensible, RISC-V powers everything from IoT devices to AI accelerators, with over 13 billion cores shipped globally. Annual RISC-V Summits, organized… Read More
Breker Verification Systems will demonstrate its new RISC-V CoreAssurance™ and SoCReady™ SystemVIP™ along with its Trek Test Suite Synthesis portfolio during the 61st Design Automation Conference (DAC) in Booth #2447. DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West… Read More
Maheen Hamid, a member of the ESD Alliance (a SEMI Technology Community) Governing Council and a member of SEMI’s North America Advisory Board, is an astute business executive. Together with her husband Adnan Hamid, they founded Breker Verification Systems, a company developing test synthesis solutions. She serves today … Read More
The much anticipated (virtual) DVCON 2022 is happening this week and functional verification plus UVM is a very hot topic. Functional Verification Engineers using UVM can enjoy a large number of benefits by synthesizing test content for their testbenches. Abstract, easily composable models, coverage-driven content, deep… Read More
Dan is joined by Dave Kelf, who was recently appointed CEO of Breker Verification Systems. Dave discusses Breker’s unique approach to verification of complex systems, what its future impact will be and what Breker will be doing at DAC.
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Webinars have been a popular form of communication since even before SemiWiki existed and they are a mainstay in today’s fast-moving semiconductor ecosystem.
In the past, SemiWiki has assisted with more than a hundred webinars. Today SemiWiki can do a complete webinar from start to finish using the GotoWebinar software. SemiWiki… Read More
Portable stimulus has been a hot topic for a couple of years in the EDA and semiconductor industries. Many observers see this approach as the next major advance in verification beyond the Universal Verification Methodology (UVM), and the next step higher in abstraction for specifying verification intent. The basic idea is to … Read More
Last week I attended the first Verification 3.0 Innovation Summit held at Levi’s Stadium in Santa Clara along with about 90 other interested engineers and former engineers (meaning marketing and sales people, like me). There was a great vibe and feel to the event as it exuded an energy level that I have not felt at an EDA event in years.… Read More
It is important when talking about a market to first establish the need and potential growth, then determine how the market is being served. This requires examining product features and services offered. … Read More
In the EDA space, nothing seems to be more fragmented in-term of solutions than in the Design Verification (DV) ecosystem. This was my apparent impression from attending the four panel sessions plus numerous paper presentations given during DVCon 2018 held in San Jose. Both key management and technical leads from DV users community… Read More
