Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)
by Daniel Payne on 06-14-2011 at 12:26 pm

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.

Notes
Why 32/28nm
Lower power, high integration requirements, mobile applications

What is Ready?
IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
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Physical IP Group at ARM

Physical IP Group at ARM
by Daniel Payne on 06-13-2011 at 5:45 pm

After lunch on Monday I met with John Heinlin, Ph.D. – VP Marketing of Physical IP Division

Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).

Q: Do you favor any EDA tools for creating your IP?
A: No, we don’t really endorse a specific… Read More


Magma, ARM, GLOBALFOUNDRIES

Magma, ARM, GLOBALFOUNDRIES
by Daniel Payne on 06-06-2011 at 11:07 am

Introduction
Monday morning at DAC I attended the breakfast presentation from Magma, ARM and GLOBALFOUNDRIES. The 28nm node is ready for business using Magma tools and ARM libraries.

During breakfast I met Karim Arabi, Ph.D. from QualComm. He’s a senior director of engineering in San Diego and wanted to learn more about… Read More


GLOBALFOUNDRIES 28nm Design Ecosystem!

GLOBALFOUNDRIES 28nm Design Ecosystem!
by Daniel Nenni on 06-01-2011 at 11:00 am

GLOBALFOUNDRIES will show off its 28nm design ecosystem at #48DAC next week in San Diego. The company will feature a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership… Read More


Intel’s 22nm Process. Atom, ARM, Apple

Intel’s 22nm Process. Atom, ARM, Apple
by Paul McLellan on 05-05-2011 at 9:52 am

Intel had a big press event yesterday at which they announced details of their 22nm process. In a change from their current processes, it goes with a vertical gate. In fact 3 gates which gives them much better control of leakage through transistors that are switched off, along with more transmission through the on transistors. They… Read More


Ivo Bolsens of Xilinx and Crossover Designs

Ivo Bolsens of Xilinx and Crossover Designs
by Paul McLellan on 04-27-2011 at 4:14 pm

I was at Mentor’s u2u (user group) meeting and one of the keynotes was by Ivo Bolsens of Xilinx. The other was by Wally Rhines and is summarized here.

Ivo started off talking analogizing SoCs as the sports-cars of the industry (fast but expensive), and FPGAs as the station wagons (not cool). In fact he even said that when Xilinx… Read More


Intel Buys an ARMy. Maybe

Intel Buys an ARMy. Maybe
by Paul McLellan on 04-19-2011 at 5:18 pm

Is Intel in trouble? Since it is the #1 semiconductor company and, shipping 22nm in Q4 this year with 14nm in 2013, it is two process generations ahead of everyone else it is hard to see why it would be. Intel, of course, continues to dominate the market for chips for notebooks, desktops and servers. But therein lies the problem. Pads… Read More


ARM and GlobalFoundries

ARM and GlobalFoundries
by Eric Esteve on 03-25-2011 at 9:49 am


Although there has been always a strong relationship between ARM and GlobalFoundries, it is interesting to notice that Intel has helped to boost it and make it even stronger. Indeed when AMD renegotiated its x86 licensing deal with Intel in 2009, one of the most significant long-term changes was a marked reduction in how much of
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ARM vs Intel…Performance? Power? OS support? Or ubiquity?

ARM vs Intel…Performance? Power? OS support? Or ubiquity?
by Eric Esteve on 03-22-2011 at 2:18 pm

This blog was posted 10 months ago, and the comments have made it much more interesting! Don’t miss the various comments at the back. Also feel free to let us know if you think the status, in this ARM vs Intel “war” has changed a lot since March 2011. Do you really think Intel has catch up with ARM in the mobile industry?Read More


DRC+, DFM, CMP, Variablility

DRC+, DFM, CMP, Variablility
by Daniel Payne on 02-10-2011 at 12:42 pm

When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.

(United States Patent 6661699. Inventor:… Read More