You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today!
I talked recently about the Intel acquisition of Altera which seems to be all about using FPGA technology to build custom accelerators for the datacenter. Some algorithms, especially in search, vision, video and so on map much better onto a hardware fabric than being implemented in code on a regular microprocessor.
So if the heart… Read More
As we are aware about SmartDV Technologies, a fast emerging company in IP space with offices in Bangalore and San Diego, its booth in 52ndDACwas located at a prominent position in front of DAC Pavilion on the exhibits floor. So, most of the crowd coming to attend sessions in DAC Pavilion had a glimpse of SmartDV. I met Deepak Kumar Tala… Read More
eSilicon ♥ ARM!by Daniel Nenni on 07-01-2015 at 5:00 amCategories: EDA, eSilicon
The things I enjoy the most at conferences are presentations by customers, the companies that solve the problems we face every day with modern semiconductor design. We all have access to the same tools and IP and use the same foundries so it’s the actual design and implementation that separates the wheat from the chaff, absolutely.… Read More
While I was at the imec Technology Forum someone asked me “Why did Intel pay $15B for Altera?” (the actual reported number is $16.7B).
The received wisdom is that Intel decided that it needs FPGA technology to remain competitive in the datacenter. There is a belief among some people that without FPGA acceleration available for vision… Read More
As I said yesterday, I’m at the imec Technology Forum (ITF) in Brussels. So what have I learned from all the people that I’ve interacted with.
There were two press releases announced at a press conference yesterday. The first was that imec was expanding its relationship with Toshiba and Sandisk. This covers bringing… Read More
Today, an SoC is seen in the context of an optimized assembly of IPs; it’s no more a single monolithic chip design. It’s very common to see an ARM processor IP along with an interconnect IP, a memory IP, and couple of buses and interfaces IP in an SoC. Although the SoC seems to be an integrated collection of IPs, it can be very complex and… Read More
It gives me a very nice, somewhat nostalgic, feeling after attending the 52[SUP]nd[/SUP] DAC. There was a period during my final academic year in 1990 and my first job when I used to search through good technical papers in DAC proceedings and try implementing those concepts in my project work. In general, representation from ‘R&D… Read More
When the term wearables is mentioned most people’s first thoughts go to devices like the Apple Watch, Fitbit Flex, or Nike Fuel Band. Wearables such as these solve first-world problems like how much exercise am I getting, or what is my heart rate. The developed world drives the development of new technology in most cases, and wearables… Read More
Tuesday night I got to meet an old colleague. OK, this is DAC, that is hardly a story. I was at the Synopsys media dinner and John Koeter handed out free wristbands to the Stars of IP party taking place later that evening. Remember, Synopsys is #3 in IP overall and #1 in interface IP. Talking of which, earlier in the day I was at the Synopsys… Read More
The attraction to an IP-based design methodology is that you can assemble an SoC from ready-made IP blocks, saving you valuable engineering development and verification time, while reducing risks from having to develop something from scratch and hoping that they meet industry standard specs. ARM is well known for supplying … Read More