WEBINAR: PG Pcells- A Correct by Construction Power and Ground Distribution Strategy

Power and Ground design can be problematic to implement, especially in lower metals. Layout can end up being very crowded and result in a compromise between routing and power structure. Power grid can be time and labor intensive for implementation largely due to the fact that often signal routing is done first and Power Grid is added on, usually manually, at a later layout stage. This can lead to difficulties meeting EM/IR requirements and the need to go through multiple flow iterations.

Implementing manually the Power Grid structure doesn’t produce a robust as an instance or mosaic based layout. It would be possible more prone to LVS discrepancies and DRC violations as it is easy to move even accidentally a piece of metal or a VIA. Integrating different gate-lengths in the same circuit can be difficult too. Ideally a uniform and consistent power mesh distributed on top of all the different devices, would provide the best supply option. Coupling on matching signals and metal density are daily layout problematics, so failing on any or multiple of the above aspects would possibly lead to rework and a waste of time and money.

Proper Power Strategy for Layouts comes with several requisites that pose great difficulty and are hard to balance without compromising on one or more aspects. Power strategy adds difficulty to an already complex process of floor-planning and is a time and labor-intensive implementation. It poses many challenges like hard to meet EM/IR specifications for a design, integration of different gate lengths in the same circuit, managing noise coupling from power/ground to signals while simultaneously maintaining BEOL density at different levels of hierarchy macro, IP, or chip.

These are the reasons that should motivate the Layout Designer addressing Power Grid from the beginning of the project following a well thought and structured solution.

IC Mask Design’s approach to PG Pcells acts as a facilitator to floor-planning by providing an initial Layout structure. It improves Layout efficiency and accuracy by replacing numerous flat metals and vias with few instances or mosaics which in turn reduces dependence upon frequent EM/IR runs and a DRC clean Layout by construction.

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IC Mask Design

With over twenty years’ experience in all areas of Analog and RF layout, IC Mask Design has helped over two hundred leading edge technology companies in 35 countries across the globe, we are chosen because we can be trusted to deliver a service that exceeds the high expectations of the industry.

When a company experiences a layout skills shortage or an unexpected increase in layout demand IC Mask Design will work with this company to complete projects to the highest standard, on time and on budget. Our work is guaranteed by the company, it is underwritten by experience of leading-edge technology node, foundry, and EDA Tool.

Our team of engineers work from multiple design centres throughout Europe. The working environment is based on a collaborative approach, solving problems, sharing experiences, and fostering a learning environment. ISO9001-2015 certification covers all our customer processes and quality systems.

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