Axiomise pioneered the adoption of formal verification in the semiconductor industry since 2017. Led by visionary CEO, Dr. Ashish Darbari, who has 63 patents in formal verification, and Neil Dunlop an industry veteran with 40 years of experience, Axiomise has helped twenty customers over the last six years by providing them access to bleeding-edge formal verification methodology via its training programs, consulting & services and vendor-neutral formal verification app for end-to-end verification of RISC-V processors.
Tell us a little bit about yourself and your company.
Axiomise provides consulting & services, training and application-specific apps for RISC-V verification such as formalISA for deploying formal methods on complex SoCs. Through our abstraction-driven methodologies and six-dimensional coverage solutions that can be used with any commercial formal verification tool, our experts can tackle the most challenging formal verification problems on a wide variety of designs including RISC-V, Arm, or x86 processors, GPUs or video blocks, networking blocks including Wi-Fi, 5G, and AI/ML.
I am the Business Development Director of the firm and joined the team in February last year.
What was the most exciting high point of 2023 for your company?
One of the main highlights from last year was to work in super complex projects for some of the big names from Silicon Valley. A notable mention was from AMD.
We are proud to have achieved 100% conversions in designs with over billion gates, and to have worked with amazingly talented teams from different parts of the world.
We made a great contribution to our clients’ projects with some of the brightest design and people that we have hired in our team. Moreover, we were able to educate our clients’ teams through bespoke training programs that again are not only unique in industry but also widely regarded as the best. We also contributed directly through our formal methods applied in their designs on the power of formal, particularly when establishing “exhaustive proofs of bug absence” working all through the early design to the sign-off their projects.
On a different note, over the course of the last 18 months our headcount increased from 1 to 15 and our team prides to be hyper diverse and with a 50/50 male/female ratio. We strongly believe that diversity promotes creativity within any team and with the community around it!
What was the biggest challenge your company faced in 2023?
The story around validation & verification is not inspiring with the industry struggling to show improvements in best practice adoption as per Harry Foster’s Wilson Research Report revealing an ever-increasing number of simulation cycles and the astronomical growth of UVM is unable to prevent the ASIC/IC re-spin which is at a staggering 76% while 66% of IC/ASIC projects continue to miss schedules.
Our broad industry experience tells us that the best way of improving these statistics is to shift-left and this can be done by adopting formal methods early in the DV flow by understanding its true potential. While the use of formal apps has certainly increased over the last decade, the application of formal is still very much on the extremities. We find this to be the most formidable challenge.
Even considering that last year we grew our team by more than 50% and our clientele by a larger percentage, the biggest challenge for us was to keep patient with the industry’s pace for adoption of formal and with the time is taking many firms to understand the best practices to deploy formal efficiently and effectively!
How is your company’s work addressing this biggest challenge?
We aim to make the semiconductor community understand that formal verification is a necessity, not just a nice to have; and that UVM and simulation are complementary to formal methods in several areas of many silicon designs. We are doing this of course through hands-on project work on customer designs as well as deploying our formalISA app and training programmes.
What do you think the biggest growth area for 2024 will be, and why?
Everything from networking (5G/6G), RISC-V and accelerator chips for AI/ML would need rigorous verification that only formal methods rooted in great methodology can provide. This is where we see the most opportunities for growth.
How is your company’s work addressing this growth?
We are providing custom formal verification services to the industry by leveraging our expertise rooted in over 60+ years of combined formal verification experience in Axiomise lead by our CEO and CTO. The speed at which we can innovate live on a project to come up with expansive abstraction-driven methodologies has no parallel in the industry. It is something we are getting to hear more and more from our customers. We can crack the hardest problems that are not possible for everyone.
What conferences did you attend in 2023 and how was the traffic?
As our team Axiomise participated and sponsored some of the top-level international conferences and summits.
We had an intense fruitful year whilst attending and networking in the following industry events: ChipEx, the first run RISC-V Summit Europe in Barcelona, DVCon India, RISC-V North America and DVCon Europe.
The traffic and engagement of attendees and organisers was great! We enjoyed meeting and learning from many professionals working in the semiconductor industry from all over the world!
Will you attend conferences in 2024? Same or more?
We will be attending and sponsoring more conferences this year.
We are a confirmed sponsor of DVCon US on 4 – 6 March 2024 and look forward to connecting the semiconductor industry in California next month.
Also Read:
RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®
A Five-Year Formal Celebration at Axiomise
Axiomise at #59DAC, Formal Update
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