Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026

At DVCon U.S. 2026, Accellera Systems Initiative reinforces its central role in shaping the future of electronic design and verification through a focused program of workshops, tutorials, and community engagement. As system complexity continues to rise across AI, automotive, HPC, and communications markets, the need for robust, interoperable standards has become more urgent. Accellera’s presence at DVCon highlights how standards development is evolving to address verification scalability, system-level modeling, and IP reuse in increasingly heterogeneous designs.

We have been working with Accellera since the early days of SemiWiki when our membership was in the thousands. Now our members are in the hundreds of thousands and it really has been a pleasure working with them.

A central theme of Accellera’s program is raising the level of abstraction in design and verification. The workshop on Portable Stimulus Standard (PSS) exemplifies this shift. As SoC verification expands beyond simulation into emulation, FPGA prototyping, and post-silicon validation, traditional testbench-centric approaches struggle to scale. PSS addresses this by allowing engineers to model verification intent at the scenario level, enabling automated generation of tests that can be reused across platforms. By focusing on practical adoption patterns, Accellera positions PSS not as a theoretical construct, but as a pragmatic solution for revitalizing legacy flows and improving coverage in real-world environments

Accellera-Sponsored Events:

Monday, March 2:
Portable Stimulus Modeling Patterns (Practical Tips for Adopting PSS)
9:00-10:30am, Grand Ballroom D

SystemC – What’s New? What’s Next?
11:00am-12:30pm, Grand Ballroom D

Thursday, March 5:
Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model
9:00am-12:30pm, Grand Ballroom D:

IP-XACT Demystified: An In-Depth Training on the IEEE 1685-2022 IP-XACT Standard
1:30-3:00pm, Grand Ballroom D

Another major pillar of Accellera’s DVCon engagement is the continued evolution of SystemC, long regarded as foundational for system-level modeling and virtual platforms. While SystemC has matured significantly, new architectural demands such as chiplet-based designs, software-defined hardware, and large-scale virtual prototyping require renewed attention to interoperability and tooling. The session outlining updates from IEEE 1666-2023, along with progress on the SystemC CCI reflects Accellera’s recognition that standards must evolve in lockstep with industry practice. Lessons drawn from widely adopted open-source frameworks such as QEMU further underscore the importance of learning from production-proven ecosystems rather than relying solely on academic or vendor-specific approaches

Verification correctness and predictability across complex clocking environments is another area where Accellera is driving standardization. The CDC-RDC tutorial introduces efforts by the Clock Domain Crossing Working Group to define a standardized abstract model using IP-XACT and TCL. CDC and RDC issues remain among the most subtle and costly classes of silicon bugs, particularly in large SoCs integrating third-party IP. By working toward a portable, interoperable CDC-RDC model, Accellera aims to reduce tool fragmentation and enable consistent verification flows across vendors, a long-standing industry challenge

The focus on IP-XACT (IEEE 1685-2022) further emphasizes Accellera’s commitment to automation and reuse. As SoC integration teams grapple with exploding register maps, memory hierarchies, and software dependencies, spreadsheet-based approaches have become untenable. The updated IP-XACT standard provides a vendor-neutral framework for capturing IP metadata in a structured, machine-readable form. Accellera’s in-depth training session reflects growing recognition that design, verification, and software teams must operate from a single source of truth to avoid costly integration errors and delays

Beyond the technical content, Accellera’s DVCon activities highlight the importance of community-driven standards development. The Birds-of-a-Feather discussion following the SystemC session and the evening reception are not peripheral events; they are integral to how consensus is built and future directions are shaped. In an era where proprietary solutions can fragment ecosystems, Accellera’s neutral, not-for-profit model remains a critical mechanism for aligning semiconductor companies, IP providers, and EDA vendors around shared technical foundations.

Overall, Accellera’s presence at DVCon U.S. 2026 reflects a broader industry transition. As scaling challenges shift from pure transistor density to system integration, verification productivity, and software alignment, standards are no longer optional—they are strategic infrastructure. Through its workshops, tutorials, and collaborative forums, Accellera continues to position itself as a catalyst for that infrastructure, ensuring the electronics industry can move forward with greater confidence, interoperability, and efficiency.

For a complete program schedule, including exhibition hours, visit the DVCon U.S. 2026 website.

Registration is open. Registration for the keynotes, panel, and exhibits is free.

Also Read:

Podcast EP330: An Overview of DVCon U.S. 2026 with Xiaolin Chen

Boosting SoC Design Productivity with IP-XACT

Podcast EP310: On Overview of the Upcoming DVCon Europe Conference and Exhibition with Dr. Mark Burton