Key Takeaways from the TSMC Technology Symposium Part 2

In Part 1, we reviewed four of the highlights of the recent TSMC Technology Symposium in San Jose. This article details the “Final Four” key takeaways from the TSMC presentations, and includes a few comments about the advanced technology research that TSMC is conducting.

(4) The 7nm node will immediately bifurcate into two technology offerings.

As mentioned in Part 1 of the symposium review, TSMC is expanding their focus to address a wider set of application markets. N7FF will be introduced with mobile and high-performance computing offerings from the start, with a corresponding design enablement “platform” releases for different markets.

Historically, the 55nm, 40nm, 28nm, and 16nm nodes have indeed been defined with multiple variants, and have continued to evolve beyond the initial offering — e.g., the 55ULP, 40ULP, 28HPC+, and 16FFC technology options mentioned in Part 1. (TSMC indicated that the 10nm node will also subsequently receive an ultra-low power ULP release.)

The 20nm node deviated from this trend — TSMC consolidated the original 20nm high-performance and mobile offerings into a single N20SoC technology, which appears to have little additional roadmap investment planned.

Due to the anticipated customer requirements, 7nm will be developed with two branches, both qualified on the same schedule, in 1Q’2017. TSMC highlighted that ~95% of the semi equipment will directly transition from 10nm to 7nm, enabling this aggressive schedule.

Mobile (vs. 10nm):

• +15-20% performance (@ iso-power)
• -30-40% total power (@ iso-performance)
• 1.6X equivalent gate density
• dense BEOL interconnect offering
• SVT/LVT/uLVT devices
• compact standard cell library
• 1.8V I/O support
• SRAM bit cell scaled by 0.76X

High-performance offering:

• larger contacted poly pitch design rule
• wider metals on (low-level) interconnect layers
• larger vias
• taller standard cell library
• 1.5V I/O support (esp. for high-speed SerDes and LPDDR4 designs)
• +10% performance over the mobile offering

TSMC is clearly anticipating high demand for 7nm. Xilinx — traditionally, a high-performance process option TSMC customer — has indicated that they will skip 10nm and jump directly from 16FF to 7nm. And, to be sure, TSMC’s mobile customers are pushing for an aggressive process qualification schedule.

(3) 16FFC will result in a “long life” offering.

When N16FF/N16FF+ were initially introduced, there was a lot of discussion to the effect that,“Well, most cost-sensitive customers will not be able to migrate from 28nm…”. With the introduction of N16FFC, TSMC is working to dispel that assumption, and is committing to expand wafer capacity (~1200K wafers annually).

TSMC highlighted some of the 16FFC process development and schedule updates:

• dual work function gate metals
• an optical shrink for a die size/cost benefit (although 16FFC adopts the same design rules as 16FF+, to expedite the qualification of IP)
• reduced mask count (additional cost benefit)
• Spice corner “tightening”
• ULP-enabled: 0.5V VDD qualification (for mobile and IoT applications)
• ultra low leakage SRAM bitcell (~1pA/cell @ 0.5V)
• HVT device offering (I_off ~10pA/um @ 0.7V)
• volume ramp now, ~70 new tapeouts expected in 2017
• automotive design platform qualified in 2Q’2016, full design enablement in 1H’2017

(2) InFo-PoP packaging technology is quickly emerging as a differentiator for 16nm.

Cross-section of TSMC’s InFO-PoP packaging technology

TSMC has previously presented its Integrated FanOut (InFO) technology, as an attractive option for small form-factor packages with a high I/O count, necessitating a fan-out trace pattern from die bumps using redistribution layer (RDL) metals embedded within the package. Here’s an earlier Semiwiki article summarizing InFO:

https://www.legacy.semiwiki.com/forum/content/5070-wafer-level-chip-scale-packaging-technology-challenges-solutions.html

At this year’s symposium, TSMC indicated they have developed an extension to InFO, enabling a stacked die configuration in a very aggressive footprint. The example they illustrated depicts a DRAM die above an application processor.

The key features of InFO-PoP are:

• thinned package (<0.9mm, ~20% thinner than a conventional PoP)
• 3 RDL layers
• “Through InFO Via” (TIV) pitch of 300um

(Note the new acronym — TIV — which is the InFO-PoP version of a through-silicon via , or TSV, used with 3D silicon interposer technology.)

• +10% improved thermal characteristics
• ~20% “system performance improvement, in next generation mobile applications” (greater memory bandwidth)
• volume production in 2Q’2016
• EDA physical design and verification, electrical analysis tool support qualified
• production fab in place (68K m**2 clean room space, advanced backend fab with automated material handling systems, ~30M units/month capacity)

(1) 10nm is on track, with a very aggressive schedule.

• first N10FF customer TO received
• Fab15 phases 5 and 6 ready for ramp in 2017 (200K wafers/quarter by YE’2017)
• full coloring support available in reference flows

  • A/B color asymmetry on interconnects impacts performance, EM, IR
  • coloring support available in both cell based (e.g., pin-color aware placement) and full-custom flows
  • routing on pre-defined color tracks
• color-aware layout parasitic extraction, EM/IR rules
• next-generation on-chip variation model for static timing analysis

TSMC provided a confident outlook for the 2017 ramp of the 10nm process node.

Cu pillars

From: http://www.tsmc.com/english/dedicatedFoundry/services/wafer_bump.htm

Finally, TSMC did offer one cautionary comment:

Scaling at advanced high-performance nodes necessitates a transition from (lead-free) bump to Cu pillar technology. This change in metallurgy and profile implies a significant difference in the mechanical stresses in the die and package layers. Designers need to ensure that they work closely with TSMC’s services team to understand how to best model and analyze their specific die-package attach configuration.

Advanced Research

The symposium presentations also briefly highlighted TSMC’s advanced semiconductor process R&D. Briefly, the 5nm node could potentially utilize:

• Ge FinFET’s (a key achievement was the development of a low source/drain contact resistance process)
• III-V FinFET’s (e.g., InGaAs nMOS)
• (vertical) III-V nanowires
• Tunnel-FET’s

The progress with EUV bring-up was briefly highlighted, showing image fidelity comparisons between (single-exposure) EUV and 193i multipatterning for contact arrays.

The “net net” of the symposium was that diverse application requirements are driving new approaches to process development and design enablement, from mobile to automotive to high-performance markets. And, significantly, there is no near-term disruption to the development of new process nodes. Indeed, somewhat amazingly, that pace of innovation appears to have increased.

-chipguy

Also read: Key Takeaways from the TSMC Technology Symposium Part 1