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TSMC Will Own the Internet of Things!

TSMC Will Own the Internet of Things!
by Daniel Nenni on 04-27-2014 at 8:00 am
Categories: Foundries, TSMC

In my quest to uncover the future of the semiconductor industry I was quite impressed by the executive presentations at the TSMC Symposium last week. Rick Cassidy opened the 20[SUP]th[/SUP] Annual TSMC Technology Symposium followed by Dr. Mark Liu, Dr. Jack Sun, Dr. Cliff Hou, J.K Wang, Dr. V.J. Wu, and Suk Lee. A variety of topics were covered but I had IoT on my mind so that is what I will talk about here.

Internet of Things (IoT)-The network of physical objects that contains embedded technology to communicate and sense or interact with the objects’ internal state or the external environment.

My interest in IoT started with chapter 8 of Fabless: The Transformation of the Semiconductor Industry where I asked 30 industry luminaries, “What’s next for the semiconductor industry?” In the 300 word responses IoT was a common thread so that is where I have been spending my time. My goal is to navigate through the hype and figure out just how the fabless semiconductor ecosystem (EDA, IP, Foundries) can monetize this emerging market. The semiconductor industry is all about design starts and to me that is what IoT is all about. From what I can tell, the majority of IoT designs today are implemented in mature nodes with 65nm considered bleeding edge technology.

The basic building blocks of an IoT chip include:

  • MCU (ARM is the default here)
  • Sensors (temperature, vibration, gyroscope, humidity, pressure, altitude)
  • Power Management (solar, energy harvesting, short burst battery usage)
  • Embedded Memory (flash, NVM, SRAM)
  • Connectivity (GSM, GPRS, LTE, Zigbee, WiFi, Mesh Network)

Let me know if I’m missing a block.

According to J.K. Wang, Vice President of Operations of 300mm fabs, TSMC ships more than 1.3M 28nm wafers annually and that will increase by 20% this year. The transition to FinFETs is expected to start in 2015 with 900k wafers shipped followed by 1.3M wafers in 2016 which will free up an amazing amount of low cost 28nm capacity. 28nm also has the strongest design ecosystem with more than 100 partners including 39 vendors offering more than 6,000 pieces of IP. This has the makings of a perfect IoT storm:

Low Cost + Large Capacity + Low Power + Design Enabled = Low Barrier to Entry!

The next of many IoT seminars I will attend is sponsored by the World Affairs Council:

The Internet of Things: Global Implications of Merging the Physical and Digital Worlds

More than nine billion devices around the world are currently connected to the Internet, including computers and smartphones. That number is expected to increase dramatically within the next decade, with estimates ranging from quintupling to 50 billion devices to reaching one trillion. Please join us for a discussion of how the Internet of Things will impact the way we live, the way business is done and how resources are consumed. Important to the discussion will be the challenges ahead when merging the physical and digital worlds and the implications for privacy and security around the world.

SPEAKERS:

MODERATOR:

  • Aleecia McDonald, Director of Privacy, Center for Internet and Society, Stanford Law School

WHEN:

Wednesday, May 7, 2014
Reception: 6:00 PM – 7:00 PM
Event: 7:00 PM – 8:00 PM

WHERE:

Cadence Design Systems, Inc.
2655 Seely Avenue, San Jose, CA 95134

I hope to see you there!

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Dr. Morris Chang: A Conversation with the Chairman

Dr. Morris Chang: A Conversation with the Chairman
by Daniel Nenni on 04-24-2014 at 10:00 pm
Categories: Foundries, TSMC

There are moments in one’s career that are memorable beyond others, and last night was one of those moments for me, absolutely:

Stanford University President John L. Hennessy will lead a discussion with Stanford Engineering Hero Morris Chang, an innovator and entrepreneur who revolutionized the semiconductor industry by creating the world’s first dedicated silicon foundry, Taiwan Semiconductor Manufacturing Company or TSMC.

The NVIDIA Auditorium at the Stanford Huang Engineering Center was filled with semiconductor executives, alumni, and students alike. I don’t know how an invitation made its way into my inbox but I am very appreciative. The conversation was engaging to say the least and quite funny at times.

Not surprisingly, NVIDIA CEO Jen-Hsun Huang did the introduction and shared some personal stories about Morris. This was reminiscent of the discussionthey had at the Computer Museum seven years ago which was used as research for the soon to be best-selling book Paul McLellan and I wrote.

Jen-Hsun started out with, “The world is full of successful people but heroes are rare”which I think fits perfectly. He also pointed out that everybody is in possession of two things: Air and products made from TSMC wafers. Jen-Hsun poked good-hearted fun at Morris but the Chairman had the last laugh, definitely.

The first question from John was if Morris had any idea of the impact TSMC would have on the world. Morris replied that at the time, TSMC was providing a solution that was waiting for a problem since the fabless companies at that time were comfortable with using IDMs for wafer manufacturing. He added that the problems came very quickly and Jen-Hsun was one of those problems! Meaning of course that NVIDIA was a fabless company that was looking for a manufacturing partner with integrity and one they could trust not to compete with them. The laughter in the auditorium acknowledged much more than that of course.

John’s second question was about TSMC’s focus on R&D. This rings true to me as I see Intel and Samsung spending billions of dollars on marketing obfuscation while TSMC focuses on R&D. The financial ratio I would like to see is R&D/marketing spending knowing full well TSMC would shine.

The Chairman responded by pointing out he had 30+ years of semiconductor experience (mostly at TI) before starting TSMC . In his words, “You have to climb to the top of a building and look at all of the available roads before you build a new one.” I have climbed a few buildings myself and find this to be very insightful.

The next question was about the Chairman’s education. Morris spent his first year at Harvard before transferring to MIT to study mechanical engineering. Morris admitted to failing his PhD exam twice at MIT before attending Stanford which again brought laughter. During his career at TI Morris was sent to Stanford to get his PhD in electrical engineering. His career goal was to be CEO, which was not possible at TI, so he joined General Instrument but decided he did not want to be CEO so he founded TSMC.

The next question was about how TSMC was launched. The Taiwan government was instrumental in funding TSMC providing 48% of the required capital. The additional investments came from Philips Semiconductor and Taiwanese investors who knew little or nothing at all about semiconductors. Morris approached Intel, TI, and semiconductor companies from Japan but they all said no. The Chairman’s memory is clear on this, naming people who actually said no such as Craig Barrett who later became Intel’s CEO.

The follow-up question was about Japan and why they are no longer major players in the semiconductor industry. According to the Chairman, Japan failed at the future. Instead of embracing the fabless semiconductor business model and unleashing innovation Japan clung to the IDM model and failed. The rest of course is history as most Japanese semiconductor companies are TSMC customers

The question I had for Morris was if he is working on an autobiography. Morris wrote a book in the 1990s which was quite successful in China. Unfortunately it did not translate well into English so it was not published here. I knew the answer to the question was no before I asked but I wanted to plant the seed anyway. It is a book I would read, absolutely. I would even write it.

When I decided to write a book my first thought was to write one about Dr. Morris Chang and how he unleashed innovation that changed the world. Friends at TSMC however suggested that I instead write about Morris’s life work which resulted in “Fabless: The Transformation of the Semiconductor Industry”, which is now available on Amazon as a paperback or in Kindle and iBook format on SemiWiki.

Morris admitted he still smokes a pipe but sited research that says pipe smokers live longer because it helps your mood (laughter). At the end of the event The Chairman was taking pictures with students so I talked to his wife Sophie. Morris always credits her for her support, and one thing I can tell you is that she is as charming as she is beautiful.

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U2U: Things You Might Not Know About TSMC

U2U: Things You Might Not Know About TSMC
by Paul McLellan on 04-10-2014 at 10:50 pm
Categories: EDA, Foundries, TSMC

At Mentor’s U2U this afternoon I attended a presentation on TSMC’s use of Calibre PERC (it is a programmable electrical rule checker) for qualification of IP in TSMC’s IP9000 program. I’ve written about this before here. Basically IP providers at N20SOC, N16FF, and below are required to use PERC to guarantee ESD is OK. This is especially critical with FinFET since the transistors are more fragile and have a lower breakdown voltage. There are also decks for 28nm but it is not required (most IP is already in volume production so problems would have shown up by now). The PERC decks guarantee that the ESD rules are all checked without the error-prone process of having to manually add identifying layers. This is the first time TSMC has specified a particular tool that must be used.

Here is a random miscellany of other facts about TSMC that I picked up:

  • Risk production (samples) for 16FF was at the end of last year
  • Risk production for 10FF will be end of 2015
  • Lots of work has gone on on controlling capacitance on M1 and M2 at 16FF
  • 10nm will have triple patterning and spacer (sidewall image transfer I assume, self-aligned double patterning). More details on 10nm at the TSMC Technology Symposium on 22nd of April
  • TSMC has invested $10B a year for several years to get ready for FinFET
  • FinFET challenges:

    • parasitic capacitance due to the gate wrapping around the fin
    • high parasitic resistance due to local interconnect M0
    • quantized device sizes (only a certain number of fins)
    • breakdown voltage is lower so ESD is more of an issue
  • TSMC has 6600 registered IPs, adding 200 per month

    • 90% hard IP is qualified through IP9000
    • 100% of soft IP is qualified
    • One column on IP listing is (eg) 5/25000 meaning it has been in 5 tapeouts and 25,000 wafers of production
  • Extending from quality audit to slicon validation

    • TSMC has set up validation centere in Taiwan
    • over 20 IPs validated already (started with interface IP)
  • 28nm cycle time started as 4 months, now down to 2 months
  • 16nm cycle time is 5 months will probably end at 3 months
  • Currently 16FF shuttle is about 160 days
  • EUV, TSMC have invested $0.5B in ASML but ROI not good, keeps slipping. They are looking at e-beam and other backup strategies
  • Since EUV is certainly not coming soon, 3D technologies (CoWoS) very important

What is driving N16FF. Mobile of course. Here are the changes from 2012-2014

  • Display 2X
  • Radio 2X
  • Connectivity 3X
  • AP 2X CPU, 5X GPU and 2X memory bandwidth
  • 2 cores go to 8 cores
  • Power same or less
  • Form factor thinner and lighter
  • Camera 8MP to 13MP

If you are a TSMC customer you can register for the technology symposium on 4/22 here.
Details of Mentor’s European U2U in Munich on November 6th is here. You can still submit abstracts until July 1st.


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What is Next for GLOBALFOUNDRIES?

What is Next for GLOBALFOUNDRIES?
by Daniel Nenni on 04-04-2014 at 8:30 am
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

In response to changing industry dynamics, AMD announced in October 2008 a new strategy to focus exclusively on the design phase of semiconductor product development. To achieve that strategy, AMD partnered with Advanced Technology Investment Company (ATIC) of Abu Dhabi to create a new joint venture company designed to become the world’s first truly global contract manufacturer of semiconductors.

On March 4, 2009, GLOBALFOUNDRIES was launched as a new joint venture combining AMD’s leading-edge semiconductor manufacturing capabilities with the long-term financial backing of ATIC. This created a new global semiconductor manufacturing foundry with approximately 3,000 employees with AMD as its first customer.

In January 2010, the company announced the completion of its merger of operations with Chartered Semiconductor, a global semiconductor foundry based in Singapore. At the time, Chartered consisted of about 7,000 employees, mostly based at the company’s 6 fabs in Singapore.

Today, GLOBALFOUNDRIES is wholly owned by ATIC and is the world’s second largest independent semiconductor foundry. However, GF is still one fourth the size of number one foundry TSMC and faces stiff competition from the ever aggressive Samsung Foundry Division and the newly launched Intel Custom Foundry Business Unit. More recently, GF shuffled the executive staff and acquired a new CEO:

Santa Clara, Calif., January 6, 2014 —Building on the successful track record of its first five years in the semiconductor industry and its continued commitment to build out its global network of manufacturing facilities, GLOBALFOUNDRIES announced today, from its new offices in Silicon Valley, Sanjay Jha has been appointed as the company’s new Chief Executive Officer. Jha has served as CEO of Motorola Mobility Inc. and as the COO of Qualcomm Inc.

After spending 14 years at Qualcomm, Sanjay joined Motorola Mobility as CEO in 2008. Sanjay then sold Motorola Mobility to Google in 2011 for $12.5B with an exit package of more the $65M. Google then sold Motorola Mobility to Lenovo in 2014 for $2.91B. Yes Sanjay is a very clever man and he knows the fabless semiconductor ecosystem inside and out.

The $100B question is: What is next for GLOBALFOUNDRIES? The wild card here of course is Sanjay Jha. I do not know Sanjay personally (yet) but I do know people who know him and based on this, I’m wildly optimistic!

It is highly unlikely that Sanjay signed on to continue to stay the course at GLOBALFOUNDRIES. Being a second source or boutique foundry against the likes of TSMC, Samsung, and Intel makes no sense whatsoever. My guess is that Sanjay will go on an acquisition spree with the intention of building a major force in the semiconductor industry, absolutely. If I were Sanjay I would start with MediaTek and I will tell you why in the comments section. Acquiring the IBM semiconductor operations is also on the table I hear.

GF reads SemiWiki so offer your advice to Sanjay. This could be a real game changer, absolutely!

About GLOBALFOUNDRIES
GLOBALFOUNDRIES is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 160 customers. With operations in Singapore, Germany and the United States, GLOBALFOUNDRIES is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GLOBALFOUNDRIES is owned by the Advanced Technology Investment Company (ATIC). For more information, visit http://www.globalfoundries.com.

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FinFET Custom Design

FinFET Custom Design
by Paul McLellan on 04-02-2014 at 8:30 pm
Categories: Foundries, TSMC

At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I’m going to leave verification until another blog.

He wasn’t talking about digital SoC design, which broadly speaking is the same as before. You write RTL, synthesize the design, place and route it and then run verification. Mostly the tools take care of the hard stuff like double patterning. And whoever designed the standard cell libraries took care of all the complicated FinFET stuff. He was talking about custom and analog design where you do actual transistor level layout.


I’m sure you know what a FinFET transistor looks like these days. What you may be less aware of is that they have to be laid out in a sort of matrix. The fin is a fixed size and so the only thing you get to vary about a transistor is how many FinFETs you get to join up in parallel to build a wider transistor. This is often referred to as quantization. In planar devices we used to be able to vary the width and length how we wanted. Actually by the time we got to 20nm this wasn’t really true, the design rules were so restrictive that the transistors were also pretty much laid out in a matrix. To build them, for lithography reasons, the gate material needed to be laid out in parallel lines at the appropriate spacing and then a cut-mask used to split the gate lines up into transistors. So the length of the transistors was pretty much fixed but at least we got to pick the width. With FinFETs we used the same technique but we don’t get to pick the width arbitrarily, just how many fins are controlled by the same signal. So a FinFET design consists of rows of source/drain with rows of gate running orthogonally.


Above is a very simple representation. TSMC doesn’t let anyone see their layout except under NDA so this is actually Cadence’s generic FinFET process used for testing tools early in the whole process. And the planar transistor on the left is nothing like the last planar process at 20nm, it is more like how things looked at 90nm when lithography OPC constraints were a lot more forgiving.

On the right is a FinFET inverter. First thing to note is that the inverter seems to have three gates (red), which is true. Every transistor has to be terminated with dummy gates on either side. You can’t just cut off the diffusion by just ending the polygon like in the planar device on the left. You need to tie it off with a gate. This was actually true at 20nm too, which is one reason I said that the planar transistor was from an old process node. In the middle you can see the red hashed area, that is the cut mask that separates the P and N transistors.

The first thing TSMC did was build a capability into the PDK to build a “transistor” that took as input how many fins were to be used. It created the layout, including dummy gates and well boundaries.

Then they created a schematic migration methodology to automate much of the migration of designs from 20nm by picking appropriate fin-counts close to simply scaling a planar transistor to 16nm. The voltages are different, the PDKs are different, and the quantized nature of FinFETs needed to be taken into account. But when they were done they would have migrated:

  • Circuit symbols and schematics
  • Hierarchical design configuration view
  • Electrical & Physical design constraints
  • Functional behavioral modeling views
  • Testbench schematics and setups

However there is still no layout and the schematic is almost certainly going to need to be changed before the cell is finalized. The first step is thus to circuit simulate the schematic using estimated parasitics to get a starting point for getting to a layout.

The next step is rapid analog prototyping, to iterate between layout, extraction, circuit simulation and tweaking transistor sizes and layout constraints. The actual layout is automatically generated under the constraints. Every time the layout changes the parasitics change so hopefully the process converges reasonably fast.

Then onto verification. But that is a topic for another day.

If you have a Cadence account you should be able to find Bob’s CDNLive presentation here.

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The Infamous Intel FPGA Slide!

The Infamous Intel FPGA Slide!
by Daniel Nenni on 03-11-2014 at 10:30 am
Categories: FinFET, Foundries, FPGA, Intel Foundry, TSMC, Xilinx

As I have mentioned before, I’m part of the Coleman Research Group so you can rent me by the hour to better understand the semiconductor industry. Most of the conversations are by phone but sometimes I do travel to the East Coast, Taiwan, Hong Kong, and China for face-to-face meetings. Generally the calls are the result of an event that needs further explanation or just a quarterly update. Again, as an active semiconductor professional I share my experiences, observations, and opinions so rarely will I agree with the analysts or journalists who rely on Google for information.

In 2003, Kevin Coleman founded Coleman Research to give investors a better way to access industry knowledge. Coleman helps thousands of clients get answers to their most critical questions, without leaving their desks. Rather than spending hours reading research reports, or traveling to meet people at conferences, we connect clients directly with industry experts, to hear immediate, relevant insights.


The Intel analyst meeting last November was full of surprises and resulted in a series of phone consultations. The Intel 14nm superior density claim slides were the most talked about and were absolutely crushed by TSMC, which I wrote about in “TSMC Responds to Intel 14nm Density Claims”. The other slide that caused a flurry of calls is the one above comparing Altera and Xilinx planar to FinFET. After talking to dozens of people (including current and former Altera, Intel, and Xilinx employees) I have concluded that this slide is an absolute fabrication. Get it? Fabrication? Hahahahaaaa….


I did a comparison of the Altera and Xilinx analyst meetings and found the slide above which supports my point. Clearly silicon does not lie so when the competing FPGA FinFET versions are released we will know for sure, but my bet is that Altera/Intel will lose this one. It also goes to my point that the transistor is not everything in modern semiconductor design and Intel’s claims of process superiority are a paper tiger when it comes to finished products.


There are thousands of FPGA and semiconductor process professionals reading SemiWiki so I’m hoping for a meaningful discussion in the comments section. If any of you would like to post a rebuttal blog I’m open to that as well. SemiWiki is an open forum for the greater good of the fabless semiconductor ecosystem, absolutely.

The most recent event that caused a flurry of calls was the JP Morgan Report: Meetings at MWC – Intel Mobile Effort Largely a Side Show, but Some Problems in Foundry a Concern. The press really had a field day with this one:

Some issues popping up with foundry business – we are concerned.Ourchecks indicate there have been some problems with Intel’s foundry effortscentered on design rules and service levels. It appears Intel is being inflexibleon design rules and having trouble adapting to a service (foundry) model. Our J.P. MorganFoundry analyst, Gokul Hariharan wrote today that Altera has re-engaged TSMC.

This resulted in a handful of tabloid worthy articles taking the JP Morgan report completely out of context:

Altera to switch 14nm chip orders back to TSMC, says paper Commercial Times, March 4; Steve Shen, DIGITIMES [Wednesday 5 March 2014]

While I appreciate the consulting business this generated I really do question the motives of Steve Shen. The first “Altera leaving Intel” rumor started HERE and I’m sure this won’t be the last but I’m still not buying it and neither should you.

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Dr. Cliff Hou, TSMC VP of R&D, Keynote

Dr. Cliff Hou, TSMC VP of R&D, Keynote
by Daniel Nenni on 02-16-2014 at 9:00 am
Categories: Foundries, TSMC

This will be my 30[SUP]th[/SUP] Design Automation Conference. I know this because my first DAC was the same year I got married and forgetting how many years you have been married can cost you half your stuff. I have known Cliff Hou for half of that time and he has proven to be one of the most humble and honorable men I have worked with, definitely.

Cliff started at TSMC in the PDK group and produced the first TSMC Reference Flow which really was the starting point for the fabless semiconductor ecosystem (Grand Alliance) that we have today. Cliff then took over the TSMC IP group before becoming the Senior Director at Design and Platform which included the PDK, IP, and other design enablement Groups inside TSMC. In 2011 Cliff was appointed TSMC’s Vice President of Research and Development. Clearly Dr. Cliff Hou is rising star in the semiconductor industry and it has been an honor to work with him.

Cliff was our choice to write the foreword to the book, “Fabless: The Transformation of the Semiconductor Industry” as he and TSMC led this transformation. The foreword alone is worth the price of the book and I can’t wait to get Cliff to sign a copy for me at #51DAC where he will be keynoting:

Industry Opportunities in the Sub-10nm Era
The human thirst for connectivity and experience, as enabled by the electronics industry and the ongoing march of Moore’s Law, has already brought, and will bring even more, profound changes in way we interact with the world and each other. This profound enhancement of the human experience enabled by constant mobile connectivity, the Cloud, and sensors, brought to an ever widening worldwide audience, will bring untold opportunity to all of us here at DAC.

All of these changes demand continued chip and wafer-based scaling to deliver the power and performance necessary to enable wondrous, new applications. In less than two years we’ll be in production at 10nm, and shortly after 7nm, all made possible by a “Grand Alliance” of design ecosystem, equipment and material suppliers. At the same time, a new paradigm is being realized: heterogeneous silicon integration combining chips from multiple process technologies with 3D packaging to deliver compelling economics for a “System in a Si Superchip.”

New design techniques will be required for those applications becoming reality, including how 10nm, and 7nm will support those requirements, new manufacturing techniques, and the benefits they will provide. The introduction of 10nm and 7nm processes will alter today’s ecosystem while opening greater EDA and IP opportunities, and present new system and chip design challenges such as near threshold design, thermal and battery limitations, and 3D IC considerations.

IC designers, ecosystem providers and foundries have been committed to open innovation and mutually beneficial teamwork for many process technology generations, but success in the sub-10nm era will require unprecedented levels of collaboration and cooperation between all of us here at DAC. Our teamwork will drive industry progress, and the more we “collaborate to innovate,” the more successful our customers and all of us will become.

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Intel 14nm Delayed Again?

Intel 14nm Delayed Again?
by Daniel Nenni on 02-12-2014 at 9:00 am
Categories: Foundries, Intel Foundry, TSMC

From the sources in which I confirmed the last Intel 14nm delay, I just confirmed another. Intel 14nm is STILL having yield problems. Remember Intel bragging about 14nm being a full node and deriding TSMC because 16nm is “just” 20nm with FinFETs added? Judging by the graph, clearly FinFETs are not the problem here. Intel used a much more aggressive metal fabric to get better density which is challenging modern lithography methods.

“People in the trenches are usually in touch with impending changes early” ― Andrew S. Grove,Only the Paranoid Survive

Meanwhile, back at the fabless semiconductor ecosystem, 20nm is yielding ahead of schedule so TSMC will see revenue this quarter versus next. I would put the chances of TSMC realizing their forecast of 20nm providing 10% of 2014 revenue as being very good. Given the more cautious approach TSMC took to FinFETs, 16nm is also on track with tape-outs happening now. If all goes as planned, 16nm will ramp in 2015 as 20nm does in 2014.

TSMC expects 20nm to be 2% of Q2 2014 revenue so the ramp begins. Looking at the 28nm ramp, 20nm is expected to be 20-30% faster:

[LIST=1]

  • 28nm 2% Q4 2011
  • 28nm 5% Q1 2012
  • 28nm 7% Q2 2012
  • 28nm 13% Q3 2012

    Back to Intel; new Intel CEO Brian Krzanich committed 14nm for Q3 2013 which was later pushed out to Q1 2014 even though he held up a laptop at the Intel Developers Forum and boasted that 14nm was in fact on track. At an analyst meeting two months later he showed the slide above and said there were yield “challenges” that they are still working on. Well, from what I have heard, they are still working on it so the Intel 14nm ramp may be delayed yet again.

    The questions I have are: If this is true when will Intel disclose this new yield challenge? How much will it delay 14nm products? What about Altera? I’m sure delaying this type of bad news until the problem is fixed is best for damage control but I find this type of behavior not transparent and untrustworthy, just my opinion of course.

    Meanwhile the Intel pumping Seeking Alpha published an article, “Does Intel’s new CEO have what it takes?” This is pure entertainment. Thus far Intel management has made many mistakes that the author glossed over but have been covered in painful detail on SemiWiki. The lack of transparency started here with BK’s first conference call:

    Intel’s Q2 Conference Call
    Intel 14nm Delayed?
    Intel Is Continuing to Scale While Others Pause To Do FinFETs
    No Mention of 14nm at the 2013 Intel Developer Forum?
    Intel Really is Delaying 14nm Move-in. 450mm is Slipping Too. EUV, who knows?
    Intel Quark: Synthesizable Core But You Can’t Have It
    Intel Bay Trail Fail
    Yes, Intel 14nm Really is Delayed…And They Lost $600M on Mobile
    Intel’s Mea Culpa!
    Intel Bay Trail Fail II
    Intel Comes Clean on 14nm Yield!
    Intel is NOT Transparent Again!
    Why Intel 14nm is NOT a Game Changer!

    We write these articles from the trenches to set the record straight. We also write these articles as research for an upcoming book on Intel to chronicle the rise and fall and hopefully the rise again of the number one semiconductor company.

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    Designing an SoC with 16nm FinFET

    Designing an SoC with 16nm FinFET
    by Daniel Payne on 02-11-2014 at 9:35 pm
    Categories: Cadence, EDA, Foundries, TSMC

    IC designers contemplating the transition to 16nm FinFET technology for their next SoC need to be informed about design flow and IP changes, so TSMC teamed up with Cadence Design Systems today to present a webinar on that topic. I attended the webinar and will summarize my findings.

    Shown below is a 3D layout concept of an ideal FinFET transistor, followed by the actual manufactured device which is rotated 90 degrees from the layout:

    Continue reading “Designing an SoC with 16nm FinFET”

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    The Great Wall of TSMC

    The Great Wall of TSMC
    by Paul McLellan on 02-03-2014 at 5:27 pm
    Categories: Foundries, TSMC

    TSMC doesn’t just sell wafers, it sells trust. It’s the Colgate Ring of Confidence for fabless customers. This focus on trust started at the very beginning when Morris Chang founded TSMC over 25 years ago, and still today trust remains an essential part of their business.

    When TSMC started, the big thing it brought was that it was a pure play foundry. It had no product lines of its own. Foundry had existed before, but it was semiconductor companies selling excess capacity to each other. This meant that the buyer of wafers was always vulnerable to the seller company being successful and needing that capacity and they would get thrown out. And that was without even considering that companies might be buying wafers from a competitor, sending them masks of their crown-jewels and trusting that nobody would try and reverse engineer anything.

    So when TSMC started, it brought the confidence that TSMC wasn’t going to suddenly stop supplying wafers since they needed the capacity for themselves, nor that TSMC was competing with them in the same end-markets. That is not to say that there never have been capacity issues: TSMC cannot afford to build excess capacity “just in case” any more than anyone else, so when businesses take off better than forecast or some other event happens, wafers can end up on allocation just as has always been the case in semiconductor, an inherently cyclical business.

    Not competing with its customers remains the case today (as, to be fair, it does for GlobalFoundries, SMIC, Jazz and other pure-play foundries). But it is not the case for Samsung, which is in the slightly bizarre situation of having Apple as its largest foundry customer while competing with it as the volume leader in the mobile market (and never mind the lawsuits). Samsung is large diversified conglomerate, almost a lot of different companies all using the Samsung brand-name. Samsung makes all the retina displays for iPhone too, and doesn’t even use them themselves. They are a huge memory supplier. Apple is rumored to be moving from Samsung to TSMC for its next application processor (presumably to be called A8).

    Intel has made a lot of noise about entering the foundry business but the only significant company that has been announced is Altera. And there are even rumors that they are thinking of going back to TSMC. But a company like Altera using Intel for its high end FPGA products might need 1000 wafers a month when a fab has a capacity of 50-100K wafers a month. It won’t “fill the fab”. It needs to get an Apple or a Qualcomm or an nVidia for that. But at least Altera can be confident that no matter how successful Intel’s other businesses are, at those volumes they are unlikely to be squeezed out, the amount of capacity they need is in the noise.

    The other area that foundries have had to invest is to create an ecosystem around them of manufacturing equipment and material suppliers, IP and EDA companies. This grand alliance has made a huge investment in R&D. In aggregate, it has invested more than any single IDM. As a result the Grand Alliance has produced more innovation in high performance, lower power, lower cost than any single IDM.

    At a modern process node deep cooperation is required. It is not possible for everything to be done serially: get the process ready, get the tools working on a stable process, use the tools to build the IP, start customer designs using the IP and the tools, ramp to volume. Everything has to happen almost simultaneously. This requires an even greater sense of trust among everyone involved, and the fact that changing PDKs means changing IP means redoing designs means inevitably an increased investment too.

    So TSMC has a competitive edge, the great wall of TSMC to keep out the barbarian hordes:

    • it sells confidence and trust, not just wafers
    • it does not compete with its customers
    • it has orchestrated a grand alliance to create an ecosystem around its factories that has made a bigger R&D investment than any single IDM.


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